Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate and an array layer. The array layer comprises a plurality of pixel circuits. Each pixel circuit comprises a driving transistor and a connection signal line. The connection signal line comprises a first connection signal line and a second connection signal line which extend along a first direction. In the same pixel circuit, the distance between the orthogonal projection of the second connection signal line on the substrate and the orthogonal projection of the first connection signal line on the substrate along a second direction is a first distance. In the adjacent two pixel circuits, the distance between the orthogonal projection of the second connection signal line on the substrate and the orthogonal projection of the first connection signal line on the substrate in the other pixel circuit along the second direction is a second distance. The absolute value of the difference between the first distance and the second distance is less than or equal to a preset difference value. The generation of the coupling capacitance between the second connection signal line and the adjacent first connection signal line is reduced, and the crosstalk problem is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic products, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the development of electronic technology, electronic products have pervaded people's lives. Display technology is a crucial technology in electronic technology, and is related to the display effect of electronic products.

[0003] In the field of display technology, display panels are divided into two categories: organic light-emitting display panels and liquid crystal display panels. Both types of display panels include an array substrate, and the light-emitting display of the light-emitting unit of the display panel is controlled through the pixel circuit and signal line provided on the array substrate.

[0004] However, due to the structure of the existing array substrate, coupling capacitance is easily generated between the signal lines, causing crosstalk problems and affecting the display effect of the display panel.

[0005] Therefore, there is an urgent need for a new array substrate, display panel and display device. SUMMARY

[0006] Embodiments of the present application provide an array substrate, a display panel and a display device. By making the distance between the second connection signal line and the two adjacent first connection signal lines in the second direction less than or equal to a preset difference value, the generation of coupling capacitance between the second connection signal line and the adjacent first connection signal line is reduced, and the crosstalk problem is improved.

[0007] Embodiments of the present application provide an array substrate, a display panel and a display device. By making the distance between the second connection signal line and the two adjacent first connection signal lines in the second direction less than or equal to a preset difference value, the generation of coupling capacitance between the second connection signal line and the adjacent first connection signal line is reduced, and the crosstalk problem is improved.

[0008] According to an aspect of the present application, the preset difference is less than or equal to 10% of any one of the first distance and the second distance.

[0009] According to an aspect of the present application, the preset difference ranges from 0 μm to 0.3 μm.

[0010] According to an aspect of the present application, the first distance is equal to the second distance; preferably, the first distance and the second distance range from 1 μm to 3 μm.

[0011] According to an aspect of the present application, the array layer further comprises a storage capacitor, the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is arranged in the same layer as the gate of the driving transistor, and the second electrode plate is arranged on the side of the first electrode plate away from the substrate; the second connection signal line is electrically connected with the storage capacitor.

[0012] According to an aspect of the present application, in the direction perpendicular to the plane where the substrate is located, the array layer comprises a semiconductor layer, a first metal layer, a second metal layer and a third metal layer which are arranged in a stack and are insulated from each other; the first connection signal line is at least partially arranged in the same layer as the semiconductor layer, the gate of the driving transistor is arranged in the same layer as the first metal layer, the second electrode plate is arranged in the same layer as the second metal layer, and the second connection signal line is at least partially arranged in the same layer as the third metal layer.

[0013] According to an aspect of the present application, the array substrate further comprises a fourth metal layer arranged on the side of the third metal layer away from the substrate; the array substrate further comprises a data signal line extending in the first direction, the first connection signal line is electrically connected with the data signal line, and the data signal line is arranged in the same layer as the fourth metal layer.

[0014] According to an aspect of the present application, the first connection signal line and the second connection signal line are both linear in the projection on the substrate.

[0015] Another aspect of the present application further provides a display panel comprising the array substrate as described in any one of the above embodiments.

[0016] Still another aspect of the present application further provides a display device comprising the display panel as described in any one of the above embodiments.

[0017] Compared with the prior art, the array substrate provided by the embodiment of the present application comprises a substrate and an array layer, and the pixel circuit of the array layer comprises a driving transistor and a connection signal line. Since the first connection signal line needs to be connected with the source or the drain of the driving transistor, and the second connection signal line needs to be connected with the gate, that is, the first connection signal line and the second connection signal line transmit different voltage signals. In the embodiment, the distance between the second connection signal line and the two adjacent first connection signal lines in the second direction is less than or equal to a preset difference, that is, the absolute value of the difference between the first distance and the second distance is less than or equal to a preset difference, so as to avoid the distance between the second connection signal line and the adjacent first connection signal line being too close, reduce the generation of the coupling capacitance between the second connection signal line and the adjacent first connection signal line, improve the crosstalk problem, avoid the voltage signal of the first connection signal line and / or the second connection signal line jumping due to the crosstalk, and improve the display effect of the array substrate when applied to the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0019] Figure 1 is a structural schematic diagram of the array substrate provided by an embodiment of the present application;

[0020] Figure 2 is Figure 1 is a partial enlarged view provided by an embodiment in B of the present application;

[0021] Figure 3 is Figure 1 is a film layer structure diagram provided by an embodiment in A-A of the present application;

[0022] Figure 4 is a pixel circuit diagram provided by an embodiment of the present application.

[0023] In the drawings:

[0024] 1 - substrate; 2 - array layer; L1 - first connection signal line; L2 - second connection signal line; G - gate; S - source; D - drain; Y - active layer; M1 - first metal layer; M2 - second metal layer; M3 - third metal layer; M4 - fourth metal layer; C - storage capacitor; C1 - first electrode plate; C2 - second electrode plate; T1 - first transistor; T2 - second transistor; T3 - third transistor; T4 - fourth transistor; T5 - fifth transistor; T6 - sixth transistor; T7 - seventh transistor; VDATA - data signal line; VREF - reference voltage signal terminal; EM - light emission control signal terminal; S1 - first scan signal terminal; S2 - second scan signal terminal; S3 - third scan signal terminal; VDD - first power voltage input terminal; VSS - second power voltage input terminal; Y - first direction; X - second direction. DETAILED DESCRIPTION

[0025] The features and exemplary embodiments of the various aspects of the present application will be described below in detail, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of these specific details for those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0026] It should be noted that, in this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0027] It should be understood that when describing the structure of a component, when a layer, a region is referred to as being "on" or "above" another layer, another region, it can mean being directly on or above another layer, another region, or containing other layers or regions between it and another layer, another region. And if the component is turned over, the layer, the region will be "under" or "below" the other layer, the other region.

[0028] Various modifications and changes can be made to the application in matters of construction and arrangement of parts without departing from the scope of the application as defined in the claims. It is intended that the application cover all such modifications and changes as fall within the scope of the claims (the technical solutions claimed in the patent application) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other if there is no contradiction.

[0029] The present application provides an array substrate, a display panel and a display device, which will be described below in conjunction with the accompanying drawings Figures 1 to 4 The embodiments of the array substrate, the display panel and the display device will be described.

[0030] Please refer to Figures 1 to 3 The present application provides an array substrate, which comprises a substrate 1 and an array layer 2 arranged on one side of the substrate 1. The array layer 2 comprises a plurality of pixel circuits, each of which comprises a driving transistor and a connection signal line. The driving transistor comprises a gate G, a source S and a drain D. The connection signal line comprises a first connection signal line L1 and a second connection signal line L2, which extend along a first direction Y. The first connection signal line L1 is electrically connected to the source S or the drain D, and the second connection signal line L2 is electrically connected to the gate G. In the same pixel circuit, along a second direction X, the distance between the orthogonal projection of the second connection signal line L2 on the substrate 1 and the orthogonal projection of the first connection signal line L1 on the substrate 1 is a first distance d1. The second direction X is perpendicular to the first direction Y. In the adjacent two pixel circuits, along the second direction X, the distance between the orthogonal projection of the second connection signal line L2 on the substrate 1 and the orthogonal projection of the first connection signal line L1 on the substrate 1 in the other pixel circuit is a second distance d2. The absolute value of the difference between the first distance d1 and the second distance d2 is less than or equal to a preset difference value.

[0031] The array substrate provided by the embodiment of the present application comprises a substrate 1 and an array layer 2, and the pixel circuit of the array layer 2 comprises a driving transistor and a connection signal line. Since the first connection signal line L1 needs to be connected with the source S or the drain D of the driving transistor, and the second connection signal line L2 needs to be connected with the gate G, the first connection signal line L1 and the second connection signal line L2 transmit different voltage signals. In the embodiment, the distance between the second connection signal line L2 and the adjacent two first connection signal lines L1 in the second direction X is less than or equal to a preset difference, i.e. the absolute value of the difference between the first distance d1 and the second distance d2 is less than or equal to a preset difference, so as to avoid the distance between the second connection signal line L2 and the adjacent first connection signal line L1 being too close, reduce the generation of coupling capacitance between the second connection signal line L2 and the adjacent first connection signal line L1, improve the crosstalk problem, avoid the voltage signal of the first connection signal line L1 and / or the second connection signal line L2 jumping due to the crosstalk, and improve the display effect of the array substrate when applied to a display panel.

[0032] It can be understood that, since the first connection signal line L1 and the second connection signal line L2 transmit different voltage signals, when the distance between the first connection signal line L1 and the second connection signal line L2 is too close, the two will form a capacitor structure as an electrode plate respectively, thereby generating coupling capacitance.

[0033] Since the size of the coupling capacitance is inversely proportional to the distance between the first connection signal line L1 and the second connection signal line L2, i.e. the greater the distance between the first connection signal line L1 and the second connection signal line L2, the smaller the generated coupling capacitance is. Therefore, the embodiment of the present application limits the difference between the first distance d1 and the second distance d2 to ensure that the distance between the second connection signal line L2 and any adjacent first connection signal line L1 is large enough. The greater the distance between the second connection signal line L2 and the first connection signal line L1, the smaller the coupling capacitance generated between the second connection signal line L2 and the first connection signal line L1, thereby improving the crosstalk problem.

[0034] In the embodiment, along the second direction X, the second connection signal line L2 is arranged between the adjacent two first connection signal lines L1. For example, when the first connection signal line L1 is arranged on the left side of the second connection signal line L2 in the same pixel circuit, the other first connection signal line L1 in the adjacent other pixel circuit is arranged on the right side of the second connection signal line L2. The first distance d1 is the distance between the second connection signal line L2 and the first connection signal line L1 on the left side of the second connection signal line L2, and the second distance d2 is the distance between the second connection signal line L2 and the first connection signal line L1 on the right side of the second connection signal line L2. Therefore, the first distance d1 and the second distance d2 need to be adjusted to avoid the distance between the second connection signal line L2 and the first connection signal line L1 being too close.

[0035] In some optional embodiments, considering the machining precision and the position forming error, the preset difference is less than or equal to 10% of any one of the first distance d1 and the second distance d2.

[0036] It is found by the inventors that when the preset difference is set to be in the range of less than or equal to 10% of any one of the first distance d1 and the second distance d2, the coupling capacitance generated between the first connection signal line L1 and the second connection signal line L2 is relatively small, and the improvement effect on the crosstalk problem is more obvious. Optionally, the first distance d1 and the second distance d2 are in the range of 1 μm to 3 μm, for example, when the first distance d1 and the second distance d2 are equal to 1 μm, and the preset difference is in the range of 0 μm to 0.1 μm; or when the first distance d1 and the second distance d2 are equal to 3 μm, and the preset difference is in the range of 0 μm to 0.3 μm, and there is no special limitation, which can be selected according to the actual size.

[0037] It can be understood that when the preset difference is equal to 0 μm, the first distance d1 is equal to the second distance d2, that is, along the second direction X, the second connection signal line L2 is located in the middle of the two adjacent first connection signal lines L1, which maximally reduces the generation of the coupling capacitance, improves the crosstalk problem between the second connection signal line L2 and the two adjacent first connection signal lines L1, and improves the display effect.

[0038] The substrate 1 can be a hard substrate such as a glass substrate, or a flexible substrate, and the material thereof can be polyimide, polystyrene, polyethylene terephthalate, poly-p-xylylene, polyether sulfone or polyethylene naphthalate. The substrate 1 is mainly used to support the devices arranged thereon.

[0039] In some optional embodiments, the array layer 2 further comprises a storage capacitor C, the storage capacitor C comprises a first electrode plate C1 and a second electrode plate C2, the first electrode plate C1 is arranged in the same layer as the gate electrode G of the driving transistor, and the second electrode plate C2 is arranged on the side of the first electrode plate C1 away from the substrate 1; the second connection signal line L2 is electrically connected with the storage capacitor C.

[0040] It should be noted that the pixel circuit generally comprises a driving module, a storage module, a data writing module, a light emitting control module and an initialization module.

[0041] The driving module can be used to provide a driving current to the light emitting element of the display panel. The driving module comprises the driving transistor described above, and specifically, whether the driving current can flow to the light emitting element through the driving module can be controlled by controlling the turn-on and turn-off of the driving module.

[0042] The storage module is connected with the driving module and has a function of storing electric energy. Optionally, the storage module includes the storage capacitor C. The storage module can be used to maintain the potential of the control terminal of the driving module. Specifically, during a charging stage in the driving process of the pixel driving circuit on the pixel unit, the storage module can be charged. During a read-write-light-emitting stage in the driving process, the storage module can maintain the potential of the control terminal of the driving module by using the voltage charged in the charging stage, that is, the second connection signal line L2 is used to transmit the voltage in the storage capacitor C to the gate G of the driving transistor.

[0043] The data writing module is connected with the driving module and the storage module and is used to write the data signal into the control terminal of the driving module. Specifically, the data writing module is connected with the data signal line VDATA and the first scanning signal terminal S1. The data signal line VDATA is used to provide the data signal. The first scanning signal terminal S1 is used to provide the first scanning signal. During the charging stage in the driving process, the data writing module charges the storage module by using the data signal under the control of the first scanning signal through the driving module. During the read-write-light-emitting stage in the driving process, the storage module maintains the potential of the control terminal of the driving module by using the voltage charged in the charging stage, which is equivalent to writing the data signal into the control terminal of the driving module.

[0044] The light-emitting control module is connected with the light-emitting element, the driving module and the power voltage input terminal and is used to control the light-emitting element to emit light. Specifically, the light-emitting control module is connected with the light-emitting control signal terminal EM and the first power voltage input terminal VDD. The light-emitting control signal terminal EM is used to provide the light-emitting control signal. The first power voltage input terminal VDD is used to provide the high-level signal. During the read-write-light-emitting stage in the driving process, the light-emitting control module is turned on under the control of the light-emitting control signal and can transmit the driving current generated by the high-level signal to the light-emitting element, so that the light-emitting element emits light.

[0045] The initialization module is connected with the driving module and the light-emitting element and is respectively used to initialize the control terminal of the driving module and the anode of the light-emitting element. Specifically, the initialization module is connected with the reference voltage signal terminal VREF and the second scanning signal terminal S2. The reference voltage signal terminal VREF is used to provide the reference voltage signal, and the reference voltage signal is used as the initialization signal. In some examples, the voltage of the reference voltage signal is negative. The second scanning signal terminal S2 is used to provide the second scanning signal. During the initialization stage in the driving process, the initialization module is turned on under the control of the second scanning signal, on one hand, the reference voltage signal is used to initialize the control terminal of the driving module, and on the other hand, the voltage of the reference voltage signal is charged into the storage module and the anode of the light-emitting element, so as to initialize the anode of the light-emitting element.

[0046] Please refer to Figure 4Optionally, the pixel circuit can adopt a 7T1C circuit, where "T" refers to a TFT (Thin Film Transistor), and "C" refers to a capacitor. Optionally, the driving module includes a first transistor T1, which is a driving transistor in the pixel driving circuit; the storage module includes a storage capacitor C; the data writing module includes a second transistor T2 and a third transistor T3; the light-emitting control module includes a fifth transistor T5 and a sixth transistor T6; and the initialization module includes a fourth transistor T4 and a seventh transistor T7.

[0047] The control end of the first transistor T1 is connected with the second end of the storage capacitor C, the second end of the third transistor T3, and the second end of the fourth transistor T4. The first end of the first transistor T1 is connected with the second end of the second transistor T2. The second end of the first transistor T1 is connected with the first end of the third transistor T3 and the first end of the sixth transistor T6. The first end of the first transistor T1 is an input end of the driving module, the second end of the first transistor T1 is an output end of the driving module, the first end of the first transistor T1 is the source S of the driving transistor, the second end of the first transistor T1 is the drain D of the driving transistor, and the control end of the first transistor T1 is the gate G of the driving transistor.

[0048] The control end of the second transistor T2 is connected with the second scan signal end S2. The first end of the second transistor T2 is connected with the data signal line VDATA. The second end of the second transistor T2 is connected with the first end of the first transistor T1.

[0049] The control end of the third transistor T3 is connected with the second scan signal end S2. The first end of the third transistor T3 is connected with the first end of the sixth transistor T6. The second end of the third transistor T3 is connected with the second end of the storage capacitor C and the second end of the fourth transistor T4.

[0050] The control end of the fourth transistor T4 is connected with the first scan signal end S1. The first end of the fourth transistor T4 is connected with the reference voltage signal end VREF. The second end of the fourth transistor T4 is connected with the second end of the storage capacitor C.

[0051] The control end of the fifth transistor T5 is connected with the light-emitting control signal end EM. The first end of the fifth transistor T5 is connected with the first end of the storage capacitor C, and the second end of the fifth transistor T5 is connected with the first end of the first transistor T1.

[0052] The control end of the sixth transistor T6 is connected with the light-emitting control signal end EM. The first end of the sixth transistor T6 is connected with the second end of the first transistor T1. The second end of the sixth transistor T6 is connected with the anode of the light-emitting element.

[0053] The control terminal of the seventh transistor T7 is connected to the third scan signal terminal S3. The first terminal of the seventh transistor T7 is connected to the reference voltage signal terminal VREF. The second terminal of the seventh transistor T7 is connected to the anode of the light-emitting element D1. The second terminal of the seventh transistor T7 is the first output terminal of the initialization module.

[0054] A first terminal of the storage capacitor C is connected to the first power voltage input terminal VDD.

[0055] The cathode of the light emitting element D1 is connected to the second power supply voltage input terminal VSS. The second power supply voltage input terminal VSS is used to provide a low level signal. In some examples, the second power supply voltage input terminal can be a ground terminal, which is not limited here.

[0056] like Figure 3 As shown, in some optional embodiments, along a direction perpendicular to the plane of the substrate 1, the array layer 2 includes a semiconductor layer, a first metal layer M1, a second metal layer M2, and a third metal layer M3 that are stacked and insulated from each other; the first connecting signal line L1 is at least partially arranged in the same layer as the semiconductor layer, the gate G of the driving transistor is arranged in the same layer as the first metal layer M1, the second electrode plate C2 is arranged in the same layer as the second metal layer M2, and the second connecting signal line L2 is at least partially arranged in the same layer as the third metal layer M3.

[0057] In this embodiment, although the first connection signal line L1 and the second connection signal line L2 are located in different film layers, since both the first connection signal line L1 and the second connection signal line L2 transmit voltage signals, and the voltage of the gate signal transmitted by the second connection signal line L2 is relatively large, when the distance between the first connection signal line L1 and the second connection signal line L2 is too close, capacitive coupling will occur between the two, thereby causing crosstalk. Therefore, the present invention needs to adjust the distance between the first connection signal line L1 and the second connection signal line L2 to reduce the capacitive coupling between the first connection signal line L1 and the second connection signal line L2 and improve the crosstalk problem.

[0058] It should be noted that the semiconductor layer in this embodiment can be made of P-si (low-temperature polycrystalline silicon), part of the semiconductor layer can be used to prepare the active layer Y of the driving transistor, and the first connecting signal line L1 is at least partially arranged in the same layer as the semiconductor layer. Specifically, the first connecting signal line L1 can be made using the same process as the semiconductor layer, and the first connecting signal line L1 and the semiconductor layer can use the same material to reduce production costs.

[0059] The first metal layer M1, the second metal layer M2 and the third metal layer M3 can be made of an opaque metal with low resistivity, such as copper, aluminum, molybdenum, titanium, etc. The gate electrode G of the driving transistor is arranged in the same layer as the first metal layer M1, that is, the gate electrode G of the driving transistor can be made by the same process as the first metal layer M1 and can be made of the same material. Similarly, the second electrode plate C2, the second metal layer M2 and the third metal layer M3 can also be formed by the same process, respectively, and are not particularly limited.

[0060] Optionally, the array substrate further comprises a fourth metal layer M4 arranged on the side of the third metal layer M3 away from the substrate 1; and the array substrate further comprises a data signal line extending along the first direction Y, the first connection signal line L1 is electrically connected to the data signal line, and the data signal line is arranged in the same layer as the fourth metal layer M4.

[0061] It can be understood that, since the first connection signal line L1 is connected to the source electrode S of the driving transistor and the data signal line, the first connection signal line L1 is used to transmit the data signal of the data signal line to the source electrode S of the driving transistor, and the first connection signal line L1 and the data signal line can be connected through a via hole.

[0062] In some optional embodiments, the extension trajectories of the orthographic projections of the first connection signal line L1 and the second connection signal line L2 on the substrate 1 are straight lines.

[0063] Considering that the first connection signal line L1 and the second connection signal line L2 extend along the first direction Y as a whole, when the extension trajectories of the orthographic projections of the first connection signal line L1 and the second connection signal line L2 on the substrate 1 are straight lines, the first connection signal line L1 and the second connection signal line L2 are arranged in parallel, along the second direction X, the distance between the first connection signal line L1 and the second connection signal line L2 is equal everywhere, which facilitates adjustment of the first distance d1 and the second distance d2 between the first connection signal line L1 and the two adjacent second connection signal lines L2. Of course, according to actual layout setting needs, the extension trajectories of the orthographic projections of the first connection signal line L1 and the second connection signal line L2 on the substrate 1 can also be curves, broken lines, etc., and are not particularly limited.

[0064] The application further provides a display panel comprising the array substrate in any of the above embodiments.

[0065] The display panel in the embodiments of the application can include a panel with a display function of a mobile phone, a tablet, a palm computer, an IPAD, a wearable device, an electronic photo frame, electronic paper and the like, and is not limited herein.

[0066] The application further provides a display device comprising the display panel in any of the above embodiments.

[0067] Therefore, the display device provided by the embodiments of the present application has the technical effects of the technical solutions of the display panel in any of the above embodiments, and the same or corresponding structures and explanations of terms are not described herein again. The display device provided by the embodiments of the present application can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: a television, a notebook computer, a desktop display, a tablet computer, a digital camera, a smart bracelet, smart glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal, and the like, and the embodiments of the present application are not specially limited to any of the above.

[0068] The above is merely a specific implementation of the present application, and those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, modules and units can refer to the corresponding processes in the foregoing method embodiments, which are not described herein again. It should be understood that the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application.

[0069] It should be further noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in an order different from the embodiments, or several steps can be performed simultaneously.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; an array layer arranged on one side of the substrate, the array layer comprising a plurality of pixel circuits, each of the pixel circuits comprising a driving transistor and a connection signal line, the driving transistor comprising a gate, a source and a drain, the connection signal line comprising a first connection signal line and a second connection signal line extending at least partially along a first direction, the first connection signal line being electrically connected to the source or the drain, and the second connection signal line being electrically connected to the gate; in the same pixel circuit, along a second direction perpendicular to the first direction, a distance between a projection of the second connection signal line on the substrate and a projection of the first connection signal line on the substrate is a first distance; in two adjacent pixel circuits, along the second direction, a distance between a projection of the second connection signal line on the substrate and a projection of the first connection signal line on the substrate in the other pixel circuit is a second distance; an absolute value of a difference between the first distance and the second distance is less than or equal to a preset difference value.

2. The array substrate of claim 1, wherein, The preset difference value is less than or equal to 10% of any one of the first distance and the second distance.

3. The array substrate of claim 2, wherein, The preset difference value is in a range of 0 μm to 0.3 μm.

4. The array substrate of claim 1, wherein, The first distance is equal to the second distance.

5. The array substrate of claim 1, wherein, The first distance and the second distance are in a range of 1 μm to 3 μm.

6. The array substrate of claim 1, wherein, The array layer further comprises a storage capacitor, the storage capacitor comprising a first electrode plate and a second electrode plate, the first electrode plate being arranged in the same layer as the gate of the driving transistor, and the second electrode plate being arranged on a side of the first electrode plate away from the substrate; the second connection signal line is electrically connected to the storage capacitor.

7. The array substrate of claim 6, wherein, In a direction perpendicular to a plane in which the substrate is arranged, the array layer comprises a semiconductor layer, a first metal layer, a second metal layer and a third metal layer arranged in a stack and insulated from each other; the first connection signal line is arranged at least partially in the same layer as the semiconductor layer, the gate of the driving transistor is arranged in the same layer as the first metal layer, the second electrode plate is arranged in the same layer as the second metal layer, and the second connection signal line is arranged at least partially in the same layer as the third metal layer.

8. The array substrate of claim 7, wherein, The array substrate further comprises a fourth metal layer arranged on a side of the third metal layer away from the substrate; the array substrate further comprises a data signal line extending along the first direction, the first connection signal line is electrically connected to the data signal line, and the data signal line is arranged in the same layer as the fourth metal layer.

9. The array substrate of claim 1, wherein, The projection of the first connection signal line on the substrate and the projection of the second connection signal line on the substrate both extend along straight lines.

10. A display panel, characterized by, The display panel comprises the array substrate according to any one of claims 1 to 9.

11. A display device comprising: The display panel comprises the array substrate according to claim 10.

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