Update the metadata prediction table using the re-prediction pipeline.

Abstract

Aspects of the present invention include a computer-implemented method for updating a metadata prediction table. The computer-implemented method includes establishing a prediction in the metadata prediction table of how an instruction set will be resolved and identifying when the instruction set is completed. The computer-implemented method further includes: upon completion of the instruction set, determining whether a prediction update queue (PUQ) associated with the instruction set indicates that the instruction set is resolved relative to the prediction in one of a variety of prohibited methods; and, based on the PUQ indicating that the instruction set is resolved in one of the variety of prohibited methods, determining that the metadata prediction table is a candidate for update.

Description

Technical Field

[0001] The present invention relates generally to predictive pipelines, and more specifically, to a method for updating a metadata prediction table using a re-predictive pipeline. Background Technology

[0002] Instruction pipelines in computer processors improve instruction execution throughput by processing instructions through multiple pipeline stages, where these stages can operate on different instructions in the instruction stream in parallel. Conditional branch instructions can cause pipeline stalls if the processor waits until a conditional branch instruction in the instruction stream is resolved in the execution stage of the pipeline before fetching the next instruction in the instruction fetch stage. A branch predictor can attempt to guess whether a conditional branch is taken, and may also include branch target prediction, which attempts to guess the target of a taken conditional or unconditional branch before calculating the branch target by decoding and executing the instruction itself. The branch target can be a computed address based on an offset and / or an indirect reference via a register.

[0003] A branch target buffer (BTB) can be used to predict the target of a predicted taken branch instruction based on the address of the branch instruction. Predicting the target of a branch instruction prevents pipeline stalling by not waiting for the branch instruction to reach the execution stage of the pipeline to calculate the branch target address. By performing branch target prediction, the branch target instruction decoding can be performed in the same loop or in a loop after the branch instruction, instead of having multiple bubble / empty loops between the branch instruction and the predicted target of the taken branch instruction. Other branch prediction components that can be included in the BTB or implemented separately include a branch history table (BHT) and a pattern history table (PHT). The branch history table can predict the direction of a branch (take or not take) based on the branch address. The pattern history table can assist in predicting the direction of a branch based on the pattern of branches encountered leading to the given branch to be predicted. Summary of the Invention

[0004] Embodiments of the present invention relate to a computer-implemented method for updating a metadata prediction table.

[0005] Non-limiting examples include establishing a prediction of how an instruction set will be resolved in a metadata prediction table and identifying when the instruction set is completed. The computer-implemented method further includes: upon instruction set completion, determining whether a prediction update queue (PUQ) associated with the instruction set indicates that the instruction set is resolved relative to the prediction in one of a number of prohibited methods; and, based on the PUQ indicating that the instruction set is resolved in one of the prohibited methods, determining that the metadata prediction table is a candidate for update.

[0006] Other embodiments of the present invention implement the features of the above-described method in computer systems and computer program products.

[0007] Additional technical features and advantages are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein, and these embodiments and aspects are considered part of the claimed subject matter. For a better understanding, refer to the detailed description and accompanying drawings. Attached Figure Description

[0008] The details of the exclusive rights described herein are specifically pointed out and explicitly claimed in the appended claims. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A system illustrating a computer-implemented method for performing chip design according to one or more embodiments of the present invention;

[0010] Figure 2 This is a schematic diagram of a system for updating branch prediction according to one or more embodiments of the present invention;

[0011] Figure 3 This is a schematic diagram illustrating the operation of a Weak Prediction Update Queue (WeakPUQ) according to one or more embodiments of the present invention;

[0012] Figure 4 This is a schematic diagram illustrating the operation of a branch error PUQ (BrWrgPUQ) according to one or more embodiments of the present invention;

[0013] Figure 5 This is a flowchart illustrating the operation of WeakPUQ and BrWrgPUQ according to one or more embodiments of the present invention;

[0014] Figure 6 This is a flowchart illustrating the operation of a re-predictive pipeline according to one or more embodiments of the present invention;

[0015] Figure 7A This is a flowchart illustrating a computer-implemented method for updating a metadata prediction table according to one or more embodiments of the present invention;

[0016] Figure 7B This is a flowchart illustrating a computer-implemented method for updating a metadata prediction table according to one or more other embodiments of the present invention;

[0017] Figure 8 This is a schematic diagram of a computer system for performing a method for updating branch prediction according to one or more embodiments of the present invention; and

[0018] Figure 9 This is a process flow of a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention.

[0019] The figures depicted herein are illustrative. Many variations can be made to the figures or operations described herein without departing from the spirit of the invention. For example, actions can be performed in a different order, or actions can be added, deleted, or modified. Furthermore, the term "coupling" and its variations describe a communication path between two elements and do not imply a direct connection between the elements without intermediate elements / connections. All such variations are considered part of the specification. Detailed Implementation

[0020] One or more embodiments of the present invention provide an accurate and efficient method for determining whether any prediction structures used to create predictions for branches need to be updated. A set of structures is created to help determine whether a particular execution pipeline path for a branch needs an update to the prediction structure for that branch. The use of this structure and a read-before-write model for completion-time updates removes much of the logic needed for tracking and applying speculative updates; thus reducing latency in the critical prediction-time pipeline used to bootstrap instruction fetching and decoding streams.

[0021] For example, branch data such as direction and target address is important for the performance of general-purpose computers (e.g., mainframes) because it allows predictive structures to act ahead of the current instruction, preparing the machine for where it will need to go in the future. When these predictive structures encounter a branch, they store the result of the branch's completion in multiple different structures. This allows the machine to more accurately determine what the branch will do in the future when predicting the branch again, using the results of the branch's previous execution. Thus, the ability to accurately update the data in these structures will improve the machine's performance in a given area.

[0022] Furthermore, branching is a very common instruction in computing machines. Because branching is so common, it is important to have a way to determine whether a branch needs to have its metadata updated. Previously, this was done by storing data from when the branch was predicted to when it was completed. However, this is expensive in terms of silicon area and sometimes power usage, especially when transmitting that data, as prediction and completion can be separated by many cycles. For example, tracking the age of speculative entries associated with the update mechanism to attempt to predict whether a branch needs to be updated based on the assumption that the prediction is correct and then tracking information about branches passing through the pipeline.

[0023] A drawback of previous solutions was that when a single branch was executed rapidly and consecutively several times, it was often impossible to know from the branch's related channels that previous branches had updated the prediction structure. In previous solutions, the update mechanism was determined based on prediction time information and how the branch was completed. Because previous solutions did not consider any updates that occurred between when a branch was predicted and when it was completed, those updates were excessive and potentially inaccurate. An example of inaccurate updates might be that if there are multiple instances of a branch updating its strength, causing it to change from an initial weak state to a strong state, but the final instance of the branch receives a branch error, this branch error will not see the updated strong state, but instead see an outdated and incorrect weak state from the initial prediction, and make an incorrect update based on seeing the outdated weak state.

[0024] Another drawback is that the methods used to determine whether a branch needs an update are often inaccurate. In these cases, writing to the array and / or unnecessary updates consumes additional power, slowing down the pipeline from making the necessary updates.

[0025] Another drawback of the previous solution was storing and carrying branch data from the prediction time up to the completion time. This meant that when a branch was resolved, the prediction time information could be used to determine what the update should be. This was costly because a large amount of information needed to be maintained for each branch. In many cases, updates were unnecessary, so tracking was pointless.

[0026] One or more embodiments of the present invention address one or more of the aforementioned disadvantages of the prior art by providing a set of side structures or predictive update queues (PUQs) that act as a funnel to determine whether a branch needs to go through the update pipeline based on how the branch is predicted and how the branch completes. There is a finite number of reasons why a branch might need to undergo update logic before its completion time. Several of these reasons can be detected at completion time by combining minimal data tracking with the results of the branch execution. These reasons will always require an update for that branch, and therefore these reasons are always experienced to make the update occur. For the remaining reasons, the PUQ is broken down by reason, and each of the PUQs is checked when the branch completes. A match with any of the PUQs indicates that the branch needs to proceed to the update pipeline. The update pipeline will re-predict the branch at completion time by reading data from the predictive structures and combining it with the completion results from the branch, to determine the correct state to update to. By going through the same process of how the branch is predicted and how it is completed, the update pipeline can determine the correct update without carrying large amounts of data through the entire pipeline from prediction to completion.

[0027] Therefore, this invention reduces the logic complexity during the prediction pipeline and potentially reduces the silicon area required to trace additional information through the pipeline. Furthermore, the PUQ structure reduces the amount of data required to perform pipeline tracing. The PUQ structure only needs to match the IA of a given branch to indicate that the branch needs to undergo an update pipeline, regardless of how the branch is completed. Additionally, PUQ allows for the maintenance of branch information for branches that will require updates.

[0028] Using a repredictive pipeline eliminates the need to store all prediction timing information in the side architecture for pipeline tracking. Since the data undergoes a repredictive branch upon completion and learns how the branch completed, the pipeline knows what updates are needed. Consequently, almost all data tracking from prediction time to completion can be removed, potentially reducing the overall silicon area and power usage of the core.

[0029] Figure 1 This is a block diagram of a system 100 for performing a computer-implemented method of updating branch prediction according to an embodiment of the present invention. System 100 includes processing circuitry 110 for generating a design that will ultimately be manufactured into an integrated circuit 120. The steps involved in the manufacture of the integrated circuit 120 are well-known and are briefly described herein. According to an embodiment of the present invention, once the physical layout is finalized, the finalized physical layout is provided to a foundry to facilitate optimization of the routing plan. Based on the finalized physical layout, a mask is generated for each layer of the integrated circuit. The wafer is then processed in mask order. The processing includes photolithography and etching. This will be referred to... Figure 9 Further discussion.

[0030] See Figure 2 It provides a system 200 for updating branch predictions, and can be used in... Figure 8 It is executed or manifested in the computer system 800. For example... Figure 2 As shown, system 200 includes a branch target buffer (BTB) 201, a pattern history table (PHT) 202, a change target buffer (CTB) 203, and a perceptron 204. System 200 also includes prediction logic 210, completion logic 211, a weakPUQ 220, a branch error PUQ (BrWrgPUQ) 230, a completion write queue 214, and a re-prediction pipeline 240. Prediction logic 210 communicates with the predicted bundle unit 212 and the weakPUQ 220. Completion logic 211 communicates with the weakPUQ 220, the BrWrgPUQ 230, the completion group unit 213, and the completion write queue 214. The re-prediction pipeline 240 is communicatively interposed between the completion write queue 214 and BTB 201, PHT 202, CTB 203, and perceptron 204.

[0031] When a branch is predicted by BTB 201 or any auxiliary structure (i.e., PHT 202, CTB 203, and Perceptron 204) that helps determine the characteristics of the branch (most notably direction and target address), prediction logic 210, completion logic 211, WeakPUQ 220, and BrWrgPUQ 230 collaboratively determine whether the branch is a candidate for update upon branch completion. Specifically, WeakPUQ 220 and BrWrgPUQ 230 determine whether the branch needs to be sent for update, and when it is determined that the branch needs to be sent for update, the data representing the branch is written to completion write queue 214.

[0032] Unexpected branches and dynamic branches that arrive at the wrong target or direction will always need to be sent via pipeline updates. Unexpected branches are those that were not predicted and learned based on instruction decoding. These types of branches can be identified at completion time by storing a very small amount of data (such as the predicted direction and target). Additionally, there are other types of dynamic branches that can also be identified at completion time and do not require additional information for necessary updates. The WeakPUQ220 tracks this information and determines at completion time that updates are necessary.

[0033] refer to Figure 3 This demonstrates an exemplary scenario of WeakPUQ 220 operation. For example... Figure 3 As shown, branches A, B, and C are provided. Branch A is predicted to be in a weak take state and is placed in WeakPUQ 220 (point 1). Branch A resolves to take (point 4) and matches in WeakPUQ 220, which means we need to update and therefore branch A is updated from weak take to strong take (point 7). At point 4, the matching entry for branch A is invalid in WeakPUQ 200. For branches B and C, prediction, resolution, and update are all performed on separate instances of the same branch, and since there is no matching entry in WeakPUQ 220, and since the entry is invalid at point 4 when branch A matches it, these branches are not sent through the update pipeline when they are completed (points 5 and 6, respectively). (Points 8 and 9 are redundant and do not occur in the implementation using WeakPUQ 200). Therefore, only the entry for branch A enters the update pipeline.

[0034] BrWrgPUQ 230 operates differently from WeakPUQ 220 because BrWrgPUQ 230 is designed to chase branches from different groups. BrWrgPUQ 230 is designed to chase future instances of branches predicted to be in a strong state (SNT (Strong Non-Take) or ST (Strong Take)). At completion time, this future instance resolves in the wrong direction before the update for that branch in the strong state has been processed by the re-prediction pipeline 240. Because the branch resolves in the wrong direction, it will be passed along the update pipeline, and simultaneously, it will be installed into BrWrgPUQ 230. BrWrgPUQ 230 is chasing branches with the same IA that were predicted after the initial branch, but before they are resolved after their update is complete and the prediction is in the correct direction. For example, a future instance of the same branch installed in BrWrgPUQ 230 might be sent via the re-prediction pipeline 240. This future instance completes without branch errors and is predicted to be in a strong state, but it doesn't match in BrWrgPUQ 230. In this case, those branches will see an incorrect state at prediction time because the update to that state hasn't occurred from the completion of the first instance, and because they resolve to miss the update if the predicted weak state will cause it. However, BrWrgPUQ 230 is there to catch this situation, so the branches know to go through the update pipeline. This means that this PUQ has entries created and invalidated at completion time, while WeakPUQ 220 has entries created at prediction time and invalidated at completion time.

[0035] See Figure 4 This demonstrates an exemplary scenario of BrWrgPUQ 230 operation. For example... Figure 4 As shown, branch A is predicted to be in a strong take (ST) state. Because it is in a strong take state, it is not placed into WeakPUQ 220 (point 1). Branch A resolves to not take, which is the wrong direction (point 2), and branch A enters the update pipeline to update the branch state for that branch. Branch A also creates an entry in BrWrgPUQ 230. After a restart following the branch error direction, before the update for branch A is complete (point 3), branch A... prime It is predicted to be in a strong state. Branch A prime Having the same instruction address as branch A, such as if a loop exists and we see the same branch predicted multiple times. Branch A completes its update process (point 4). When branch A... prime When the resolution result is correctly achieved, it typically does not automatically know that an update is necessary because it is predicted to be in a strong state and is correctly resolved (point 5). Branch A primeCheck and find a match in BrWrgPUQ 230. This tells branch A... prime It needs to go through an update pipeline because it has additional information from the parsing of branch A. Branch A prime Then it goes through the update pipeline and updates from the WT state back to the ST state (point 6).

[0036] refer to Figure 5 The operation of WeakPUQ 220 and BrWrgPUQ 230 will now be described.

[0037] In the initial instance, branch X completes at 501, and it is determined whether branch X resolved in the wrong direction or with the wrong target at 502. If branch X resolved in the wrong direction or with the wrong target, at 503, the entry for branch X is written to BrWrgPUQ 230, and an attempt is made to write the entry for branch X to the completion write queue at 504. If the completion write queue 504 is full and cannot accept writes to branch X, the data is not installed into the completion write queue. This is followed by waiting for completion events 505 and 501 for the completion of branch X. If branch X did not resolve in the wrong direction or with the wrong target, at 506, the entry for branch X is searched in WeakPUQ 220, and at 507 it is determined whether a hit exists in WeakPUQ 220. If a hit exists, at 508, the entry for branch X is invalidated from WeakPUQ 220, and control proceeds to 504. Conversely, if there is no hit, then at 509, the entry for branch X is searched in BrWrgPUQ230, and at 510, it is determined whether a hit exists. If a hit exists, then at 511, the entry for branch X is invalidated from BrWrgPUQ 230, and control proceeds to 504. Conversely, if there is no hit, then at 512 it is found that branch X does not need to be updated, and control proceeds to 505.

[0038] Return to reference Figure 2 Once a branch enters the update pipeline, the re-prediction pipeline 240 is used to perform the re-prediction of the branch. That is, once it is determined that a branch should go through the update pipeline, the final step before the process completes is to update the branch state. Since most of the data tracking has been removed from the process, the re-prediction of the branch is performed at completion time. The logic of the reproduction pipeline 240 reads data from the array, and it is where the re-prediction pipeline 240 picks up branch data rather than from information traced through the pipeline. Using the most current data, it becomes possible to determine the necessary updates for the branch, and once the update is determined, the logic of the reproduction pipeline 240 writes the data back to update the array.

[0039] refer to Figure 6 The operation of the re-predictive pipeline will now be described.

[0040] Initially, at 601, the entry for the next branch is searched in the write completion queue 214, and at 602, it is determined whether the entry for the next branch is valid. If the entry is invalid, control returns to 601. If the entry is valid, at 603, the metadata tables of one or more of BTB201, PHT202, CTB203, and perceptron 204 are indexed, a hit detection is performed at 604, and a hit is determined at 605. If no hit is detected, at 606, the branch is found to be unexpected, and at 607, it is determined whether the metadata state needs to be updated. If the metadata state needs to be updated, at 608, the updated state is written to the metadata table, and control proceeds to 601. If a hit is detected, at 609, it is determined whether a duplicate is found, and if a duplicate is found, at 610, all but one duplicate entry is invalidated, at 611, a re-predicted value is determined, at 612 the re-predicted value is compared with the existing result, and control proceeds to 607. If no duplicate is found, control immediately proceeds to 611.

[0041] refer to Figure 7A A computer-implemented method for updating a metadata prediction table as generally described above is provided. The computer-implemented method includes establishing a prediction (701) in the metadata prediction table of how an instruction set will be resolved, and identifying that the instruction set has been completed (702). The computer-implemented method further includes: upon completion of the instruction set, determining whether a prediction update queue (PUQ) associated with the instruction set indicates that the instruction set is resolved relative to the prediction in one of a number of prohibited methods (703); and, based on the PUQ indicating that the instruction set is resolved in one of the number of prohibited methods, determining that the metadata prediction table is a candidate for update (704). Additionally, the method may include updating the characteristics of the metadata prediction table as a candidate for update (705).

[0042] According to one or more embodiments of the present invention, the determination of the characteristics of the metadata prediction table to be updated in operation 704 may include: identifying an instruction set that is parsed with an incorrect target, in the wrong direction, or as an unexpected resolution; determining that the characteristics of the metadata prediction table need to be strengthened or weakened; or determining that the instruction set is parsed as an incorrect branch. However, it should be understood that other embodiments exist, and the determination of the characteristics of the metadata prediction table to be updated in operation 704 may involve other determinations, conclusions, etc.

[0043] In any case, the ability of WeakPUQ 220 to track the correctness of the prediction based on the assumptions will require updating the instruction set at completion time, and the ability of BrWrgPUQ 230 to track the instruction set that will require updating based on how multiple instances of each instruction set in the instruction set are completed, enable operation 704 to determine that the characteristic of the metadata prediction table is a candidate for update. Thus, operation 704's determination that the characteristic of the metadata prediction table is a candidate for update may also include observing that the characteristic of the metadata prediction table is a candidate for update (7041) and confirming that the characteristic of the metadata prediction table is a candidate for update is correct (7042).

[0044] As an example, for a metadata prediction table whose characteristics (including strengthening / weakening updates) are in a predefined state (i.e., unsaturated state), the observation of operation 7041 and the confirmation of operation 7042 as an update will be described below. The observation of operation 7041 occurs when a prediction is established in the metadata prediction table, and this observation includes assuming that an update will be needed if the instruction set resolves as expected, and writing the data representing the instruction set and the prediction as entries to the PUQ (such as WeakPUQ 220). The confirmation of operation 7042 occurs when the instruction set completes, and this confirmation includes comparing the data of the completed instruction with the data representing the previous instruction set written to the PUQ as a previous entry. The confirmation of operation 7042 also includes determining whether there is a match between the data representing the instruction set and the data representing the previous instruction set in the PUQ, invalidating the entry if a match is found, and confirming that the characteristics of the metadata prediction table should be updated.

[0045] As another example, for a situation where the characteristics of the metadata prediction table should be changed to account for branch error instances, the observation of operation 7041 and the confirmation of operation 7042 are described below as an update. The observation of operation 7041 occurs when the first and second instances of the instruction set are completed, and this observation includes writing data and predictions representing the first instance of the instruction set into a PUQ (such as BrWrgPUQ 230), respectively. The confirmation of operation 7042 occurs when the second instance of the instruction set is completed, and includes comparing the second data with data representing the previous instruction set written to the PUQ as a previous entry, determining whether there is a match between the second data representing the second instruction set and the data representing the previous instruction set in the PUQ, invalidating the entry if a match is found, and confirming that the characteristics of the metadata prediction table should be changed to account for branch error instances.

[0046] As used herein, the metadata prediction table may include one or more selected from the group consisting of BTB201, PHT202, CTB203 and perceptron 204.

[0047] See Figure 7BThis provides a computer-implemented method for performing operation 705 as an update of the characteristics of the metadata prediction table of candidates to be updated, as... Figure 7A The additional set of operations for the method. For example... Figure 7B As shown, the execution of operation 705 is a computer-implemented method for updating the characteristics of the metadata prediction table of the candidate to be updated, comprising: reading characteristic data from the metadata prediction table when the instruction set is completed (704), comparing the characteristic data with knowledge of how the instruction set is parsed (705), and determining whether to update the characteristics of the metadata prediction table based on the result of the comparison (706).

[0048] Turn now Figure 8 A computer system 800 is generally illustrated according to embodiments. The computer system 800 may be an electronic computer framework that includes and / or employs any number and combination of computing devices and networks utilizing different communication technologies, as described herein. The computer system 800 can be easily extended, scalable, and modularized, with the ability to be changed to different services or to reconfigure certain features independently of other features. The computer system 800 may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, the computer system 800 may be a cloud computing node. The computer system 800 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. The computer system 800 can be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules may reside in local and remote computer system storage media, including memory storage devices.

[0049] like Figure 8As shown, the computer system 800 has one or more central processing units (CPUs) 801a, 801b, 801c, etc. (collectively or commonly referred to as processor 801). Processor 801 can be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 801 (also referred to as processing circuitry) is coupled to system memory 803 and various other components via system bus 802. System memory 803 may include read-only memory (ROM) 804 and random access memory (RAM) 805. ROM 804 is coupled to system bus 802 and may include a basic input / output system (BIOS) that controls certain basic functions of computer system 800. RAM is a read-write memory coupled to system bus 802 for use by processor 801. System memory 803 provides temporary memory space for the operation of instructions during operation. System memory 803 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0050] Computer system 800 includes an input / output (I / O) adapter 806 and a communication adapter 807 coupled to a system bus 802. I / O adapter 806 may be a Small Computer System Interface (SCSI) adapter that communicates with a hard disk 808 and / or any other similar component. I / O adapter 806 and hard disk 808 are collectively referred to herein as mass storage 810.

[0051] Software 811 executing on computer system 800 may be stored in mass storage device 810. Mass storage device 810 is an example of a tangible storage medium readable by processor 801, wherein software 811 is stored as instructions for execution by processor 801 to operate computer system 800, such as those described below with respect to the various figures. Examples of computer program products and the execution of these instructions are discussed in more detail herein. Communication adapter 807 interconnects system bus 802 with network 812, which may be an external network enabling computer system 800 to communicate with other such systems. In one embodiment, a portion of system memory 803 and mass storage device 810 jointly store an operating system, which may be any suitable operating system, such as z / OS or AIX from IBM, for coordination. Figure 8 The functions of the different components shown.

[0052] Additional input / output devices are shown connected to system bus 802 via display adapter 815 and interface adapter 816. In one embodiment, adapters 806, 807, 815, and 816 may be connected to one or more I / O buses connected to system bus 802 via an intermediate bus bridge (not shown). Display 819 (e.g., screen or display monitor) is connected to system bus 802 via display adapter 815, which may include a graphics controller and a video controller to improve performance for graphics-intensive applications. Keyboard 821, mouse 822, speaker 823, etc., may be interconnected to system bus 802 via interface adapter 816, which may include, for example, a super I / O chip integrating multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Therefore, as Figure 8 The computer system 800 configured therein includes processing capabilities in the form of a processor 801, storage capabilities including system memory 803 and mass storage device 810, input devices such as a keyboard 821 and a mouse 822, and output capabilities including a speaker 823 and a display 819.

[0053] In some embodiments, the communication adapter 807 may use any suitable interface or protocol (such as an Internet Small Computer System Interface) to send data. The network 812 may be a cellular network, radio network, wide area network (WAN), local area network (LAN), or the Internet. External computing devices may connect to the computer system 800 via the network 812. In some examples, the external computing device may be an external web server or a cloud computing node.

[0054] It should be understood that Figure 8 The block diagram is not intended to indicate that the computer system 800 will include Figure 8 All components shown. Conversely, computer system 800 may include... Figure 8 Any suitable fewer or additional components not shown herein (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, the embodiments described herein with respect to computer system 800 can be implemented with any suitable logic, wherein the logic as mentioned herein may include any suitable hardware (e.g., processor, embedded controller, or application-specific integrated circuit, etc.), software (e.g., applications, etc.), firmware, or any suitable combination of hardware, software, and firmware.

[0055] Figure 9This is a process flow diagram of a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. Once physical design data is obtained, in part based on a computer-implemented method for updating branch prediction as described herein, the integrated circuit 120 can be manufactured according to general reference. Figure 9 The known processes described are used to fabricate the wafer. Typically, wafers with multiple copies of the final design are fabricated and diced (i.e., sliced) so that each die is a copy of the integrated circuit 120. At block 910, the process includes fabricating a mask for photolithography based on the finalized physical layout. At block 920, wafer fabrication includes performing photolithography and etching using the mask. Once the wafer has been sliced, at block 930, testing and sorting of each die is performed to filter out any defective dies.

[0056] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments of the invention may be devised without departing from the scope of the invention. Various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are illustrated in the following description and drawings. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the invention is limited in this respect by not illustrating the figures. Thus, the connection of entities may refer to direct or indirect connections, and the positional relationship between entities may be direct or indirect positional relationships. Furthermore, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein.

[0057] One or more of the methods described herein may be implemented by any one or a combination of the following techniques, each of which is well known in the art: discrete logic circuits having logic gates for performing logical functions on data signals, application-specific integrated circuits (ASICs) having appropriately combined logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0058] For the sake of brevity, conventional techniques relating to the manufacture and use of the present invention may or may not be described in detail herein. Specifically, various aspects of the computing systems and specific computer programs used to implement the different technical features described herein are well known. Consequently, for the sake of brevity, many conventional implementation details are only briefly mentioned or omitted entirely herein, without providing well-known system and / or process details.

[0059] In some embodiments, various functions or actions may occur at a given location and / or in conjunction with the operation of one or more devices or systems. In some embodiments, a portion of a given function or action may be performed at a first device or location, and the remainder of the function or action may be performed at one or more additional devices or locations.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should also be understood that when the terms “comprises” and / or “comprising” are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0061] All means or steps in the appended claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing the function in conjunction with other claimed elements as specifically claimed. This disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. These embodiments were chosen and described in order to best explain the principles and practical application of this disclosure, and to enable others skilled in the art to understand this disclosure with respect to different embodiments having different modifications suitable for the particular intended use.

[0062] The diagrams described herein are illustrative. Many variations may be made to the diagrams or steps (or operations) described herein without departing from the spirit of this disclosure. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term "coupling" describes a signal path between two elements and does not imply a direct connection between elements without intermediate elements / connections. All such variations are considered part of this disclosure.

[0063] The following definitions and abbreviations will be used to interpret the claims and description. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variations thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0064] Furthermore, the term "exemplary" is used herein to mean "used as an example, illustration, or illustration." Any implementation or design described herein as "exemplary" is not necessarily to be construed as superior to or better than other implementations or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0065] The terms “about,” “substantially,” “roughly,” and their variations are intended to include the degree of error associated with a measurement of a specific quantity based on the equipment available at the time of application submission. For example, “about” could include a range of ±8%, 5%, or 2% of a given value.

[0066] This invention can be a system, method, and / or computer program product with any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0067] Computer-readable storage media can be tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0068] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0069] Computer-readable program instructions for performing the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to perform aspects of the invention.

[0070] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0071] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more boxes of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0072] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0073] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a non-linear order. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0074] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A computer-implemented method of updating a metadata prediction table, the computer- implemented method comprising: establishing, in the metadata prediction table, a prediction of how an instruction set will resolve, the prediction of how the instruction set will resolve including a prediction of a direction and target of a branch instruction in the instruction set; identifying that the instruction set is complete; determining, at the time the instruction set is complete, whether a prediction update queue (PUQ) associated with the instruction set indicates that the instruction set resolved in one of a plurality of prescribed ways relative to the prediction; deciding, based on the PUQ indicating that the instruction set resolved in one of the plurality of prescribed ways, that the metadata prediction table is a candidate for updating; and updating the metadata prediction table in accordance with a result of the deciding.

2. The computer-implemented method of claim 1, wherein, Deciding that the metadata prediction table is a candidate for updating includes determining how the instruction set was resolved.

3. The computer-implemented method of claim 1, wherein, Deciding that the metadata prediction table is a candidate for updating includes: confirming that the metadata prediction table is a candidate for updating is correct.

4. The computer-implemented method of claim 3, wherein, For a case where the metadata prediction table is in a predefined state: the confirming occurs at the time the instruction set is complete, and the confirming includes comparing data representing the instruction set with data representing a previous instruction set written as a previous entry into one of the PUQs, and determining whether there is a match between the data representing the instruction set and the data representing the previous instruction set in one of the PUQs.

5. The computer-implemented method of claim 3, wherein, For a case where the metadata prediction table should be changed to resolve a branch misprediction instance: the confirming occurs at the time a second instance of the instruction set is complete, and the confirming includes comparing second data representing the second instance of the instruction set with data representing a previous instruction set written as a previous entry into one of the PUQs, and determining whether there is a match between the second data representing the second instance of the instruction set and the data representing the previous instruction set in one of the PUQs.

6. The computer-implemented method of claim 1, wherein, The deciding is accomplished by: a weak prediction update queue (Weak PUQ) to track a first instruction set that will require updating at completion time based on a correctness of a prediction of the first instruction set; and a branch misprediction PUQ (BrWrg PUQ) to track a second instruction set that will require updating based on how a plurality of instances of each of the first instruction set and the second instruction set completed.

7. The computer-implemented method of claim 1, wherein updating the metadata prediction table includes: reading, at the time the instruction set is complete, feature data from the metadata prediction table; comparing the feature data with knowledge of how the instruction set resolved; and determining, based on a result of the comparing, whether to update the metadata prediction table.

8. A computer program product for updating a metadata prediction table, the computer program product comprising a computer program which, when executed by a processor, carries out the operations of the method according to any one of claims 1 to 7.

9. A system for updating a metadata prediction table, the system comprising: a memory having computer readable instructions; and a processor to execute the computer readable instructions. one or more processors to execute the computer-readable instructions that control the one or more processors to perform operations of the method of any one of claims 1-7.

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