Hardware connection testing method, device, equipment and readable storage medium
Through simplified hardware connection testing methods and devices, it is directly connected to the physical layer chip, sending test instructions, and performing initial configuration and loopback testing, solving the problem of high learning costs for SI engineers in hardware connection testing and improving testing efficiency.
Patent Information
- Application Number
- CN202211362097.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-02
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2042-11-02
AI Technical Summary
In the prior art, SI engineers need to use additional testing tools or learn complex register instructions during hardware connection testing, resulting in high learning costs and long testing time, which reduces work efficiency.
It provides a hardware connection testing method and device, through the test terminal, connects to the physical layer chip, sends test instructions and obtains results, performs initial configuration and port loopback testing, simplifies operational processes, and reduces learning costs and error probability.
No need for support from other platforms, simplifies the testing process, reduces the learning cost and probability of errors for SI engineers, and improves the efficiency of hardware connection testing.
Smart Images
Figure CN115794530B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of hardware testing, and in particular to a hardware connection testing method, device, equipment and readable storage medium. Background Art
[0002] The physical layer of a switch is responsible for processing physical address data and is a critical component of the switch. With the continuous expansion of global networks, the number of switches in use has also increased, and the number of switches that switch operators need to manage, configure, and test has also increased significantly. Traditionally, hardware connection testing of switch physical layer chips requires SI (Signal Integrity) engineers to use test software that is compatible with the physical layer chips. The advantages of this hardware connection testing method are its powerful software features; however, the disadvantages are also significant: this type of software typically has a complex interface, a relatively fixed operating environment, and a high learning curve. Furthermore, the testing process requires repeated flashing of the physical layer chip firmware, which is time-consuming and may even require a demo board for testing.
[0003] To address the learning curve for specialized software, a method for directly reading and writing physical layer chip registers to test hardware connections has gradually emerged. This method offers the advantage of not requiring additional platform support. However, instructions for directly manipulating registers are difficult for SI engineers to understand, resulting in a high probability of error, and supporting limited testing methods. Therefore, there is an urgent need for a hardware connection testing method, apparatus, device, and readable storage medium that can provide SI engineers with a simple operating environment, allowing them to focus more on testing and debugging hardware connections, thereby improving their work efficiency. Summary of the Invention
[0004] In order to solve the problems of the prior art, the embodiments of the present invention provide a hardware connection testing method, device, equipment and readable storage medium to overcome the problem in the prior art that SI engineers need to use additional testing tools or need to additionally and systematically learn register instructions in the hardware connection testing process in order to perform hardware connection testing, which increases the time cost of hardware connection testing and reduces the work efficiency of SI engineers.
[0005] In order to solve one or more of the above technical problems, the present invention adopts the following technical solutions:
[0006] In a first aspect, a hardware connection testing method is provided, comprising:
[0007] Connecting the physical layer chip to the hardware under test and a test terminal, and initializing and configuring the physical layer chip; wherein the test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip, wherein the communication information at least includes the test instructions;
[0008] Using a test terminal to send a test instruction to the physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction;
[0009] Comparing the first result and the second result with a test parameter set to determine whether a parameter of the first result or a parameter of the second result is normal, wherein the test parameter set includes normal test parameters corresponding to the test instruction;
[0010] If the result of determining whether the parameters of the first result or the second result are normal is yes, performing a port loopback test and obtaining a result of the port loopback test;
[0011] Analyze the results of the port loopback test to obtain the results of the connection test.
[0012] Furthermore, the physical layer chip is initialized and configured, including:
[0013] Send initialization configuration file to the physical layer chip;
[0014] Verify the return value of the initialization configuration file;
[0015] If the return value check result of the initialization configuration file is correct, the initialization configuration file is used to initialize the physical layer chip.
[0016] Furthermore, the initialization configuration file is used to initialize the physical layer chip, including:
[0017] Configure the physical layer chip in retimer mode as a 4×10G QSFP port;
[0018] Configuring a socket port for transmitting communication information for the QSFP port; wherein the socket port is used to transmit communication information;
[0019] The physical layer chip is configured as a first side and a second side. The first side feeds back a corresponding first result after receiving a test instruction, and the second side feeds back a corresponding second result after receiving a test instruction.
[0020] Furthermore, if the return value check result of the initialization configuration file is an error, the physical layer chip is configured as a default configuration.
[0021] Furthermore, sending a test instruction to the physical layer chip and obtaining a first result and a second result of the hardware under test responding to the test instruction include:
[0022] Use the test terminal to send test instructions to the physical layer chip through the socket;
[0023] Parsing the test instruction and executing the parsed test instruction through the first side and the second side;
[0024] A first result corresponding to feedback from the first side executing the test instruction and a second result corresponding to feedback from the second side executing the test instruction are obtained.
[0025] Furthermore, a port loopback test is performed and the results of the port loopback test are obtained, including:
[0026] Set the traffic direction and use the first side of the physical side chip as the packet sending side to send data; the traffic direction includes at least: the packet sending side and the packet receiving side;
[0027] Receive data on the receiving side of the traffic direction;
[0028] Compare the sent data with the received data, obtain the comparison result, and use the comparison result as the result of the port loopback test.
[0029] Furthermore, before comparing the first result and the second result with the test parameter set, the method further includes:
[0030] Perform a hardware connection test on the correctly connected hardware to obtain the correct test parameter set.
[0031] In a second aspect, a hardware connection test device is provided, comprising: an initial configuration module, a test execution module, a parameter comparison module, a loopback test module, and a result analysis module;
[0032] An initial configuration module is used to connect the physical layer chip to the hardware under test and the test terminal, and to initialize the configuration of the physical layer chip; wherein the test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip, and the communication information includes at least the test instructions;
[0033] A test execution module, configured to use a test terminal to send a test instruction to the physical layer chip, and obtain a first result and a second result of the hardware under test responding to the test instruction;
[0034] a parameter comparison module, configured to compare the first result and the second result with a test parameter set to determine whether the parameters of the first result or the second result are normal, wherein the test parameter set includes normal test parameters corresponding to the test instruction;
[0035] a loopback test module, configured to perform a port loopback test and obtain a result of the port loopback test if the result of determining whether the parameters of the first result or the second result are normal is yes;
[0036] The result analysis module is used to analyze the results of the port loopback test and obtain the results of the connection test.
[0037] In a third aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of a hardware connection testing method described in the first aspect are implemented.
[0038] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of a hardware connection testing method described in the first aspect are implemented.
[0039] The technical solution provided by the embodiment of the present invention has the following beneficial effects:
[0040] 1. The hardware connection test method and device disclosed in the present invention can be directly used on hardware devices such as switches, without the need for other platform support or repeated programming, thus reducing the debugging cost of the chip under test;
[0041] 2. The test method is concise and intuitive, which reduces the learning cost and error probability of SI engineers and greatly enriches the means of hardware testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0043] Figure 1 1 is a schematic diagram of a hardware connection testing method provided by an embodiment of the present invention;
[0044] Figure 2 Schematic diagram of a hardware connection test device provided by an embodiment of the present invention;
[0045] Figure 3 This is a schematic diagram of a hardware connection test computer device provided by an embodiment of the present invention;
[0046] Figure 4 This is a physical layer chip Line side eye diagram provided by an embodiment of the present invention;
[0047] Figure 5 This is a schematic diagram of a test parameter set provided by an embodiment of the present invention;
[0048] Figure 6 This is a schematic diagram of the flow direction of a loopback test provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0049] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0050] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar expressions used in this disclosure do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a," "an," or "the" do not indicate a quantitative limitation, but rather indicate the presence of at least one. The numbers in the drawings in this specification merely distinguish between various functional components or modules and do not indicate a logical relationship between the components or modules. Terms such as "include" or "comprising" mean that the element or object preceding the term includes the elements or objects listed after the term, and their equivalents, without excluding other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0051] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that, in the accompanying drawings, the same reference numerals are given to components having substantially the same or similar structures and functions, and repeated descriptions thereof will be omitted.
[0052] In view of the existing technology, when SI engineers are testing hardware, specifically switch connections, they face the dilemma of a lack of debugging methods that can provide SI engineers with a simple operating environment, forcing SI engineers to spend time and money learning how to use dedicated software or learn additional knowledge such as instructions for directly operating registers before they can carry out their main job of signal integrity analysis, making it difficult to improve work efficiency. The embodiment of the present invention discloses a hardware connection test method, device, equipment and readable storage medium, which facilitates SI engineers to quickly get started with the test tools when conducting hardware device connection tests, avoid learning complex debugging environment operations, and thus improve the work efficiency of analyzing test objects and connection conditions. The specific technical solutions are as follows:
[0053] In one embodiment, Figure 1 As shown, a hardware connection testing method includes:
[0054] S100: Connect the physical layer chip to the hardware to be tested and the test terminal, and initialize and configure the physical layer chip.
[0055] S200: Using a test terminal to send a test instruction to a physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction.
[0056] S300: Compare the first result and the second result with the test parameter set to determine whether the parameters of the first result or the second result are normal.
[0057] If the result of determining whether the parameters of the first result or the second result are normal is yes, then S400: performing a port loopback test and obtaining a result of the port loopback test.
[0058] S500: Analyze the result of the port loopback test and obtain the result of the connection test.
[0059] In one embodiment, a hardware connection testing method is performed as follows:
[0060] S000: Perform a hardware connection test on the correctly connected hardware to be tested to obtain a correct test parameter set.
[0061] S100: Connecting a physical layer chip (PHY chip) to the hardware under test and a test terminal, and initializing and configuring the physical layer chip. The test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip. The communication information at least includes the test instructions.
[0062] Specifically include:
[0063] S110: Send an initialization configuration file to the physical layer chip. The initialization configuration file contains the specific environment and parameters for initializing the physical layer chip. In one embodiment, the PHY chip is configured as a 4x10G QSFP port (port 1, port 2, port 3, and port 4) via the CPU10GBASE-KR. These ports are interconnected with other 4x10G port devices. This is used to test port 1 traffic during a high-temperature reset stress test scenario.
[0064] S120: Check the return value of the initialization configuration file; the return value is used to verify the correctness of the initialization configuration file to avoid initialization configuration errors caused by bit errors.
[0065] If the return value check result of the initialization configuration file is correct, then S130: initialization configuration of the physical layer chip is performed using the initialization configuration file. Specifically including:
[0066] S131: Configure the physical layer chip in retimer mode as a 4x10G QSFP port.
[0067] S132: Configuring a socket port for transmitting communication information for the QSFP port; wherein the socket port is used to transmit communication information;
[0068] S133: The physical layer chip is configured into a first side and a second side. The first side feeds back a corresponding first result after receiving the test instruction. The second side feeds back a corresponding second result after receiving the test instruction.
[0069] In one embodiment, the first side of the physical layer chip is configured as the host side, and the second side is configured as the line side. Accordingly, during the test, the first result fed back by the first side is the first eye diagram, and the second result fed back by the second side is the second eye diagram.
[0070] If the return value check result of the initialization configuration file is an error, then S130′: the physical layer chip is configured as a default configuration.
[0071] S200: Using a test terminal to send a test instruction to a physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction.
[0072] Specifically include:
[0073] S210: Use the test terminal to send a test command to the physical layer chip through the socket. In one embodiment, the command is mcdtool -v eye 1 line, which is used to view the eye diagram on the port 1 line side.
[0074] S220: Parse the test command, and execute the parsed test command through the first side and the second side. In one embodiment, the command will be parsed and sent to the physical layer chip for execution.
[0075] S230: Obtain a first result corresponding to the feedback of the test instruction executed by the first side, and a second result corresponding to the feedback of the test instruction executed by the second side. Figure 4 As shown. The signal quality is good.
[0076] By executing S210 to S230 on the host side in the same manner, an eye diagram on the host side can be obtained.
[0077] S300: Compare the first result and the second result with the test parameter set to determine whether the parameters of the first result or the second result are normal.
[0078] The test parameter set is the serdes parameter. By executing the mcdtool -v tune_result 1 host command, you can view the CTLE and DFE training results of port 1 and draw the following Figure 5 Similarly, you can run the mcdtool-vtune_result 1 line command to view the Line side parameters.
[0079] If the result of determining whether the parameters of the first result or the second result are normal is yes, then S400: performing a port loopback test and obtaining a result of the port loopback test.
[0080] Specifically include:
[0081] S410: Set the traffic direction and use the first side of the physical side chip as the packet sending side to send data; the traffic direction includes at least: a packet sending side and a packet receiving side.
[0082] S420: Receive data on the packet receiving side in the traffic direction;
[0083] S430: Compare the sent data with the received data, obtain a comparison result, and use the comparison result as a result of the port loopback test.
[0084] In one embodiment, execute mcdtool -s traffic 1 start to send packets from the host side of the PHY chip corresponding to port 1, such as Figure 6 In the traffic direction ①, the peer device can receive packets normally, so it can be judged that there is no abnormality in the entire link from the host side rx to the line side tx. Figure 6 In traffic direction ②, port 1 cannot receive packets normally and contains a large number of CRC errors. This indicates that an abnormality exists in the direction from the line side (rx) to the host side (tx).
[0085] Run mcdtool-s loopback 1 host pcs to configure pcs loopback on the host side of the PHY chip and send packets from the peer device. Figure 6 As shown in the traffic direction ③, the traffic is looped back to the peer device and can receive packets normally. Therefore, the exception occurs from the host side PCS to the host side TX PMA. Further configure the host side to configure internal loopback, execute mcdtool-sloopback 1 host internal, and send packets from the peer device, such as Figure 6 In the traffic direction ④, the traffic is looped back to the peer device. If an abnormality occurs in packet reception, the abnormality can be accurately located at the host-side TX PMA.
[0086] If the result of determining whether the parameters of the first result or the second result are normal is no, then S400' is executed: an error result is returned and the error result is used as the result of the connection test, and then the connection test method ends.
[0087] S500: Analyze the result of the port loopback test and obtain the result of the connection test.
[0088] In another embodiment, Figure 2 As shown, a hardware connection test device includes: an initial configuration module, a test execution module, a parameter comparison module, a loopback test module, and a result analysis module.
[0089] An initial configuration module is used to connect the physical layer chip to the hardware under test and the test terminal, and to initialize the configuration of the physical layer chip; wherein the test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip, and the communication information includes at least the test instructions;
[0090] A test execution module, configured to use a test terminal to send a test instruction to the physical layer chip, and obtain a first result and a second result of the hardware under test responding to the test instruction;
[0091] a parameter comparison module, configured to compare the first result and the second result with a test parameter set to determine whether the parameters of the first result or the second result are normal, wherein the test parameter set includes normal test parameters corresponding to the test instruction;
[0092] a loopback test module, configured to perform a port loopback test and obtain a result of the port loopback test if the result of determining whether the parameters of the first result or the second result are normal is yes;
[0093] The result analysis module is used to analyze the results of the port loopback test and obtain the results of the connection test.
[0094] In another embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 3As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a hardware connection method described in the first aspect above is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad provided on the computer device housing, or an external keyboard, touchpad or mouse.
[0095] In another embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the hardware connection testing method described in the first aspect are implemented.
[0096] By implementing the embodiments described in this application, it can be directly used to perform connection tests on hardware such as switches, without the need for other platform support or repeated burning, thereby reducing the debugging cost of the chip under test; at the same time, the testing method is simple and intuitive, reducing the learning cost and error probability of SI engineers, and greatly enriching the means of hardware testing.
[0097] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present invention, and will not be described in detail here.
[0098] Example 1
[0099] The following combination Figure 1 , describes a hardware connection testing method.
[0100] S100: Connect the physical layer chip to the hardware to be tested and the test terminal, and initialize and configure the physical layer chip.
[0101] S200: Using a test terminal to send a test instruction to a physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction.
[0102] S300: Compare the first result and the second result with the test parameter set to determine whether the parameters of the first result or the second result are normal.
[0103] If the result of determining whether the parameters of the first result or the second result are normal is yes, then S400: performing a port loopback test and obtaining a result of the port loopback test.
[0104] S500: Analyze the result of the port loopback test and obtain the result of the connection test.
[0105] Example 2
[0106] A hardware connection testing method specifically includes:
[0107] S000: Perform a hardware connection test on the correctly connected hardware to be tested to obtain a correct test parameter set.
[0108] S100: Connecting the physical layer chip to the hardware under test and the test terminal, and initializing the configuration of the physical layer chip. The test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip. The communication information at least includes the test instructions.
[0109] Specifically include:
[0110] S110: Sending an initialization configuration file to the physical layer chip;
[0111] S120: Verify the return value of the initialization configuration file;
[0112] If the return value check result of the initialization configuration file is correct, then S130: initialization configuration of the physical layer chip is performed using the initialization configuration file. Specifically including:
[0113] S131: Configure the physical layer chip in retimer mode as a 4×10G QSFP port;
[0114] S132: Configuring a socket port for transmitting communication information for the QSFP port; wherein the socket port is used to transmit communication information;
[0115] S133: The physical layer chip is configured into a first side and a second side. The first side feeds back a corresponding first result after receiving the test instruction. The second side feeds back a corresponding second result after receiving the test instruction.
[0116] If the return value check result of the initialization configuration file is an error, then S130′: the physical layer chip is configured as a default configuration.
[0117] S200: Using a test terminal to send a test instruction to a physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction.
[0118] Specifically include:
[0119] S210: Use the test terminal to send a test instruction to the physical layer chip through the socket.
[0120] S220: Parse the test instruction, and execute the parsed test instruction through the first side and the second side.
[0121] S230: Acquire a first result corresponding to feedback from the first side executing the test instruction, and a second result corresponding to feedback from the second side executing the test instruction.
[0122] S300: Compare the first result and the second result with the test parameter set to determine whether the parameters of the first result or the second result are normal.
[0123] If the result of determining whether the parameters of the first result or the second result are normal is yes, then S400: performing a port loopback test and obtaining a result of the port loopback test.
[0124] Specifically include:
[0125] S410: Set the traffic direction and use the first side of the physical side chip as the packet sending side to send data; the traffic direction includes at least: a packet sending side and a packet receiving side.
[0126] S420: Receive data on the packet receiving side in the traffic direction;
[0127] S430: Compare the sent data with the received data, obtain a comparison result, and use the comparison result as a result of the port loopback test.
[0128] If the result of determining whether the parameters of the first result or the second result are normal is no, S400 ′ is executed: an error result is returned, and the error result is used as the result of the connection test.
[0129] S500: Analyze the result of the port loopback test and obtain the result of the connection test.
[0130] Example 3
[0131] The following combination Figure 2 , describing a hardware connection testing device.
[0132] A hardware connection test device specifically comprises: an initial configuration module, a test execution module, a parameter comparison module, a loopback test module, and a result analysis module.
[0133] An initial configuration module is used to connect the physical layer chip to the hardware under test and the test terminal, and to initialize the configuration of the physical layer chip; wherein the test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip, and the communication information includes at least the test instructions;
[0134] A test execution module, configured to use a test terminal to send a test instruction to the physical layer chip, and obtain a first result and a second result of the hardware under test responding to the test instruction;
[0135] a parameter comparison module, configured to compare the first result and the second result with a test parameter set to determine whether the parameters of the first result or the second result are normal, wherein the test parameter set includes normal test parameters corresponding to the test instruction;
[0136] a loopback test module, configured to perform a port loopback test and obtain a result of the port loopback test if the result of determining whether the parameters of the first result or the second result are normal is yes;
[0137] The result analysis module is used to analyze the results of the port loopback test and obtain the results of the connection test.
[0138] Example 4
[0139] A computer device, which may be a terminal, may have an internal structure as shown in FIG. Figure 3 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a hardware connection method described in the first aspect above is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad provided on the computer device housing, or an external keyboard, touchpad or mouse.
[0140] A hardware connection method specifically includes:
[0141] S000: Perform a hardware connection test on the correctly connected hardware to be tested to obtain a correct test parameter set.
[0142] S100: Connecting the physical layer chip to the hardware under test and the test terminal, and initializing the configuration of the physical layer chip. The test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip. The communication information at least includes the test instructions.
[0143] Specifically include:
[0144] S110: Sending an initialization configuration file to the physical layer chip;
[0145] S120: Verify the return value of the initialization configuration file;
[0146] If the return value check result of the initialization configuration file is correct, then S130: initialization configuration of the physical layer chip is performed using the initialization configuration file. Specifically including:
[0147] S131: Configure the physical layer chip in retimer mode as a 4×10G QSFP port;
[0148] S132: Configuring a socket port for transmitting communication information for the QSFP port; wherein the socket port is used to transmit communication information;
[0149] S133: The physical layer chip is configured into a first side and a second side. The first side feeds back a corresponding first result after receiving the test instruction. The second side feeds back a corresponding second result after receiving the test instruction.
[0150] If the return value check result of the initialization configuration file is an error, then S130′: the physical layer chip is configured as a default configuration.
[0151] S200: Using a test terminal to send a test instruction to a physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction.
[0152] Specifically include:
[0153] S210: Use the test terminal to send a test instruction to the physical layer chip through the socket.
[0154] S220: Parse the test instruction, and execute the parsed test instruction through the first side and the second side.
[0155] S230: Acquire a first result corresponding to feedback from the first side executing the test instruction, and a second result corresponding to feedback from the second side executing the test instruction.
[0156] S300: Compare the first result and the second result with the test parameter set to determine whether the parameters of the first result or the second result are normal.
[0157] If the result of determining whether the parameters of the first result or the second result are normal is yes, then S400: performing a port loopback test and obtaining a result of the port loopback test.
[0158] Specifically include:
[0159] S410: Set the traffic direction and use the first side of the physical side chip as the packet sending side to send data; the traffic direction includes at least: a packet sending side and a packet receiving side.
[0160] S420: Receive data on the packet receiving side in the traffic direction;
[0161] S430: Compare the sent data with the received data, obtain a comparison result, and use the comparison result as a result of the port loopback test.
[0162] If the result of determining whether the parameters of the first result or the second result are normal is no, S400 ′ is executed: an error result is returned, and the error result is used as the result of the connection test.
[0163] S500: Analyze the result of the port loopback test and obtain the result of the connection test.
[0164] Example 5
[0165] A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the hardware connection testing method described in the first aspect above are implemented, specifically including:
[0166] S000: Perform a hardware connection test on the correctly connected hardware to be tested to obtain a correct test parameter set.
[0167] S100: Connecting the physical layer chip to the hardware under test and the test terminal, and initializing the configuration of the physical layer chip. The test terminal is used to send communication information test instructions to the hardware under test through the physical layer chip. The communication information at least includes the test instructions.
[0168] Specifically include:
[0169] S110: Sending an initialization configuration file to the physical layer chip;
[0170] S120: Verify the return value of the initialization configuration file;
[0171] If the return value check result of the initialization configuration file is correct, then S130: initialization configuration of the physical layer chip is performed using the initialization configuration file. Specifically including:
[0172] S131: Configure the physical layer chip in retimer mode as a 4×10G QSFP port;
[0173] S132: Configuring a socket port for transmitting communication information for the QSFP port; wherein the socket port is used to transmit communication information;
[0174] S133: The physical layer chip is configured into a first side and a second side. The first side feeds back a corresponding first result after receiving the test instruction. The second side feeds back a corresponding second result after receiving the test instruction.
[0175] If the return value check result of the initialization configuration file is an error, then S130′: the physical layer chip is configured as a default configuration.
[0176] S200: Using a test terminal to send a test instruction to a physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction.
[0177] Specifically include:
[0178] S210: Use the test terminal to send a test instruction to the physical layer chip through the socket.
[0179] S220: Parse the test instruction, and execute the parsed test instruction through the first side and the second side.
[0180] S230: Acquire a first result corresponding to feedback from the first side executing the test instruction, and a second result corresponding to feedback from the second side executing the test instruction.
[0181] S300: Compare the first result and the second result with the test parameter set to determine whether the parameters of the first result or the second result are normal.
[0182] If the result of determining whether the parameters of the first result or the second result are normal is yes, then S400: performing a port loopback test and obtaining a result of the port loopback test.
[0183] Specifically include:
[0184] S410: Set the traffic direction and use the first side of the physical side chip as the packet sending side to send data; the traffic direction includes at least: a packet sending side and a packet receiving side.
[0185] S420: Receive data on the packet receiving side in the traffic direction;
[0186] S430: Compare the sent data with the received data, obtain a comparison result, and use the comparison result as a result of the port loopback test.
[0187] If the result of determining whether the parameters of the first result or the second result are normal is no, S400 ′ is executed: an error result is returned, and the error result is used as the result of the connection test.
[0188] S500: Analyze the result of the port loopback test and obtain the result of the connection test.
[0189] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program loaded on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a memory, or installed from a ROM. When the computer program is executed by an external processor, the above-mentioned functions defined in the method of the embodiment of the present application are executed.
[0190] It should be noted that the computer-readable medium of the embodiments of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the embodiments of the present application, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device. In the embodiments of the present application, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or convey a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.
[0191] The computer-readable medium may be included in the server or may exist independently and not incorporated into the server. The computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the terminal's peripheral mode is inactive, obtain the frame rate of applications on the terminal; when the frame rate meets a screen-off condition, determine whether the user is currently accessing the terminal's screen information; and, in response to determining that the user is not accessing the terminal's screen information, control the screen to enter an immediate dimming mode.
[0192] Computer program code for performing the operations of embodiments of the present application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0193] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without expending creative work.
[0194] The above is a detailed introduction to the technical solutions provided by this application. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand the method and core concept of this application. At the same time, for those skilled in the art, based on the concept of this application, there may be changes in the specific implementation methods and application scope. In summary, the contents of this specification should not be understood as limiting this application.
[0195] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A hardware connection testing method, characterized in that: The method comprises: Connecting the physical layer chip to the hardware under test and a test terminal, and initializing and configuring the physical layer chip; wherein the test terminal is used to send communication information to the hardware under test through the physical layer chip, the communication information including at least a test instruction; Using the test terminal to send a test instruction to the physical layer chip, and obtaining a first result and a second result of the hardware under test responding to the test instruction; comparing the first result and the second result with a test parameter set to determine whether a parameter of the first result or a parameter of the second result is normal, wherein the test parameter set includes normal test parameters corresponding to the test instruction; If the result of determining whether the parameters of the first result or the second result are normal is yes, performing a port loopback test and obtaining a result of the port loopback test; Analyze the result of the port loopback test to obtain the result of the connection test; The sending of a test instruction to the physical layer chip and obtaining a first result and a second result of the hardware under test in response to the test instruction includes: Using the test terminal, sending a test instruction to the physical layer chip through a socket; Parsing the test instruction, and executing the parsed test instruction through the first side and the second side; A first result corresponding to feedback from the first side executing the test instruction and a second result corresponding to feedback from the second side executing the test instruction are obtained.
2. A hardware connection testing method according to claim 1, characterized in that: The initializing configuration of the physical layer chip includes: Sending an initialization configuration file to the physical layer chip; Verify the return value of the initialization configuration file; If the return value check result of the initialization configuration file is correct, the initialization configuration file is used to initialize the physical layer chip.
3. A hardware connection testing method according to claim 2, characterized in that: The initializing configuration of the physical layer chip using the initialization configuration file includes: The physical layer chip is configured as a 4×10G QSFP port in a retimer mode; Configuring a socket port for transmitting communication information for the QSFP port; wherein the socket port is used to transmit communication information; The physical layer chip is configured as a first side and a second side. The first side feeds back a corresponding first result after receiving the test instruction, and the second side feeds back a corresponding second result after receiving the test instruction.
4. A hardware connection testing method according to claim 2, characterized in that: If the return value check result of the initialization configuration file is an error, the physical layer chip is configured as a default configuration.
5. A hardware connection testing method according to claim 1, characterized in that: The performing of the port loopback test and obtaining the result of the port loopback test includes: Setting a traffic direction and using the first side of the physical layer chip as a packet sending side to send data; the traffic direction includes at least: a packet sending side and a packet receiving side; receiving data on a packet receiving side in the traffic direction; The sent data is compared with the received data to obtain a comparison result, and the comparison result is used as a result of the port loopback test.
6. A hardware connection testing method according to claim 1, characterized in that: Before comparing the first result and the second result with the test parameter set, the method further includes: Perform a hardware connection test on the correctly connected hardware to obtain the correct test parameter set.
7. A hardware connection testing device for implementing the hardware connection testing method according to any one of claims 1 to 6, characterized in that: The device includes: an initial configuration module, a test execution module, a parameter comparison module, a loopback test module, and a result analysis module; The initial configuration module is configured to connect the physical layer chip to the hardware under test and the test terminal, and to initialize the configuration of the physical layer chip; wherein the test terminal is configured to send communication information to the hardware under test via the physical layer chip, wherein the communication information includes at least a test instruction; The test execution module is configured to use the test terminal to send a test instruction to the physical layer chip, and obtain a first result and a second result of the hardware under test responding to the test instruction; The parameter comparison module is configured to compare the first result and the second result with a test parameter set to determine whether the parameters of the first result or the second result are normal, wherein the test parameter set includes normal test parameters corresponding to the test instruction; The loopback test module is configured to perform a port loopback test and obtain a result of the port loopback test if the result of determining whether the parameters of the first result or the second result are normal is yes; The result analysis module is used to analyze the result of the port loopback test and obtain the result of the connection test.
8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.
Citation Information
Patent Citations
Switch based process level network message analysis method
CN104038383A
Link fault diagnosis method and device, electronic equipment and readable storage medium
CN114448915A