Programmable fourier transform memory-in-circuit

Abstract

The application will break through the traditional Fourier transform implementation, explore a new method for realizing Fourier transform based on storage and computing integration technology, and innovatively propose a high-energy efficient Fourier transform calculation circuit from the perspective of analog circuit, belonging to the field of signal analysis and signal processing. First, research how to use the memristor array to design a complex matrix multiplication operation circuit; secondly, on this basis, research on programmable in-memory computing circuit of one-dimensional Fourier transform and its inverse transform is carried out. Considering that a large amount of two-dimensional signals need to be processed in practical applications, therefore, on the basis of the research on one-dimensional Fourier transform calculation circuit, the research on programmable in-memory computing circuit of two-dimensional Fourier transform is carried out. The application has very important scientific significance and potential economic benefits for the realization of real-time Fourier transform; the research results can be widely applied to signal processing in the field of Internet of Things, and help to form core intellectual property rights in this field.

Description

Technical Field

[0001] This invention relates to a programmable Fourier transform in-memory computing circuit, belonging to the field of signal analysis and signal processing. Background Technology

[0002] In recent years, the implementation of Fourier transform has become a research hotspot both domestically and internationally. However, software-based implementations, relying on computer-based software programming, are difficult to deploy in practical applications. Existing hardware implementations have improved the computational performance of Fourier transform to some extent, but still suffer from problems such as memory constraints, low real-time performance, and high hardware power consumption when calculating large-point Fourier transforms.

[0003] (1) Software Algorithm-Based Implementation: In 1968, engineers proposed a DFT (Fast Fourier Transform) algorithm called "split basis," which improved the computation speed by 20% compared to the previously proposed classic "radix-2" algorithm. Subsequently, a series of algorithms related to "split basis" were proposed, including a divide-and-conquer DFT algorithm that improved computation speed by reducing the number of additions. A recursive cyclic group decomposition algorithm (RCFA) was also proposed, which could be implemented using a finite number of different computational units. A variant called "conjugate pair DFT" could reduce the number of operations, but later literature confirmed that the number of operations in this method was the same as the normal "split basis." American engineers recursively modified the "split basis," reducing the number of operations by 6%. Similar to the one-dimensional DFT algorithm, the 2D-DFT has also been continuously improved at the algorithm level. In traditional methods, the 2D-DFT is calculated by reusing the one-dimensional DFT; this method is called the "row-column" method. The rapid development of one-dimensional DFT technology has also provided more possibilities for the implementation of 2D-DFT, one of which is the "vector basis" DFT. Furthermore, American researchers have used a "multi-vector" DFT algorithm to simultaneously compute all column transformations in the array, while also avoiding some unnecessary multiplication operations, thus improving computational speed. In addition, there is a simulation of the Cooley-Tukey algorithm, which has fewer addition and multiplication operations than the standard algorithm. A new method for implementing 2D-DFT on a shrinking array structure has been proposed, which significantly reduces the multiplication required for computation. Many domestic researchers have also optimized the Fourier transform at the algorithm level. Researchers have improved the accuracy of function interpolation 2D-DFT by eliminating the requirement for function interpolation. In 2020, researchers proposed an optimization strategy and method for Cooley-Tukey DFT for even-basis systems, and also proposed an implementation method for ultra-large point-value DFT; this method avoids three explicit transposes by optimizing hinge factor storage and accessing the 2D matrix by row and column indices, thus saving memory resources. Subsequently, in 2021, researchers proposed a hybrid basis DFT algorithm adaptable to DFT computations with different point counts, utilizing a hybrid factorization model combining prime factorization and Cooley-Tukey factorization, and employing a general butterfly unit module design. In the same year, researchers combined the computational characteristics of DFT with distributed stream processing, proposing a Flink-based parallel DFT workflow method. They also designed a cache window suitable for DFT in Flink, allowing for partial overlap between communication and computation time, thus accelerating DFT processing. Based on the analysis of the above literature, it can be seen that at the algorithm improvement level, researchers have used various methods to reduce computational load and improve computational speed.However, current improvements to software algorithms mainly rely on software programming methods for general-purpose computers, which result in slow processing speeds, high performance overhead, and difficulty in deployment in practical applications.

[0004] (2) Hardware-based implementation methods: Hardware implementation mainly takes three forms: Application-Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), and Field-Programmable Gate Arrays (FPGAs). A traditional hardware-oriented design method, namely the Single-Path Delay (SDF) Fourier Transform, mainly focuses on the "radix-2" design. Subsequently, there have been many hardware designs for "radix-4", "radix-6", and "radix-8". Singaporean scholars PK et al. proposed a register-based storage design, which significantly reduces the storage area involved compared to RAM-based storage cells, but increases the delay cost. Indian researchers normalized the twiddle factor on the FPGA to reduce the multiplication count, which is more computationally efficient than the standard "radix-2" DFT and reduces multiplications without sacrificing any numerical accuracy. US researchers designed a low-error asynchronous adder, which reduces the hardware cost required by the proposed adder by 76% compared to the traditional adder, and realizes the Asynchronous Stochastic Fast Fourier Transform (ASC-DFT). Compared with the traditional DFT architecture, the delay time and area are significantly improved, while the computational accuracy of the DFT signal-to-noise ratio measurement is not reduced. Spanish researchers proposed a folding architecture where butterfly computations are multiplexed into a small logic unit. This architecture can provide sufficient throughput for some programs, but storage complexity remains high. Subsequently, researchers at the same university proposed a new DFT hardware architecture called Constant Multiplier (CM) DFT, which reduces the number of block random access memory (BRAM) and digital signal processing (DSP) slices compared to previous methods. Storage and computation speed are also key areas of research in 2D-DFT hardware design, leading to the proposal of a high-performance, ultra-long point DFT hardware implementation architecture and the design and implementation of a multi-core parallel 2D-DFT processor. The "row-column" algorithm is commonly used for 2D-DFT implementations on FPGAs. However, this algorithm introduces a significant DRAM row activation delay in memory stride access to external memory. To address this issue, many studies have optimized the energy consumption of 2D Fourier transform architectures. In addition, some researchers have proposed hybrid architectures capable of performing either 1D or 2D Fourier transforms, achieving a balance between high-speed processing and storage, but still leaving room for improvement in computational accuracy. The hardware implementation method has also attracted the attention of many scholars in China, and many universities, research institutions and companies have carried out active research and achieved fruitful results. Researchers in Taiwan, China have implemented a configurable DFT processor on an FPGA. This processor is based on a hybrid radiation algorithm and also adopts the SDF architecture. Its configurable architecture is achieved by bypassing specific processing elements. This processor can achieve flexible configuration, but its calculation speed is relatively slow.Existing technologies have proposed a reconfigurable Fourier transform design. The reconfigurable design modules can be connected as needed to meet the required number of Fourier transform points. In 2018, the butterfly arithmetic unit was optimized, reducing the number of multipliers and lowering power consumption. A ping-pong storage structure was adopted for the storage unit, improving data throughput. Simultaneously, floating-point operations were used to improve the processor's computational accuracy. In 2019, researchers designed a new 16-point DFT architecture, employing a twiddle factor merging method to reduce the number of multiplications, additions, and subtractions used in the design, and utilizing a common subexpression sharing scheme to optimize hardware resource sharing between twiddle factors. In 2020, researchers proposed a novel hybrid-radix reconfigurable DFT processor, consisting of a novel reconfigurable butterfly unit supporting "radix-2 / 3" DFT and multi-path parallel conflict-free memory, achieving multi-path data parallelism and operational continuity during the DFT process. Subsequently, in 2021, they...

[50] Furthermore, by optimizing conflict-free memory access rules and the twiddle factor generation scheme, and combining radix-2 and radix-8 time-domain decimation DFT algorithms, a high-performance hybrid radix DFT processor was designed to improve computational speed and hardware efficiency. In 2021, addressing the issue of excessive resource consumption by the twiddle factor module in DFT hardware implementation, researchers designed a high-performance single-path delay feedback structure for radix-2... 2 "The Fast Fourier Transform processor uses a hybrid approach of CORDIC and MCM to design the twitch factor module, achieving a DFT architecture that eliminates the need for conventional multipliers and reduces hardware resource consumption."

[0005] Based on the analysis of the above literature, it can be seen that although some progress has been made at the hardware implementation level, the above-mentioned digital hardware implementation schemes have the memory wall problem, resulting in problems such as high hardware power consumption and low real-time performance, which cannot meet the high-speed computing requirements under resource-constrained conditions. Summary of the Invention

[0006] The purpose of this invention is to break through the traditional implementation of Fourier transform, explore a new method for implementing Fourier transform based on in-memory computing technology, and innovatively propose a high-efficiency Fourier transform computing circuit from the perspective of analog circuits, thereby overcoming the shortcomings of existing technologies.

[0007] This invention is achieved through the following technical solution: Based on Fourier transform of in-memory computing technology, it innovatively proposes a high-efficiency Fourier transform calculation circuit from the perspective of analog circuits, analyzes the calculation rules of complex matrix multiplication, and establishes the corresponding circuit model.

[0008] Based on the circuit model, a memristor array circuit for complex matrix multiplication is designed and constructed; this includes designing a complex matrix multiplication operation circuit using a memristor array, expanding a programmable in-memory calculation circuit for one-dimensional Fourier transform and its inverse transform, studying the specific process of Fourier transform calculation based on the complex matrix multiplication circuit, designing corresponding calculation modules according to its calculation rules, and establishing circuit models for each module.

[0009] Based on the established circuit model, this study investigates the design of a programmable in-memory computing circuit for Fourier transform, studies the relationship between Fourier transform and its inverse transform, and then designs and implements a programmable in-memory computing circuit for inverse Fourier transform. Building upon the one-dimensional Fourier transform computing circuit, the study investigates the separability of the two-dimensional Fourier transform and constructs a circuit model. Based on the circuit model, the study investigates the design of a programmable in-memory computing circuit for the two-dimensional Fourier transform. Next, the study investigates the separability of the two-dimensional inverse Fourier transform, and then designs a computing circuit that can implement the two-dimensional inverse Fourier transform, which is then used to process two-dimensional signals such as image signals and video signals.

[0010] This invention includes the following steps:

[0011] Step 1: Design of the in-memory calculation circuit for complex matrix multiplication:

[0012] S1.1, Complex multiplication circuit design based on memristor array:

[0013] Suppose E, v, and w represent three different complex numbers, j is the imaginary unit, and v Re Let v be the real part of the complex number v. Im w is the imaginary part of the complex number v. Re Let w be the real part of the complex number w. Im Let be the imaginary part of the complex number w, where E represents the result of multiplying v and w, and their relationship is shown in equations (1) and (2).

[0014] E = v·w = (v Re +w Im ·j)·(w Re +w Im ·j)

[0015] =(v Re ·w Re -v Im ·w Im )+(v Re ·w Im +v Im ·w Re )·j (1)

[0016] Where v = v Re +v Im ·j,w=w Re +wIm ·j (2)

[0017] The real part of the complex number E is: v Re ·w Re -v Im ·w Im The imaginary part is: v Re ·w Im +v Im ·w Re ;

[0018] In equation (2), v Re With v Im The equivalent value is considered as the circuit's input voltage V. Re With v Im w Re with w Im The equal values ​​are respectively regarded as the conductance w of the first row. Re ′-G f With -(w Im ′-G f ), or the w in the second line Re ′-G f with w Im ′-G f The value of w. Re ′, w Im ′, G f All are resistance values.

[0019] The intuitive representation is shown in equation (3):

[0020] w Re =w Re ′-G f

[0021] w Im =-(w Im ′-G f ) or = w Im ′-G f (3)

[0022] Based on the virtual short and virtual open properties of operational amplifier A1, equation (4) can be derived:

[0023]

[0024] Where v f This is the value of the feedback voltage;

[0025] At this time, n=1, then v f =-(v Re +v Im According to Kirchhoff's laws, we can obtain equation (5):

[0026] i Re =v Re ·w Re ′+v Im ·w Im ′-(v Re +v Im )·G f

[0027] =v Re ·(w Re ′-G f )+v Im ·(w Im ′-G f )

[0028] i Im =v Re ·w Im ′+v Im ·w Re ′-(v Re +v Im )·G f

[0029] =v Re ·(w′ Im -G f )+v Im ·(w Re ′-G f (5)

[0030] In the above formula, i Re i Im These are two feedback calculation values;

[0031] Substituting equation (3) into equation (5), we obtain equation (6):

[0032] i Re =v Re ·w Re -v Im ·w Im i Im =v Re ·w Im +v Im ·w Re (6)

[0033] According to equation (6), i Re i Im The value of is the value of the real part and the imaginary part of the complex product E, thus completing the complex multiplication operation. Re i Im Converted into an equivalent voltage, it is named a complex multiplier;

[0034] S1.2, Design of a complex vector-matrix multiplication circuit based on memristor array:

[0035] The principle of complex vector-matrix multiplication is shown in equation (7).

[0036]

[0037] Where W is a complex matrix, V is a complex vector, j is the imaginary unit, and V jRe Let V be the real part of the complex vector V. jIm Let V be the imaginary part of the complex vector V, and I be the complex vector of the result of the operation;

[0038] Similar to the complex multiplication circuit, a general-purpose resistor G is introduced. f Due to the effect of operational amplifier A1, equation (8) is obtained.

[0039]

[0040] For each row, it can be found that

[0041]

[0042] Substituting equation (8) into equation (9), we can obtain

[0043]

[0044] Among them, W jRe and W jIm They are the real and imaginary parts of the complex numerical matrix to be calculated, and

[0045]

[0046] By using the memristor array W jRe ′ and W jIm Adjustments were made to make W jRe and W jIm The value of satisfies the complex vector-matrix multiplication calculation under different coefficients;

[0047] In a complex vector-matrix multiplication circuit, according to Kirchhoff's laws, each output current in the circuit is the result of a complex vector-matrix multiplication operation.

[0048] Step 2: Design of in-memory computation circuits for one-dimensional Fourier transform and its inverse transform:

[0049] The DFT expression for a finite-length sequence x(n) of length N is:

[0050]

[0051] in Rotation factor, j is the imaginary unit, e is the natural constant, and n is a variable from 0 to N-1:

[0052]

[0053] The DFT expression of a finite-length sequence x(n) of length N can be expanded into a matrix form as shown in equation (14).

[0054]

[0055] Therefore, an in-memory calculation circuit for one-dimensional Fourier transform is designed by combining an in-memory calculation circuit for multiplying real and complex matrices.

[0056] The circuit inputs are V0, V1, V2, ... V n-1 , representing the real number sequence x(0), x(1), x(2), ... x(n-1) of N points respectively; since the rotation factor has the case of complex numbers, the rotation factor is uniformly adjusted in the circuit to an in-memory calculation unit composed of real and imaginary parts, and the positive, negative and 0 values ​​are generated by adjusting the weight of the memristor, so as to realize the rotation factor with different values.

[0057] The input voltage is multiplied by the memristor matrix to obtain the output current. This current is then converted into an equivalent voltage by an operational amplifier circuit, resulting in the output voltage sequence V. 0Re V 0Im V 1Re V 1Im V 2Re V 2Im ,···V n-1Re V n-1Im That is, the result of the Fourier transform of the N-point real number sequence. Each value of the output result is composed of the real part voltage and the imaginary part voltage. Similarly, the in-memory calculation circuit design of the DFT is designed, and the in-memory calculation circuit design of its inverse transform can also be realized. The calculation formula of IDFT is shown in Equation (15).

[0058]

[0059] Its matrix calculation is expressed in the form of equation (16).

[0060]

[0061] Unlike the forward transform, the inverse transform takes a complex sequence as its input. Therefore, in circuit design, the real and imaginary voltages must be input separately. That is, the input is a complex vector, while its twitch factor is still a complex matrix. This utilizes the complex vector-matrix multiplication circuit method proposed in step 1. In addition, after converting to the output voltage, the output voltage needs to be multiplied by 1 / N. This completes the inverse Fourier transform calculation, and the imaginary voltage of the output is 0.

[0062] Step 3: Memory circuit design for two-dimensional Fourier transform and its inverse transform:

[0063] Two-dimensional (N1 x N2) DFT and IDFT can be defined as follows:

[0064]

[0065]

[0066] In equations (17) and (18), N1 and N2 can be of arbitrary dimensions. Assuming N1 = N2 = N, the transformations of the two-dimensional DFT and the two-dimensional IDFT in the above equations can be simplified as follows:

[0067]

[0068]

[0069] The separability of two-dimensional DFT and two-dimensional IDFT can be expressed by rewriting equations (19) and (20) as follows:

[0070]

[0071]

[0072] Equation (21) is to perform a one-dimensional DFT on the two-dimensional sequence x(n1,n2) along the column direction, and then perform a one-dimensional DFT on the resulting matrix along the row direction; perform N one-dimensional DFTs on each column, with each column having a length of N, and then perform N one-dimensional DFTs on each row, with each row having a length of N.

[0073] Equation (22) is to perform a one-dimensional IDFT on the two-dimensional sequence X(k1,k2) along the column direction, and then perform a one-dimensional IDFT on the resulting matrix along the row direction; perform N one-dimensional IDFTs on each column, with each column having a length of N, and then perform N one-dimensional IDFTs on each row, with each row having a length of N.

[0074] Based on the one-dimensional Fourier transform circuit, a two-dimensional Fourier transform circuit is designed.

[0075] The beneficial effects of this invention are that it breaks through the traditional implementation method of Fourier transform and explores a high-energy-efficiency hardware implementation method of in-memory computing analog Fourier transform; this invention has significant scientific significance and potential economic benefits for the implementation of real-time Fourier transform; the research results can be widely applied to signal processing in the Internet of Things field, which will help to form core intellectual property rights in this field. Attached Figure Description

[0076] Figure 1 Design a circuit for complex number multiplication;

[0077] Figure 2 Design of a circuit for complex vector-matrix multiplication;

[0078] Figure 3 A graph showing the calculation of the rotation factor;

[0079] Figure 4 This is an N-point DFT circuit diagram;

[0080] Figure 5 This is an N-point IDFT circuit diagram;

[0081] Figure 6 For the separability of 2D-DFT;

[0082] Figure 7 For the separability of 2D-IDFT;

[0083] Figure 8 The circuit diagram for 4-point DFT in-memory computation (real number input sequence);

[0084] Figure 9 The circuit diagram for 4-point DFT in-memory computation (complex input sequence);

[0085] Figure 10 This is a thumbnail of the 4-point DFT in-memory computation.

[0086] Figure 11 A simplified diagram of a 4x4 2D-DFT circuit;

[0087] Figure 12 This is a circuit diagram for 4-point IDFT memory computation.

[0088] Figure 13 This is a thumbnail of the 4-point IDFT in-memory computation.

[0089] Figure 14 A simplified diagram of a 4x4 two-dimensional inverse Fourier transform circuit;

[0090] Figure 15 This is a flowchart of a one-dimensional convolution process;

[0091] Figure 16 This is a flowchart of a two-dimensional convolution process;

[0092] Figure 17 This is a flowchart of the low-pass filtering process for the in-memory computing circuit. Detailed Implementation

[0093] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present invention. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concept of the present invention; moreover, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale; the following description, with reference to the accompanying drawings... Figures 1 to 17 This invention describes a programmable Fourier transform in-memory computing circuit based on in-memory computing technology. It innovatively proposes a high-efficiency Fourier transform computing circuit from an analog circuit perspective, analyzes the calculation rules of complex matrix multiplication, and establishes the corresponding circuit model.

[0094] Based on the circuit model, a memristor array circuit for complex matrix multiplication is designed and constructed. This includes designing a complex matrix multiplication operation circuit using a memristor array, expanding a programmable in-memory computing circuit for one-dimensional Fourier transform and its inverse transform, studying the specific process of Fourier transform calculation based on the complex matrix multiplication circuit, designing corresponding computing modules according to its calculation rules, and establishing circuit models for each module. Based on the established circuit models, the design of a programmable in-memory computing circuit for Fourier transform is studied, the relationship between Fourier transform and its inverse transform is investigated, and then a programmable in-memory computing circuit for implementing the inverse Fourier transform is designed. Based on the one-dimensional Fourier transform computing circuit, the separability of the two-dimensional Fourier transform is studied, and a circuit model is constructed. Based on the circuit model, the design of a programmable in-memory computing circuit for the two-dimensional Fourier transform is studied. Then, the separability of the two-dimensional inverse Fourier transform is studied, and a computing circuit that can implement the two-dimensional inverse Fourier transform is designed and used to process two-dimensional signals such as image signals and video signals.

[0095] This invention includes the following steps:

[0096] Step 1: Design of the in-memory calculation circuit for complex matrix multiplication:

[0097] S1.1, Complex multiplication circuit design based on memristor array:

[0098] Suppose E, v, and w represent three different complex numbers, j is the imaginary unit, and v Re Let v be the real part of the complex number v. Imw is the imaginary part of the complex number v. Re Let w be the real part of the complex number w. Im Let be the imaginary part of the complex number w, where E represents the result of multiplying v and w, and their relationship is shown in equations (1) and (2).

[0099] E = v·w = (v Re +w Im ·j)·(w Re +w Im ·j)

[0100] =(v Re ·w Re -v Im ·w Im )+(v Re ·w Im +v Im ·w Re )·j (1)

[0101] Where v = v Re +v Im ·j,w=w Re +w Im ·j (2)

[0102] The real part of the complex number E is: v Re ·w Re -v Im ·w Im The imaginary part is: v Re ·w Im +v Im ·w Re ;

[0103] like Figure 1 The circuit shown can perform complex number multiplication. In equation (2), v Re With v Im The equivalent value is considered as the circuit's input voltage V. Re With v Im w Re with w Im The equal values ​​are respectively regarded as the conductance w of the first row. Re ′-G f With -(w Im ′-G f ), or the w in the second line Re ′-G f with w Im ′-G f The value of w. Re ′, w Im ′, G f All are resistance values;

[0104] The intuitive representation is shown in equation (3):

[0105] w Re =w Re ′-G f

[0106] w Im =-(w Im ′-G f ) or = w Im ′-G f (3)

[0107] Based on the virtual short and virtual open properties of operational amplifier A1, equation (4) can be derived:

[0108]

[0109] Where v f This is the value of the feedback voltage;

[0110] At this time, n=1, then v f =-(v Re +v Im According to Kirchhoff's laws, we can obtain equation (5):

[0111] i Re =v Re ·w Re ′+v Im ·w Im ′-(v Re +v Im )·G f

[0112] =v Re ·(w Re ′-G f )+v Im ·(w Im ′-G f )

[0113] i Im =v Re ·w Im ′+v Im ·w Re ′-(v Re +v Im )·G f

[0114] =v Re ·(w′ Im -G f )+v Im ·(w Re ′-G f (5)

[0115] In the above formula, i Re i Im These are two feedback calculation values;

[0116] Substituting equation (3) into equation (5), we obtain equation (6):

[0117] i Re =v Re ·w Re -v Im ·w Im i Im =v Re ·w Im +v Im ·w Re (6)

[0118] According to equation (6), i Re i Im The value of is the value of the real part and the imaginary part of the complex product E, thus completing the complex multiplication operation. Re i Im Convert to an equivalent voltage and simplify the circuit diagram to Figure 1 As shown on the right, it is named the complex multiplier;

[0119] S1.2, Design of a complex vector-matrix multiplication circuit based on memristor array:

[0120] The principle of complex vector-matrix multiplication is shown in equation (7).

[0121]

[0122] Where W is a complex matrix, V is a complex vector, j is the imaginary unit, and V jRe Let V be the real part of the complex vector V. jIm Let V be the imaginary part of the complex vector V, and I be the complex vector of the result of the operation;

[0123] Figure 2 The circuit shown can be represented by equation (7), where a pair of input voltages correspond to the real and imaginary parts of a complex unit in the operational vector, and the array of four memristors corresponds to the real and imaginary parts of a complex unit in the operational matrix. The output current represents the complex vector after the operation is completed, and a pair of currents represents the real and imaginary parts of a complex unit.

[0124] Similar to the complex multiplication circuit, a general-purpose resistor G is introduced. f Due to the effect of operational amplifier A1, equation (8) is obtained.

[0125]

[0126] For each row, it can be found

[0127]

[0128] Substituting equation (8) into equation (9), we can obtain

[0129]

[0130] Among them, W jRe and W jIm They are the real and imaginary parts of the complex numerical matrix to be calculated, and

[0131]

[0132] By using the memristor array W jRe ′ and W jIm Adjustments were made to make W jRe and W jIm The value of satisfies the complex vector-matrix multiplication calculation under different coefficients;

[0133] In a complex vector-matrix multiplication circuit, according to Kirchhoff's laws, each output current in the circuit is the result of a complex vector-matrix multiplication operation.

[0134] Step 2: In-memory computation circuit design for one-dimensional Fourier transform and its inverse transform:

[0135] The DFT expression for a finite-length sequence x(n) of length N is:

[0136]

[0137] in Rotation factor, j is the imaginary unit, e is the natural constant, and n is a variable from 0 to N-1:

[0138]

[0139] It can be done Figure 3 The rotation factor is calculated in the following way: the horizontal axis represents the real part of the rotation factor, and the vertical axis represents the imaginary part of the rotation factor. The entire circle is always divided into N equal parts. When N = 8, the entire circle is divided into 8 equal parts.

[0140] In fact, the DFT expression of a finite-length sequence x(n) of length N can be expanded into a matrix form, as shown in equation (14).

[0141]

[0142] Therefore, an in-memory calculation circuit for one-dimensional Fourier transform is designed by combining an in-memory calculation circuit for multiplying real and complex matrices.

[0143] Figure 4 The diagram shows an N-point Fourier transform memory calculation circuit. The circuit inputs are V0, V1, V2, ..., V... n-1 , representing the real number sequence x(0), x(1), x(2), ... x(n-1) of N points respectively; since the rotation factor has the case of complex numbers, the rotation factor is uniformly adjusted in the circuit to an in-memory calculation unit composed of real and imaginary parts, and the positive, negative and 0 values ​​are generated by adjusting the weight of the memristor, so as to realize the rotation factor with different values.

[0144] The input voltage is multiplied by the memristor matrix to obtain the output current. This current is then converted into an equivalent voltage by an operational amplifier circuit, resulting in the output voltage sequence V. 0Re V 0Im V 1Re V 1Im V 2Re V 2Im ,···V n-1Re V n-1Im That is, the result of the Fourier transform of the N-point real number sequence, and each value of the output result is composed of the real part voltage and the imaginary part voltage;

[0145] Similarly, the in-memory computation circuit design for DFT can also realize the in-memory computation circuit design for its inverse transformation. The calculation formula for IDFT is shown in equation (15).

[0146]

[0147] Its matrix calculation is expressed in the form of equation (16).

[0148]

[0149] Figure 5 This is the in-memory calculation circuit design diagram for the N-point IDFT. Unlike the forward transform, the input sequence for the inverse transform is a complex sequence. Therefore, the circuit design requires separate input of the real and imaginary voltages. That is, the input is a complex vector, while its twitch factor is still a complex matrix. This utilizes the complex vector-matrix multiplication circuit method proposed in step 1. In addition, after finally converting to the output voltage, the output voltage needs to be multiplied by 1 / N. This completes the inverse Fourier transform calculation, and the imaginary voltage of the output is 0.

[0150] Step 3: Memory circuit design for two-dimensional Fourier transform and its inverse transform:

[0151] Two-dimensional (N1 x N2) DFT and IDFT can be defined as follows:

[0152]

[0153]

[0154]

[0155] In equations (17) and (18), N1 and N2 can be of arbitrary dimensions. Assuming N1 = N2 = N, the transformations of the two-dimensional DFT and the two-dimensional IDFT in the above equations can be simplified as follows:

[0156]

[0157]

[0158] The separability of two-dimensional DFT and two-dimensional IDFT can be expressed by rewriting equations (19) and (20) as follows:

[0159]

[0160]

[0161] Equation (21) involves performing a one-dimensional DFT on the two-dimensional sequence x(n1,n2) along the column direction, and then performing a one-dimensional DFT on the resulting matrix along the row direction. The transformation process is as follows: Figure 6 As shown, first, N one-dimensional DFTs are performed on each column, with each column having a length of N. Then, N one-dimensional DFTs are performed on each row, with each row having a length of N.

[0162] Equation (22) involves performing a one-dimensional IDFT on the two-dimensional sequence X(k1,k2) along the column direction, and then performing a one-dimensional IDFT on the resulting matrix along the row direction. The transformation process is as follows: Figure 7 As shown, firstly, N one-dimensional IDFTs are performed on each column, with each column having a length of N. Then, N one-dimensional IDFTs are performed on each row, with each row having a length of N.

[0163] Based on the one-dimensional Fourier transform circuit, a two-dimensional Fourier transform circuit is designed. The design process is illustrated below using a 4x4 matrix as an example. First, the in-memory calculation circuit for the 4-point one-dimensional DFT is designed, categorized into two cases based on whether the input sequence contains real or complex numbers. Figure 8 and Figure 9 use Figure 10 The diagrams (left: real input sequence, right: complex input sequence) are replaced with thumbnails, with different colors representing different forms of input sequences. Based on the separability of 2D-DFT, a simplified diagram of the designed 4x42D-DFT circuit is shown below. Figure 11 (Column DFT: real input sequence, row DFT: complex input sequence) as shown. Figure 11Parallel computing circuit units are used to process the two-dimensional signal. During the input phase, the four-point sampled signal of each column is input into four different four-point one-dimensional DFT circuits, with each column using a reverse input method. For example, the first column is V... C11 V C12 V C13 V C14 The reverse order result is V. C11 V C13 V C12 V C14 Since the input is a sequence of real numbers, the column DFT transformation stage uses... Figure 8 The 4-point basis DFT circuit shown calculates all four columns simultaneously. Next, a row DFT transform is performed, so the column DFT results need to be reordered. Since the input to the row transform is a complex sequence, a [missing information - likely a specific method or technique] is used in the row DFT transform stage. Figure 9 The 4-point DFT circuit shown calculates all four lines simultaneously. The final output is a sequential V. C11‘ V C21‘ ,···V C34‘ V C44‘ Each output contains both real and imaginary parts. The circuit described above employs parallel computing, enabling in-memory computation of the two-dimensional Fourier transform from input to output.

[0164] like Figure 12 The diagram shown is a circuit diagram for 4-point IDFT memory calculation.

[0165] Will Figure 12 Simplified to Figure 13 The thumbnail is used instead.

[0166] Based on the separability of 2D-IDFT, a simplified diagram of the designed 4x4 2D-IDFT circuit is shown below. Figure 14 As shown. Figure 14 Parallel computing circuit units are used to perform inverse Fourier transform processing on two-dimensional signals. The circuit calculation principle is the same as that of 2D-DFT, where the sampled sequence is input into the circuit in reverse order to complete the calculation and obtain the final output.

[0167] Step 4: Application of Fourier transform calculation circuit in image convolution and filtering:

[0168] Convolution is widely used in signal processing and image processing. One-dimensional linear convolution: A sequence x(n) of length M and a sequence h(n) of length L undergo linear convolution to obtain a sequence y(n) of length M+L-1. When N>M+L-1, linear convolution can be solved using the Discrete Fourier Transform (DFT). The two sequences x(n) and h(n) are zero-padded and multiplied in the DFT domain to achieve circular convolution. One period of this result is the linear convolution result. This process can be... Figure 15 As shown. Given a sequence of M points {x(n)} = {x0, x1, ..., xn}. M-1 A sequence of L points {h(n)} = {h0, h1, ..., h...} L-1 Then calculate their convolution:

[0169] 1) Add NM zeros to the end of the sequence x(n) to obtain {x e (n)}={x0,x1…,x M-1 ,0,0…,0}, and N≥M+L-1.

[0170] 2) Add NM zeros to the end of the sequence h(n) to obtain {h e (n)}={h0,h1…,h L-1 ,0,0…,0}, and N≥M+L-1.

[0171] 3) Calculate {x} e The N-point DFT of (n)} yields {X e F (k)}, k=0,1…,N-1.

[0172] 4) Repeat step 3) to calculate {h} e The N-point DFT of (n)} yields {H e F (k)}, k=0,1…,N-1.

[0173] 5) Place {X e F (k)} and {H e F Multiplying (k) together yields {X} e F (k)}{H e F (k)}, k=0,1…,N-1.

[0174] 6) For {X e F (k)}{H e FPerforming an N-point IDFT on x(n) yields y(n), where n = 0, 1, ..., N-1. This is the result of the linear convolution of x(n) and y(n).

[0175] It is easy to see from the above convolution process that the one-dimensional DFT and IDFT in-memory computing circuits designed in this project can be applied to signal convolution processing to realize parallel signal processing and computing.

[0176] In addition, many signals are represented in two-dimensional form in practical applications, thus requiring the computation of two-dimensional convolutions. The following is a detailed process for calculating two-dimensional convolutions using 2D-DFT and 2D-IDFT. Figure 16 express:

[0177] 1) For a two-dimensional sequence x(n1,n2), add N1-(M1-1) zeros along the n1 direction and N2-(M2-1) zeros along the n2 direction. ext (n1, n2) is obtained by expanding the original size M1×M2 to a size N1×N2. And it satisfies N1≥M1+L1-1, N2≥M2+L2-1.

[0178] 2) For a two-dimensional sequence y(n1,n2), add N1-(L1-1) zeros along the n1 direction and N2-(L2-1) zeros along the n2 direction. ext (n1, n2) is obtained by expanding the original size L1×L2 to a size N1×N2. And it satisfies N1≥M1+L1-1, N2≥M2+L2-1.

[0179] 3) For x ext Calculate X using 2D-DFT (n1, n2). e F (k1,k2),k1,k2=0,1…,N-1.

[0180] 4) For y ext Calculate the 2D-DFT of (n1,n2) to obtain Y. e F (k1,k2),k1,k2=0,1…,N-1.

[0181] 5) X e F (k1,k2) and Y e F Multiplying (k1, k2) gives X. e F (k1,k2)Y e F (k1,k2),k1,k2=0,1…,N-1.

[0182] 6) Regarding X e F (k1,k2)Y e F (k1,k2) Calculate 2D-IDFT to obtain the non-periodic convolution of x(n1,n2) and y(n1,n2).

[0183] Therefore, a circuit capable of performing two-dimensional sequence convolution calculations can be constructed using the designed 2D-DFT and 2D-IDFT in-memory computing circuits. This method enables parallel computation of two-dimensional signal convolution, achieving fast and efficient signal processing. For image processing, the most common processing method is filtering, and the essence of filtering is convolution. A noisy image can be used as the original signal input, and the other input is the convolution kernel. By inputting these two signals into the circuit for calculation, the convolution result can be obtained. Different image processing effects, such as smoothing and sharpening, can be achieved by adjusting the size and specific value of the convolution kernel. Figure 17 The diagram shows a schematic flowchart of image low-pass filtering using a circuit. The input two-dimensional image signal is converted to the frequency domain by a two-dimensional Fourier transform, then multiplied by the designed low-pass filter matrix to remove high-frequency components, and finally undergoes a two-dimensional inverse Fourier transform to obtain the filtered image signal.

[0184] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A programmable Fourier transform memory computing circuit, characterized in that: Based on in-memory computing technology, this paper proposes a high-efficiency Fourier transform calculation circuit from the perspective of analog circuits, analyzes the calculation rules of complex matrix multiplication, and establishes the corresponding circuit model. Based on the circuit model, a memristor array circuit for complex matrix multiplication was designed and constructed. This included designing a complex matrix multiplication operation circuit using a memristor array, expanding a programmable in-memory calculation circuit for one-dimensional Fourier transform and its inverse transform, studying the specific process of Fourier transform calculation based on the complex matrix multiplication circuit, designing corresponding calculation modules according to its calculation rules, and establishing circuit models for each module. The design is as follows: The DFT expression for a finite-length sequence x(n) of length N is: in Rotation factor, j is the imaginary unit, e is the natural constant, and n is a variable from 0 to N-1: The DFT expression of a finite-length sequence x(n) of length N can be expanded into a matrix form as shown in equation (14). Therefore, an in-memory calculation circuit for one-dimensional Fourier transform is designed by combining an in-memory calculation circuit for multiplying real and complex matrices. The circuit inputs are V0, V1, V2, ... V n-1 Let x(0), x(1), x(2), ..., x(n-1) be the real number sequences of points N respectively. Since the rotation factor can be complex, the rotation factor in the circuit is uniformly adjusted to an in-memory calculation unit composed of real and imaginary parts. Positive, negative and 0 values ​​are generated by adjusting the weight of the memristor, thereby realizing different values ​​of the rotation factor. The input voltage is multiplied by the memristor matrix to obtain the output current. This current is then converted into an equivalent voltage by an operational amplifier circuit, resulting in the output voltage sequence V. 0Re V 0Im V 1Re V 1Im V 2Re V 2Im ,···V n-1Re V n-1Im That is, the result of the Fourier transform of the N-point real number sequence, and each value of the output result is composed of the real part voltage and the imaginary part voltage; Similarly, the in-memory computation circuit design for DFT can also realize the in-memory computation circuit design for its inverse transformation. The calculation formula for IDFT is shown in equation (15). Its matrix calculation is expressed in the form of equation (16). Unlike the forward transform, the inverse transform takes a complex sequence as its input. Therefore, in circuit design, the real and imaginary voltages must be input separately. That is, the input is a complex vector, while its twitch factor is still a complex matrix. This utilizes the complex vector-matrix multiplication circuit method proposed in step 1. In addition, after converting to the output voltage, the output voltage needs to be multiplied by 1 / N. This completes the inverse Fourier transform calculation, and the imaginary voltage of the output is 0. Based on the established circuit model, the design of a programmable in-memory computing circuit for Fourier transform is studied, the relationship between Fourier transform and its inverse transform is studied, and then a programmable in-memory computing circuit for inverse Fourier transform is designed and implemented. Based on the one-dimensional Fourier transform calculation circuit, the separability of the two-dimensional Fourier transform is studied, and a circuit model is constructed. Based on the circuit model, the design of a programmable in-memory computing circuit for two-dimensional Fourier transform is studied. Then, the separability of the inverse two-dimensional Fourier transform is studied, and a computing circuit that can realize the inverse two-dimensional Fourier transform is designed to process two-dimensional signals such as image signals and video signals.

2. The programmable Fourier transform in-memory computing circuit according to claim 1, characterized in that... Includes the following steps: Step 1: Design of the in-memory calculation circuit for complex matrix multiplication: S1.1, Complex multiplication circuit design based on memristor array: Suppose that E, v, and w represent three different complex numbers, where E represents the product of v and w, and their relationship is shown in equations (1) and (2). E=v·w=(v Re +w Im ·j)·(w Re +w Im j) =(v Re ·w Re -v Im ·w Im )+(v Re ·w Im +v Im ·w Re )·j (1) where v = v Re + v Im · j, w = w Re + w Im · j(2) The real part of the complex number E is: v Re ·w Re -v Im ·w Im The imaginary part is: v Re ·w Im +v Im ·w Re j is the imaginary unit, v Re Let v be the real part of the complex number v. Im w is the imaginary part of the complex number v. Re Let w be the real part of the complex number w. Im Let w be the imaginary part of the complex number w; In equation (2), v Re With v Im The equivalent value is considered as the circuit's input voltage V. Re With v Im w Re with w Im The equal values ​​are respectively regarded as the conductance w of the first row. Re ′-G f With -(w Im ′-G f ), or the w in the second line Re ′-G f with w Im ′-G f The value of w, where w Re ′, w Im ′, G f All are resistance values; intuitively represented as shown in equation (3): w Re =w Re ′-G f w Im = -(w Im ′ - G f ) or = w Im ′ - G f (3) Based on the virtual short and virtual open properties of operational amplifier A1, equation (4) is derived: Where v f This is the value of the feedback voltage; At this time, n=1, then v f =-(v Re +v Im According to Kirchhoff's laws, we obtain equation (5): i Re =v Re ·w Re ′+v Im ·w Im ′-(v Re +v Im )·G f =v Re ·(w Re ′-G f )+v Im ·(w Im ′-G f ) i Im =v Re ·w Im ′+v Im ·w Re ′-(v Re +v Im )·G f =v Re ·(w′ Im -G f )+v Im ·(w Re ′-G f ) (5) In the above formula, i Re i Im These are two feedback calculation values; Substituting equation (3) into equation (5), we obtain equation (6): i Re =v Re ·w Re -v Im ·w Im ,i Im =v Re ·w Im +v Im ·w Re (6) According to equation (6), i Re i Im The value of is the value of the real part and the imaginary part of the complex product E, thus completing the complex multiplication operation; i Re i Im Converted into an equivalent voltage, it is named a complex multiplier; S1.2, Design of a complex vector-matrix multiplication circuit based on memristor array: The principle of complex vector-matrix multiplication is shown in equation (7). Where W is a complex matrix, V is a complex vector, j is the imaginary unit, and V jRe Let V be the real part of the complex vector V. jIm Let V be the imaginary part of the complex vector V, and I be the complex vector of the result of the operation; Similar to the complex multiplication circuit, a general-purpose resistor G is introduced. f Due to the effect of operational amplifier A1, equation (8) is obtained, where V f This is the value of the feedback voltage; For each row found Substituting equation (8) into equation (9) yields Among them, W jRe and W jIm They are the real and imaginary parts of the complex numerical matrix to be calculated, and By using the memristor array W jRe ′ and W jIm Adjustments were made to make W jRe and W jIm The value of satisfies the complex vector-matrix multiplication calculation under different coefficients; In a complex vector-matrix multiplication circuit, according to Kirchhoff's laws, each output current in the circuit is the result of a complex vector-matrix multiplication operation. Step 2: Design of in-memory computing circuit for one-dimensional Fourier transform and its inverse transform; Step 3: Memory circuit design for two-dimensional Fourier transform and its inverse transform: The two-dimensional (N1 x N2) DFT and IDFT are defined as follows: In equations (17) and (18), N1 and N2 are arbitrary dimensions. Assuming N1 = N2 = N, then the above equations regarding the two-dimensional DFT... The transformation of the two-dimensional IDFT is simplified as follows: The separability of the two-dimensional DFT and the two-dimensional IDFT can be expressed by rewriting equations (19) and (20) as follows: Equation (21) is to perform a one-dimensional DFT on the two-dimensional sequence x(n1,n2) along the column direction, and then perform a one-dimensional DFT on the resulting matrix along the row direction; perform N one-dimensional DFTs on each column, with each column having a length of N, and then perform N one-dimensional DFTs on each row, with each row having a length of N. Equation (22) is to perform a one-dimensional IDFT on the two-dimensional sequence X(k1,k2) along the column direction, and then perform a one-dimensional IDFT on the resulting matrix along the row direction; perform N one-dimensional IDFTs on each column, with each column having a length of N, and then perform N one-dimensional IDFTs on each row, with each row having a length of N. Based on the one-dimensional Fourier transform circuit, a two-dimensional Fourier transform circuit is designed.

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