Semiconductor memory device and method of operating a semiconductor memory device

Abstract

Embodiments of the present disclosure relate to a semiconductor memory device and an operating method of a semiconductor memory device. A method of operating a semiconductor memory device to program selected memory cells to store a data bit in each of the selected memory cells includes fuzzy programming and fine programming.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0120307, ​​filed on September 9, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to electronic devices, and more specifically to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can have a two-dimensional structure in which they are arranged in a horizontal direction on a semiconductor substrate, or a three-dimensional structure in which they are arranged in a vertical direction on a semiconductor substrate. Three-dimensional memory devices are designed to overcome the limited integration density of two-dimensional memory devices and can include multiple memory cells vertically stacked on a semiconductor substrate. A controller can control the operation of the semiconductor memory device. Summary of the Invention

[0005] According to one embodiment of this disclosure, a method of operating a semiconductor memory device to program selected memory cells to store N bits of data in each selected memory cell may include: fuzzy programming, used to increase a threshold voltage of a first memory cell to an intermediate programming state by using an intermediate verification voltage, the first memory cell to be programmed to a first to (2)th... N -1) The (2nd)th step in the target programming state N-1 ) to (2) N -1) Target programming state; and fine programming, used by using the first to (2) N -1) Verify the voltage to program the selected memory cell to the target programming state, where fine programming includes: increasing the number of cells to be programmed to the (2)th programming state. N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state, and the increase in the voltage to be programmed to the first to (2) N-1 -1) The threshold voltage of the second memory cell in the target programming state (where N is a natural number).

[0006] According to one embodiment of this disclosure, a method of operating a semiconductor memory device to program selected memory cells to store N bits of data in each selected memory cell may include: fuzzy programming, used to increase a threshold voltage of a first memory cell to an intermediate programming state by using an intermediate verification voltage, the first memory cell to be programmed to a first to (2)th... N -1) The (2nd)th step in the target programming stateN-1 ) to (2) N -1) Target programming state; and fine programming, used by using the first to (2) N -1) Verify the voltage to program the selected memory cell to the target programming state, where fine programming includes: increasing the number of cells to be programmed to the first to (2)th programming state. N-1 -1) The threshold voltage of the second memory cell in the target programming state, and the increase to be programmed to the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state (where N is a natural number).

[0007] According to one embodiment of this disclosure, a method of operating a semiconductor memory device to program selected memory cells to store N bits of data in each selected memory cell may include: first fuzzy programming, used to increase a threshold voltage of a first memory cell to a first intermediate programming state by using an intermediate verification voltage, the first memory cell to be programmed to a first to (2)th intermediate programming state. N -1) The (2nd)th step in the target programming state N-1 ) to (2) N -1) Target programming state; Second fuzzy programming, used by using a (2)th fuzzy programming voltage greater than the intermediate verification voltage. N -1) Verify the voltage to be programmed to the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state is increased from the first intermediate programming voltage to the second intermediate programming state; and fine programming is used to program the selected memory cell to the target programming state (where N is a natural number). Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a memory system including a semiconductor memory device and a controller according to an embodiment of the present disclosure;

[0009] Figure 2 It's a diagram. Figure 1 The diagram shows a block diagram of a semiconductor memory device.

[0010] Figure 3 It's a diagram. Figure 2 A diagram illustrating an embodiment of the memory cell array shown;

[0011] Figure 4 It's a diagram. Figure 3 The circuit diagram of one of the memory blocks (BLKa) from BLK1 to BLKz is shown;

[0012] Figure 5 It's a diagram. Figure 3 A circuit diagram of another embodiment of one of the memory blocks BLK1 to BLKz (BLKb) shown;

[0013] Figure 6 It is illustrated in Figure 2 A circuit diagram of an embodiment of a memory block (BLKc) included in the memory cell array 110 shown;

[0014] Figure 7 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 8 It's a diagram. Figure 7 A flowchart of an embodiment of step S100 shown;

[0016] Figure 9 It's a diagram. Figure 7 A flowchart of an embodiment of step S200 shown;

[0017] Figure 10 The diagram illustrates when based on Figure 7 , Figure 8 and Figure 9 A diagram illustrating the threshold voltage distribution of the selected memory cells when the method shown performs programming operations;

[0018] Figure 11 The diagram illustrates when based on Figure 7 , Figure 8 and Figure 9 The diagram illustrates the threshold voltage distribution of the selected memory cell when a sudden power outage (SPO) occurs during programming operations as shown in the illustration.

[0019] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure;

[0020] Figure 13 It's a diagram. Figure 12 A flowchart of an embodiment of step S210 shown;

[0021] Figure 14 It's a diagram. Figure 12 A flowchart of an embodiment of step S230 shown;

[0022] Figure 15 The diagram illustrates when based on Figure 12 , Figure 13 and Figure 14 A diagram illustrating the threshold voltage distribution of the selected memory cells when the programming operation is performed using the method shown.

[0023] Figure 16 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure;

[0024] Figure 17 It's a diagram. Figure 16 A flowchart of an embodiment of step S220 shown;

[0025] Figure 18 It's a diagram. Figure 16 A flowchart of an embodiment of step S240 shown;

[0026] Figure 19 The diagram illustrates when based on Figure 16 , Figure 17 and Figure 18 A diagram illustrating the threshold voltage distribution of the selected memory cells when the programming operation is performed using the method shown.

[0027] Figure 20 It's a diagram. Figure 7 A flowchart of another embodiment of step S200;

[0028] Figure 21 The diagram illustrates when based on Figure 7 , Figure 8 and Figure 20 A diagram illustrating the threshold voltage distribution of the selected memory cells when the programming operation is performed using the method shown.

[0029] Figure 22 It's a diagram. Figure 7 A flowchart of another embodiment of step S200;

[0030] Figure 23 The diagram illustrates when based on Figure 7 , Figure 8 and Figure 22 A diagram illustrating the threshold voltage distribution of the selected memory cells when the programming operation is performed using the method shown.

[0031] Figure 24 It's a diagram. Figure 7 A flowchart of another embodiment of step S200;

[0032] Figure 25 It's a diagram. Figure 7 A flowchart of another embodiment of step S200;

[0033] Figure 26 It's a diagram. Figure 1 A block diagram of an example controller is shown;

[0034] Figure 27 It's a diagram. Figure 26 A block diagram illustrating an application example of the memory system shown; and

[0035] Figure 28 The diagram includes the references above. Figure 27 A block diagram of the computing system describing the memory system. Detailed Implementation

[0036] The specific structural or functional descriptions of examples of embodiments of the concept disclosed in this specification are merely illustrative for the purpose of describing examples of embodiments of the concept, and examples of embodiments of the concept may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0037] Various embodiments are directed to semiconductor memory devices and methods of operation thereof that can improve data reliability.

[0038] In one embodiment, the intermediate verification voltage can be less than the (2)th verification voltage. N-1 Verify the voltage.

[0039] In one embodiment, fuzzy programming may include: applying a programming disable voltage to a bit line coupled to a memory cell to be programmed into an intermediate programming state; applying a programming enable voltage to a bit line coupled to an incompletely programmed memory cell among the memory cells to be programmed into the intermediate programming state; applying a programming voltage to a word line coupled to a selected memory cell; and performing a verification operation on the memory cell to be programmed into the intermediate programming state using an intermediate verification voltage.

[0040] In one embodiment, fine programming may include: using the (2) N-1 ) to (2) N -1) Verify the voltage, increase the voltage to be programmed to (2) N-1 ) to (2) N -1) The threshold voltage of the memory cell in the target programming state; and by using the first to (2) N-1 -1) Verify the voltage, increase the voltage to be programmed to the first to (2) N-1 -1) Threshold voltage of the memory cell in the target programming state.

[0041] In one embodiment, the number to be programmed to (2) N-1 ) to (2) N -1) The threshold voltage of the memory cell in the target programming state may include: applying a programming disable voltage to the memory cell in the selected memory cell that is fully programmed to the corresponding target programming state and to the first to (2) N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2)N -1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying programming voltage to word lines coupled to the selected memory cells; and using the (2) N-1 ) to (2) N -1) Verify the voltage, to be programmed to (2) N-1 ) to (2) N -1) The memory cell in the target programming state performs a verification operation.

[0042] In one embodiment, add to be programmed to the first through (2) N-1 -1) The threshold voltage of the memory cell in the target programming state may include: applying a programming disable voltage to the memory cell in the selected memory cell that is fully programmed to the corresponding target programming state and to the (2) N-1 ) to (2) N -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the first to (2) N-1 -1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying programming voltage to word lines coupled to the selected memory cells; and using the first to (2) N-1 -1) Verify the voltage, to be programmed to the first to (2) N-1 -1) The memory cell in the target programming state performs a verification operation.

[0043] In one embodiment, fine programming may include: applying a programming disable voltage to a memory cell within a selected memory cell that is fully programmed to the corresponding target programming state and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying a first programming voltage to word lines coupled to the selected memory cells; applying a programming disable voltage to the memory cells within the selected memory cells that are fully programmed to the corresponding target programming state and to the (2) bit lines coupled to the target programming state memory cells. N-1 ) to (2) N -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the first to (2) N-1-1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying a second programming voltage less than the first programming voltage to word lines coupled to the selected memory cells; and using the first to (2) N -1) Verify voltage, perform verification operation on the selected memory cell.

[0044] In one embodiment, fine programming may include: applying a programming disable voltage to a memory cell within a selected memory cell that is fully programmed to the corresponding target programming state and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to unprogrammed memory cells in the target programming state; applying a first programming voltage to word lines coupled to the selected memory cells; applying a programming disable voltage to bit lines coupled to fully programmed memory cells in the selected memory cells; applying a programming enable voltage to bit lines coupled to unprogrammed memory cells in the selected memory cells; applying a second programming voltage less than the first programming voltage to word lines coupled to the selected memory cells; and using the first to (2) N-1 The verification voltage is used to perform a verification operation on the selected memory cell. In one embodiment, N can be 3.

[0045] In one embodiment, fine programming may include: applying a programming disable voltage to a memory cell within a selected memory cell that is fully programmed to the corresponding target programming state, and to the (2) N-1 ) to (2) N -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the first to (2) N-1 -1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying a first programming voltage to word lines coupled to the selected memory cells; applying a programming disable voltage to the memory cells within the selected memory cells that are fully programmed to the corresponding target programming state and to the first to (2) word lines coupled to the target programming state memory cells. N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2) N-1) Bit lines coupled to unprogrammed memory cells within the target programming state; applying a second programming voltage greater than the first programming voltage to word lines coupled to the selected memory cells; and using the first to (2) N -1) Verify voltage, perform verification operation on the selected memory cell.

[0046] In one embodiment, fine programming may include: applying a programming inhibit voltage to a bit line coupled to a fully programmed memory cell within a selected memory cell; applying a programming enable voltage to a bit line coupled to an unprogrammed memory cell within the selected memory cell; applying a first programming voltage to a word line coupled to the selected memory cell; and applying a programming inhibit voltage to a memory cell within the selected memory cell that is fully programmed to a corresponding target programming state and to the first to (2)th word lines. N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2) N -1) Bit lines in the target programming state memory cells coupled to memory cells that are not fully programmed; applying a second programming voltage greater than the first programming voltage to word lines coupled to the selected memory cells; and using the first to (2) N -1) Verify voltage, perform verification operation on the selected memory cell.

[0047] In one embodiment, the first fuzzy programming may include: applying a programming disable voltage to a bit line coupled to a memory cell to be programmed into a first intermediate programming state; applying a programming enable voltage to a bit line coupled to an incompletely programmed memory cell within the memory cell to be programmed into the first intermediate programming state; applying a programming voltage to a word line coupled to a selected memory cell; and performing a verification operation on the memory cell to be programmed into the first intermediate programming state using an intermediate verification voltage.

[0048] In one embodiment, the second fuzzy programming may include: applying a programming disable voltage to a memory cell within a selected memory cell that is fully programmed to the corresponding target programming state, and to the first to (2)th fuzzy programming. N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying programming voltage to word lines coupled to the selected memory cells; and using the (2)N-1 ) to (2 N -1) Verify the voltage, to be programmed to (2) N-1 ) to (2) N -1) The memory cell in the target programming state performs a verification operation.

[0049] In one embodiment, the second fuzzing may further include: after performing the verification operation, determining the relationship between the (2)th and (3)th fuzzing operations. N -1 ) to (2) N -1) Whether the threshold voltage of all memory cells corresponding to the target programming state is greater than the (2) N-1 Verify the voltage.

[0050] In one embodiment, the second fuzzy programming can respond to determining the (2) N-1 ) to (2) N -1) The threshold voltage of all memory cells corresponding to the target programming state is greater than the (2) N-1 The process ends after verifying the voltage.

[0051] In one embodiment, in response to determining the (2) N-1 ) to (2) N -1) At least one of the threshold voltages of the memory cell corresponding to the target programming state is less than the threshold voltage of the (2) N-1 ) Verify the voltage, and the second fuzzy programming can re-perform the following operations: apply a programming disable voltage to the memory cell in the selected memory cell that is fully programmed to the corresponding target programming state and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the memory cell corresponding to the target programming state; apply the programming enable voltage to the bit line corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to unprogrammed memory cells within the target programming state memory cells; applying programming voltage to word lines coupled to the selected memory cells; and using the (2) N-1 ) to (2 N -1) Verify the voltage, to be programmed to (2) N-1 ) to (2) N -1) The memory cell in the target programming state performs a verification operation.

[0052] In one embodiment, fine programming may include: applying a programming disable voltage to a bit line coupled to a memory cell in the selected memory cell that is fully programmed to the corresponding target programming state; applying a programming enable voltage to a bit line coupled to a memory cell in the selected memory cell that is not fully programmed to the corresponding target programming state; applying a programming voltage to a word line coupled to the selected memory cell; and using first to second (2) N -1) Verify voltage, perform verification operation on the selected memory cell.

[0053] In one embodiment, the intermediate verification voltage can be less than the (2)th verification voltage. N-1 Verify the voltage.

[0054] Figure 1 This is a block diagram illustrating a memory system 1000 including a semiconductor memory device 100 and a controller 200 according to an embodiment of the present disclosure.

[0055] refer to Figure 1 The memory system 1000 may include a semiconductor memory device 100 and a controller 200. Additionally, the memory system 1000 may communicate with a host 300. The controller 200 may control the general operation of the semiconductor memory device 100. Additionally, the controller 200 may control the operation of the semiconductor memory device 100 based on commands received from the host 300.

[0056] Figure 2 It's a diagram. Figure 1 Block diagram of semiconductor memory device 100 shown.

[0057] refer to Figure 2 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, read and write circuitry 130, control logic 140, and a voltage generator 150. The control logic 140 may be implemented in hardware, software, or a combination of both. For example, the control logic 140 may be a control logic circuitry that operates according to an algorithm and / or executes control logic code.

[0058] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz may be coupled to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz may be coupled to read and write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. According to one embodiment, the multiple memory cells may be non-volatile memory cells with a vertical channel structure. The memory cell array 110 may have a two-dimensional structure. According to one embodiment, the memory cell array 110 may have a three-dimensional structure. Each memory cell included in the multiple memory cells of the memory cell array 110 may store at least one bit of data (i.e., DATA). According to one embodiment, each memory cell included in the multiple memory cells of the memory cell array 110 may be a single-level cell (SLC) storing 1 bit of data. According to another embodiment, each memory cell included in the multiple memory cells of the memory cell array 110 may be a multi-level cell (MLC) storing 2 bits of data. According to another embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may be a three-level cell (TLC) that stores 3 bits of data. According to another embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may be a four-level cell (QLC) that stores 4 bits of data. According to one embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may store five or more bits of data.

[0059] Address decoder 120, read and write circuitry 130, and voltage generator 150 can operate as peripheral circuitry configured to drive memory cell array 110. Address decoder 120 can be coupled to memory cell array 110 via word line WL. Address decoder 120 can be controlled by control logic 140. Address decoder 120 can receive addresses via input / output buffers (not shown) in semiconductor memory device 100.

[0060] Address decoder 120 can be configured to decode the block address of a received address. Address decoder 120 can select at least one memory block based on the decoded block address. Additionally, during a read voltage application operation in a read operation, address decoder 120 can apply a read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block, and can apply a pass voltage Vpass to the unselected word line. Additionally, during a program verification operation, address decoder 120 can apply a verification voltage generated by voltage generator 150 to the selected word line of the selected memory block, and can apply a pass voltage Vpass to the unselected word line.

[0061] Address decoder 120 can be configured to decode the column address of a received address. Address decoder 120 can then transmit the decoded column address to read and write circuitry 130.

[0062] Read and programming operations of the semiconductor memory device 100 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line in response to the block and row addresses. The column address can be decoded by the address decoder 120 and provided to the read and write circuitry 130.

[0063] Address decoder 120 may include block decoder, row decoder, column decoder and address buffer.

[0064] The read and write circuitry 130 may include multiple page buffers PB1 to PBm. The read and write circuitry 130 may operate as a read circuit during a read operation of the memory cell array 110 and as a write circuit during a write operation. The page buffers PB1 to PBm may be coupled to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, the page buffers PB1 to PBm may continuously supply sensing current to the bit lines coupled to the memory cells to sense the threshold voltage of the memory cells and sense changes in current caused by the programming state of the corresponding memory cells via sensing nodes, thereby latching sensed data. The read and write circuitry 130 may operate in response to page buffer control signals output from control logic 140.

[0065] During a read operation, the read and write circuit 130 can sense data in the memory cell, temporarily store the read data, and output the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. According to one embodiment, in addition to a page buffer (or page register), the read and write circuit 130 may also include a column selector.

[0066] Control logic 140 can be coupled to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 can be configured to control the general operation of semiconductor memory device 100 in response to control signal CTRL. Additionally, control logic 140 can output control signals to control the sense node precharge potential levels of page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110.

[0067] During a read operation, voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass in response to a control signal output from control logic 140. Voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage to generate multiple voltages having various voltage levels, and can selectively activate the multiple pump capacitors in response to control by control logic 140 to generate multiple voltages. As described above, voltage generator 150 may include a charge pump, and the charge pump may include the aforementioned pump capacitors. The specific configuration of the charge pump included in voltage generator 150 can be designed in various ways.

[0068] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" configured to perform read, write, and erase operations on the memory cell array 110. Control logic 140 can control the peripheral circuitry to perform read, write, and erase operations on the memory cell array 110.

[0069] Figure 3 It's a diagram. Figure 2 A diagram illustrating an embodiment of the memory cell array 110 shown.

[0070] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block BLK1 to BLKz may include a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells may be arranged in the +X, +Y, and +Z directions. References will follow. Figure 4and Figure 5 To describe the structure of each memory block.

[0071] Figure 4 It's a diagram. Figure 3 The circuit diagram shown is for one of the memory blocks (BLKa) from BLK1 to BLKz.

[0072] refer to Figure 4 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. According to one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, "m" cell strings may be arranged in the row direction (i.e., the +X direction). Figure 4 The illustration shows two unit strings arranged in the column direction (i.e., the +Y direction). However, it can be understood that three or more unit strings can be arranged in the column direction.

[0073] Each of the cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0074] Each select transistor in the select transistors SST and DST, and each memory cell in the memory cells MC1 to MCn, may have a structure similar to each other. According to one embodiment, each of the select transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. According to one embodiment, a pillar for providing the channel layer may be provided in each cell string. According to one embodiment, a pillar for providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer.

[0075] The source selection transistor SST of each cell string can be coupled between the common source line CSL and the first to p memory cells MC1 to MCp.

[0076] According to one embodiment, source selection transistors of cell strings arranged in the same row can be coupled to source selection lines extending along the row direction, and source selection transistors of cell strings arranged in different rows can be coupled to different source selection lines. Figure 4 In the first row, the source selection transistors SST of cell strings CS11 to CS1m can be coupled to the first source selection line SSL1. In the second row, the source selection transistors SST of cell strings CS21 to CS2m can be coupled to the second source selection line SSL2.

[0077] According to another embodiment, the source selection transistors SST of cell strings CS11 to CS1m and CS21 to CS2m can be co-coupled to a single source selection line.

[0078] The first to nth memory cells MC1 to MCn of each cell string can be coupled between the source select transistor SST and the drain select transistor DST.

[0079] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp can be arranged sequentially in the direction opposite to the +Z direction and can be coupled in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn can be arranged sequentially in the +Z direction and can be coupled in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn can be coupled through the channel transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string can be coupled to the first to nth word lines WL1 to WLn, respectively.

[0080] The gate of the pipe transistor PT in each unit string can be coupled to the pipe line PL.

[0081] The drain select transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged along the row direction can be coupled to drain select lines extending along the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be coupled to the second drain select line DSL2.

[0082] A string of cells arranged along the column direction can be coupled to a bit line extending along the column direction. Figure 4 In the first column, the cell strings CS11 and CS21 can be coupled to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be coupled to the m-th bit line BLm.

[0083] In a row-oriented cell string, memory cells coupled to the same word line can form a single page. For example, memory cells in cell strings CS11 to CS1m in the first row, coupled to the first word line WL1, can form a single page. Memory cells in cell strings CS21 to CS2m in the second row, coupled to the first word line WL1, can form another page. A cell string arranged in one row direction can be selected when either drain select line DSL1 or DSL2 is selected. When one of the word lines WL1 to WLn from the first to the nth word line is selected, a page can be selected from the selected cell string.

[0084] According to another embodiment, even-numbered bit lines and odd-numbered bit lines can replace the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings in the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be coupled to even-numbered bit lines, and odd-numbered cell strings in the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be coupled to odd-numbered bit lines.

[0085] According to one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. In one embodiment, when more dummy memory cells are provided, the operational reliability of the memory block BLKa can be improved; however, the size of the memory block BLKa may increase. On the other hand, in one embodiment, when the number of dummy memory cells is reduced, the size of the memory block BLKa can be reduced, and the operational reliability of the memory block BLKa may decrease.

[0086] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on some or all of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after programming, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word lines coupled to the dummy memory cells.

[0087] Figure 5 It's a diagram. Figure 3 A circuit diagram of another embodiment of one of the memory blocks BLK1 to BLKz (BLKb) shown.

[0088] refer to Figure 5The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may extend in the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0089] The source select transistor SST of each cell string can be coupled between a common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row can be coupled to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row can be coupled to a first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row can be coupled to a second source select line SSL2. According to another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly coupled to a single source select line.

[0090] The first to nth memory cells MC1 to MCn of each cell string can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn can be coupled to the first to nth word lines WL1 to WLn, respectively.

[0091] The drain select transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction can be coupled to drain select lines extending along the row direction. The drain select transistors (DST) of cell strings CS11' to CS1m' in the first row can be coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row can be coupled to the second drain select line DSL2.

[0092] result, Figure 5 The memory block BLKb shown can have the same characteristics as... Figure 4 The equivalent circuit shown is similar to that of memory block BLKa, except that the pipe transistor PT is removed from each cell string of memory block BLKb.

[0093] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction can be coupled to even-numbered bit lines respectively, and odd-numbered cell strings in the cell strings CS11' to CS1m' or CS21' to CS2m' arranged along the row direction can be coupled to odd-numbered bit lines respectively.

[0094] According to one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the first to nth memory cells MC1 to MCn. Alternatively, one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. In one embodiment, when more dummy memory cells are provided, the operational reliability of the memory block BLKb can be improved; however, the size of the memory block BLKb may increase. On the other hand, in one embodiment, when the number of dummy memory cells is reduced, the size of the memory block BLKb can be reduced, and the operational reliability of the memory block BLKb may decrease.

[0095] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on some or all of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after programming, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word lines coupled to the dummy memory cells.

[0096] Figure 6 It is illustrated in Figure 2 A circuit diagram of an embodiment of a memory block (BLKc) included in the memory cell array 110 shown, comprising memory blocks BLK1 to BLKz.

[0097] refer to Figure 6 The memory block BLKc may include multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm may be coupled to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0098] Each of the select transistors SST and DST, and each of the memory cells MC1 to MCn, may have a structure similar to each other. According to one embodiment, each of the select transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. According to one embodiment, pillars for providing the channel layer may be provided in each cell string. According to one embodiment, pillars for providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer.

[0099] The source selection transistor SST of each cell string can be coupled between the common source line CSL and the first to nth memory cells MC1 to MCn.

[0100] The first to nth memory cells MC1 to MCn of each cell string can be coupled between the source select transistor SST and the drain select transistor DST.

[0101] The drain selection transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MC1 to MCn.

[0102] Memory cells coupled to the same word line can form a single page. When the drain select line DSL is selected, cell strings CS1 to CSm can be selected. When one of the word lines WL1 to WLn is selected, a page can be selected from the selected cell string.

[0103] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. The even-numbered unit strings in the unit strings CS1 to CSm can be coupled to the even-numbered bit lines respectively, and their odd-numbered unit strings can be coupled to the odd-numbered bit lines respectively.

[0104] Figure 7 This is a flowchart illustrating a method of operating a semiconductor memory device 100 according to an embodiment of the present disclosure. For ease of discussion, see reference... Figures 7 to 23 The method of operating a semiconductor memory device according to this disclosure is described based on three-level cell (TLC) programming operations. However, the above description is for illustrative purposes only. The method of operating a semiconductor memory device according to this disclosure can be applied to multi-level cell (MLC) or four-level cell (QLC). In other words, this disclosure can be applied to semiconductor memory devices that store N bits of data in each memory cell.

[0105] According to one embodiment, a fuzzy-fine programming scheme can be used to mitigate interference affecting adjacent cells due to programming operations in a three-dimensional memory cell array. The fuzzy-fine programming scheme can refer to a scheme that includes first programming the selected memory cell to an intermediate programming state P. IS The programming method consists of fuzzy programming steps and fine programming steps that then program the selected memory cells to the target programming states PV1 to PV7.

[0106] refer to Figure 7 A method of operating a semiconductor memory device according to an embodiment of the present disclosure may include, at step S100, using an intermediate verification voltage VRF IS The selected memory cell is fuzzy programmed; and at step S200, the selected memory cell is fine programmed using first to seventh verification voltages. In this disclosure, the term "selected memory cell" may refer to a memory cell belonging to a physical page being programmed. The selected memory cell may be coupled to a selected word line.

[0107] At step S100, the threshold voltage distribution of the selected memory cell can be changed from erase state E0 to erase state E IS and intermediate programming state P IS Fuzzy programming can refer to the process of temporarily changing the threshold voltage distribution of a memory cell to the erase state E before changing the threshold voltage distribution of the memory cell to the erase state E and the target programming states PV1 to PV7. IS and intermediate programming state P IS Programming operations. Intermediate verification voltage VRF. IS This can be used to change the threshold voltage distribution of at least some memory cells corresponding to the erase state E0 to an intermediate verification voltage VRF. IS The verification voltage. The following will refer to... Figure 8 and Figure 10 Let's describe step S100.

[0108] At step S200, the threshold voltage distribution of the selected memory cell can be determined from the erase state E. IS and intermediate programming state P IS The process changes to erase state E and target programming states PV1 to PV7. Since the selected memory cell is a TLC, after the programming operation terminates, the threshold voltage distribution of the memory cell can belong to one of eight states (i.e., erase state E and target programming states PV1 to PV7). When each memory cell stores N bits, after the programming operation terminates, the threshold voltage distribution of the memory cell can belong to 2... NThe states (i.e., erase state E and target programming states PV1 to PV2) are: N -1)) is a state.

[0109] For example, at step S200, it is in the erase state E. IS The threshold voltage distribution of the memory cell can be changed to erase state E and first to third target programming states PV1 to PV3. When each memory cell stores N bits, the threshold voltage distribution is different from that in erase state E. IS The threshold voltage distribution of the corresponding memory cell can be changed to erase state E and the first to (2)th ... N-1 -1) Target programming state PV1 to PV(2) N-1 -1).

[0110] Additionally, at step S200, it belongs to the intermediate programming state P. IS The threshold voltage distribution of the memory cells can be changed to the fourth to seventh target programming states PV4 to PV7. When each memory cell stores N bits, it belongs to the intermediate programming state P. IS The threshold voltage distribution of the memory cell can be changed to the (2) N-1 ) to (2) N -1) Target programming state.

[0111] The first through seventh verification voltages can be used to compare with the erased state E IS and intermediate programming state P IS The corresponding threshold voltage distribution of the memory cell changes to erase state E and target programming states PV1 to PV7. For example, when each memory cell stores N bits, the first to (2)th threshold voltage distributions can be used. N-1 Verify the voltage. The following will refer to... Figure 9 and Figure 10 Let's describe step S200.

[0112] Figure 8 It's a diagram. Figure 7 The flowchart shows an embodiment of step S100. Figure 9 It's a diagram. Figure 7 The flowchart shows an embodiment of step S200. Figure 10 The diagram illustrates when based on Figures 7 to 9 The diagram shows the threshold voltage distribution of the selected memory cell when the method shown performs programming operations.

[0113] In the following text, see references Figure 8 and Figure 10 To describe Figure 7 Step S100.

[0114] refer to Figure 8Step S100 may include: applying a programming disable voltage to the state P that is programmed into an intermediate programming state. IS The memory cell and the E that maintains the erase state IS The bit line coupled to the memory cell (S310); the programming enable voltage is applied to the bit line to be programmed into the intermediate programming state P. IS The bit line coupled to the selected memory cell is (S330); a programming voltage is applied to the word line coupled to the selected memory cell is (S350); an intermediate verification voltage VRF is used. IS Perform a verification operation (S370) on the selected memory cell; and determine whether the selected memory cell has been fully programmed to the intermediate programming state P. IS (S390).

[0115] According to one embodiment, the erase state E is maintained in the selected memory cell. IS The least significant bit (LSB) of each memory cell in the memory unit can be 1. In the selected memory cell, the program to be programmed to the intermediate programming state P... IS The least significant bit (LSB) of a memory cell can be 0. For example... Figure 10 As shown, maintain the erase state E. IS The least significant bit (LSB) of the memory cell can be 1, and it is to be programmed into the intermediate programming state P. IS The least significant bit (LSB) of the memory cell is 0. In other words, the fuzzy programming operation at step S100 can be essentially the same as the single-level cell (SLC) programming operation.

[0116] like Figure 8 As shown, steps S310, S330, S350, and S370 can be repeated until the selected memory cell is programmed to an intermediate programming state. In other words, the fuzzy programming operation of the selected memory cell can include multiple programming loops. Each programming loop can include steps S310, S330, S350, and S370.

[0117] At step S310, as a result of the verification operation performed at step S370 in the previous programming cycle, a programming disable voltage can be applied to the intermediate programming state P to be programmed. IS The memory cell and the E that maintains the erase state IS The bit lines are coupled to the fully programmed memory cells within the memory cells. In the intermediate programming state P, the memory cells are to be programmed... IS The memory cell and the E that maintains the erase state IS Within a memory cell, the threshold voltage of a programmed memory cell should not be increased further. Therefore, a programming disable voltage can be applied to the memory cell to be programmed into the intermediate programming state P.IS The memory cell and the E that maintains the erase state IS The bit lines of the memory cells in which the programming is completed are coupled so that the threshold voltage of the corresponding memory cell is not increased even when a programming voltage is applied to the selected word line (S350).

[0118] At step S330, a programming enable voltage can be applied to the state P to be programmed into the intermediate programming state. IS The bit line is a memory cell that was not fully programmed as a result of the verification operation performed at step S370 in a previous programming cycle. In this way, when a programming voltage is applied to the selected word line (S350), the threshold voltage of the corresponding memory cell can be increased.

[0119] Figure 8 The illustration shows that step S330 is executed after step S310. However, this disclosure is not limited thereto. Steps S310 and S330 may relate to the bit line voltage settings of the programming unit and the programming disable unit. Therefore, step S310 may be executed after step S330, or steps S310 and S330 may be executed simultaneously.

[0120] Subsequently, at step S350, a programming voltage can be applied to the word line coupled to the selected memory cell. Therefore, the threshold voltage of the programming cell within the selected memory cell can be increased, while the threshold voltage of the programming inhibit cell can remain unchanged. More specifically, the selected memory cell may include the cell to be programmed into an intermediate programming state P. IS The memory cell and the E that maintains the erase state IS The memory cell. In the intermediate programming state P, it is to be programmed. IS Within the memory cells, there is a voltage greater than the intermediate verification voltage VRF. IS Memory cells with a threshold voltage can be "programmable disable cells". They have a voltage less than the intermediate verification voltage VRF. IS The memory cell with the threshold voltage can be a "programming cell". In the early stages of the programming operation, all memory cells can have a threshold voltage corresponding to the erase state E0. Therefore, the cell to be programmed to the intermediate programming state P... IS All memory cells can be programmable cells. As the programming cycle repeats, the threshold voltage of the programmable cells can be gradually increased, and the threshold voltage of some memory cells can exceed the intermediate verification voltage VRF. IS On the other hand, it has a voltage greater than the intermediate verification voltage VRF. IS The memory cell with a threshold voltage can be a programmable disable cell. As the programming loop continues to repeat, the cell to be programmed to the intermediate programming state P... ISThe threshold voltage of the memory cell can eventually be greater than the intermediate verification voltage VRF. IS As a result, the program needs to be programmed into the intermediate programming state P. IS All memory cells can be programmable disabled cells.

[0121] Keep erase state E IS The memory cells can be programmed-disabled cells from the early stages of programming operations.

[0122] At step S370, the intermediate verification voltage VRF can be used. IS The memory cells to be programmed to the intermediate programming state are then subjected to a verification operation. More specifically, this is achieved by applying the intermediate verification voltage VRF at step S370. IS By applying voltage to the selected word line, it can be determined whether the threshold voltage of the memory cell to be programmed into the intermediate programming state is greater than the intermediate verification voltage VRF. IS In the memory cells that serve as programming units based on the verification results of previous verification operations, the voltage has a higher value than the intermediate verification voltage VRF, resulting from the application of a programming voltage at step S350 in the current programming cycle. IS The memory cell with the threshold voltage can be changed to a programmable disabled cell.

[0123] At step S390, it can be determined whether the memory cell to be programmed to the intermediate programming state has already been programmed to the intermediate programming state. More specifically, when the memory cell to be programmed to the intermediate programming state P... IS The threshold voltage of all memory cells is greater than the intermediate verification voltage VRF. IS When (S390: Yes), step S100 can end. When the program to be programmed reaches the intermediate programming state P... IS At least some of the memory cells in the memory cell have a threshold voltage less than the intermediate verification voltage VRF. IS If (S390: No), the process can proceed to step S310 and the subsequent programming loop can be repeated.

[0124] Because fuzzy programming operations are based on Figure 8 To execute the steps, such as... Figure 10 As shown, the threshold voltage distribution corresponding to the initial erase state E0 can be changed to the erase state E IS and intermediate programming state P IS Keep erased in E state IS The memory cell and the programmable state P are in the intermediate programming state. ISThe memory cells can be distinguished from each other based on the LSB of each memory cell. In other words, the fuzzy programming operation can be essentially the same as the SLC programming operation based on the LSB of each memory cell. When the fuzzy programming operation is completed, the threshold voltage distribution of the memory cells can be divided into erase states E. IS and intermediate programming state P IS Therefore, the LSB of each memory cell can use the intermediate read voltage R. IS To read.

[0125] In the following text, Figure 7 Step S200 reference Figure 9 and Figure 10 To describe.

[0126] refer to Figure 9 Step S200 may include: applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state PV1 to PV7 (S315); applying a programming enable voltage to a bit line coupled to a memory cell not programmed to a target programming state PV1 to PV7 (S335); applying a programming voltage to a word line coupled to a selected memory cell (S355); performing a verification operation on the selected memory cell using the first to seventh verification voltages VRF1 to VRF7 (S375); and determining whether the selected memory cell has been programmed to a target programming state PV1 to PV7 (S395).

[0127] like Figure 10 As shown, steps S315, S335, S355, and S375 can be repeated until the selected memory cell is programmed to the target programming state. In other words, the fine-grained programming operation of the selected memory cell can include multiple programming loops. Each program loop can include steps S315, S335, S355, and S375.

[0128] At step S315, as a result of the verification operation performed at step S375 in the previous programming cycle, a programming inhibit voltage may be applied to the bit line coupled to the fully programmed memory cell among the memory cells to be programmed to the target programming states PV1 to PV7. Additionally, the programming inhibit voltage may be applied to the bit line coupled to the memory cell holding the erase state E.

[0129] At step S335, as a result of the verification operation performed at step S375 in the previous programming cycle, a programming enable voltage can be applied to each bit line of the unprogrammed memory cell coupled to the memory cells to be programmed to the target programming states PV1 to PV7. In this way, when the programming voltage is applied to the selected word line at step S355, the threshold voltage of the corresponding memory cell can be increased.

[0130] Figure 9 The illustration shows that step S335 is executed after step S315. However, this disclosure is not limited thereto. Steps S315 and S335 may relate to the bit line voltage settings of the programming unit and the programming disable unit. Therefore, step S315 may be executed after step S330, or steps S315 and S335 may be executed simultaneously.

[0131] Subsequently, at step S355, a programming voltage can be applied to the word line coupled to the selected memory cell. Therefore, the threshold voltage of the programming cell within the selected memory cell can be increased, while the threshold voltage of the programming disable cell can remain unchanged.

[0132] At step S375, the first to seventh verification voltages VRF1 to VRF7 can be used to perform a verification operation on the selected memory cell. More specifically, by applying the first to seventh verification voltages VRF1 to VRF7 to the selected word line at step S375, it can be determined whether the threshold voltage of the selected memory cell is greater than its corresponding first to seventh verification voltages VRF1 to VRF7.

[0133] For example, when the threshold voltage of a memory cell to be programmed into the third target programming state PV3 is greater than the third verification voltage VRF3, the corresponding memory cell can be a programming disable cell. In another example, when the threshold voltage of a memory cell to be programmed into the fifth target programming state PV5 is less than the fifth verification voltage VRF5, the corresponding memory cell can be a programming cell.

[0134] At step S395, it can be determined whether the selected memory cells have been fully programmed to their respective target programming states. Step S200 can end when the threshold voltage of all selected memory cells is greater than the corresponding verification voltage (S395: Yes). When the threshold voltage of at least some selected memory cells is less than the corresponding verification voltage (S395: No), the process can proceed to step S315, and the subsequent programming cycle can be repeated.

[0135] Because fine programming operations are based on Figure 9 The steps are executed to erase state E. IS and intermediate programming state PIS The threshold voltage distribution can be changed to erase state E and the first to seventh target programming states PV1 to PV7. More specifically, with erase state E IS The threshold voltage distribution of the corresponding memory cell can be changed to erase state E and first to third target programming states PV1 to PV3, and intermediate programming state P IS The threshold voltage distribution can be changed to the fourth to seventh target programming states PV4 to PV7.

[0136] The memory cells corresponding to the erase state E and the first to seventh target programming states PV1 to PV7 can be partitioned based on the MSB, CSB, and LSB of each memory cell. Figure 10 In the example, the MSB of the memory cell corresponding to the erase state E can be 0, the CSB can be 1, and the LSB can be 1. Additionally, in Figure 10 In the example, the MSB of the memory cell corresponding to the first target programming state PV1 can be 0, the CSB can be 0, and the LSB can be 1.

[0137] After the fine programming operation is completed, the LSB of each selected memory cell can be read using the fourth read voltage R4. For example... Figure 10 As shown, based on the fourth read voltage R4, the LSB of all memory cells on the left can be 1, and the LSB of all memory cells on the right can be 0. Therefore, an LSB read operation can be performed on the memory cells using the fourth read voltage R4. Figure 10 As shown, when the fuzzy programming operation is completed, the read voltage used for the LSB read operation can be the intermediate read voltage R. IS Furthermore, when the fine programming operation is completed, the read voltage used for the LSB read operation can be greater than the intermediate read voltage R. IS The fourth read voltage R4.

[0138] Figure 11 The diagram illustrates when based on Figures 7 to 9 The diagram illustrates the threshold voltage distribution of the selected memory cell during a sudden power outage (SPO) when the programming operation is performed using the method shown. For ease of discussion, the description of the process of performing fuzzy programming in the initial erase state E0 is omitted.

[0139] refer to Figure 11 After the fuzzy programming operation is completed and the threshold voltage distribution of the memory cell is changed to the erase state E IS and intermediate programming state P IS Subsequently, a sudden power outage (SPO) may occur during fine programming operations. In other words, if in the erase state E ISWhen the threshold voltage distribution of the corresponding memory cell is changed to erase state E and the first to third target programming states PV1 to PV3 through fine programming operations, an SPO occurs. This is related to the erase state E. IS The threshold voltage distribution of the corresponding memory cell may be changed to erase state E'. Additionally, if in the intermediate programming state P... IS When the threshold voltage distribution of the corresponding memory cell is changed to the fourth to seventh target programming states PV4 to PV7 through fine programming operations, an SPO occurs, which is then related to the intermediate programming state P. IS The threshold voltage distribution of the corresponding memory cell may be changed to an intermediate programming state P'.

[0140] like Figure 11 As shown, when memory device 100 performs an LSB read operation to resume programming after an SPO occurs, a read failure may occur. In other words, when using the intermediate read voltage R... IS When performing an LSB read operation, the memory cell corresponding to the intermediate programming state P' can be correctly read as "0 (zero)". However, some bits in the memory cell corresponding to the erase state E' may be incorrectly read as 0. More specifically, in the memory cell corresponding to the erase state E', the bit position is lower than the intermediate read voltage R. IS The LSB of each memory cell in a memory cell with a threshold voltage can be correctly read as "1 (-)". However, in the memory cell corresponding to the erase state E', the LSB has a voltage greater than the intermediate read voltage R. IS The LSB of each memory cell in a memory cell with a threshold voltage may be incorrectly read as 0.

[0141] When an LSB read operation is performed using the fourth read voltage R4, the bits of each memory cell in the memory cell corresponding to the erase state E' can be correctly read as "1 (one)". However, some bits in each memory cell in the memory cell corresponding to the intermediate programming state P' may be incorrectly read as 1. More specifically, in the memory cells corresponding to the intermediate programming state P', the LSB of each memory cell having a threshold voltage greater than the fourth read voltage R4 can be correctly read as "0 (zero)". However, in the memory cells corresponding to the intermediate programming state P', the LSB of each memory cell having a threshold voltage less than the fourth read voltage R4 may be incorrectly read as 1.

[0142] Additionally, when using the intermediate reading voltage R ISWhen multiple sampling read voltages exist between the fourth read voltage R4 and the fourth read voltage R4 to perform an LSB read operation, there may be overlap between the threshold voltage distribution of the memory cell corresponding to the erase state E' and the threshold voltage distribution corresponding to the intermediate programming state P'. In other words, even when using multiple read voltages to perform an LSB read operation, error correction of the read data may occur due to the overlap between the threshold voltage distribution of the memory cell corresponding to the erase state E' and the threshold voltage distribution corresponding to the intermediate programming state P'. Figure 11 The error occurred because the memory cell corresponding to the shaded area "A" in the image was not identified.

[0143] An example of an SPO occurring during fine programming is described. However, the same phenomenon can occur during fine programming when the programming operation is paused in response to a programming pause command from the controller.

[0144] The method for operating a semiconductor memory device according to embodiments of the present disclosure, associated with a programming operation using a fuzzy-fine programming method, involves dividing selected memory cells into multiple groups based on a corresponding target programming state and applying a programming voltage to the memory cells included in each group, which can be performed individually. Therefore, even when the programming operation is paused by an SPO or programming pause command, LSB data can still be read normally from the memory cells. Thus, the data reliability of the semiconductor memory device can be improved.

[0145] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure. According to another embodiment, a fuzzy-fine programming scheme can be used to improve interference affecting adjacent cells caused by programming operations in a three-dimensional memory cell array.

[0146] refer to Figure 12 A method of operating a semiconductor memory device according to an embodiment of the present disclosure may include: using an intermediate verification voltage VRF IS Perform fuzzy programming on the selected memory cell (S100); perform fine programming on the memory cell to be programmed to a higher target programming state (PV4 to PV7) using the verification voltages (VRF4 to VRF7) in the first group (S210); and perform fine programming on the memory cell to be programmed to a lower target programming state (PV1 to PV3) using the verification voltages (VRF1 to VRF3) in the second group (S230).

[0147] At step S100, the threshold voltage distribution of the selected memory cell can be changed from erase state E0 to erase state E IS and intermediate programming state P IS .because Figure 12 Step S100 and Figure 7 Step S100 is basically the same, so its description will be omitted.

[0148] Additionally, at step S210, the intermediate programming state P IS The threshold voltage distribution of the corresponding memory cells can be changed to higher target programming states PV4 to PV7. Verification voltages VRF4 to VRF7 from the first group can be used. Verification voltages VRF4 to VRF7 from the first group can each correspond to higher target programming states PV4 to PV7. At step S210, a fine-grained programming operation can be performed on the memory cells corresponding to the higher target programming states PV4 to PV7 among all target programming states PV1 to PV7. Therefore, step S210 can be referred to as the first fine-grained programming operation. The following will refer to... Figure 13 and Figure 15 Let's describe step S210.

[0149] At step S230, the erase state E IS The threshold voltage distribution of the corresponding memory cells can be changed to erase state E and lower target programming states PV1 to PV3. Verification voltages VRF1 to VRF3 from the second group can be used. Verification voltages VRF1 to VRF3 from the second group can each correspond to a lower target programming state PV1 to PV3. At step S230, a fine programming operation can be performed on the memory cells corresponding to the lower target programming states PV1 to PV3 among all target programming states PV1 to PV7. Therefore, step S230 can be referred to as the second fine programming operation. The following will refer to... Figure 14 and Figure 15 Let's describe step S230.

[0150] Figure 13 It's a diagram. Figure 12 The flowchart of an embodiment of step S210 is shown. Figure 14 It's a diagram. Figure 12 The flowchart shows an embodiment of step S230. Figure 15 The diagram illustrates when based on Figures 12 to 14 The diagram shows the threshold voltage distribution of the selected memory cell when the programming operation is performed using the method shown.

[0151] In the following text, see references Figure 13 and Figure 15 To describe Figure 12 Step S210.

[0152] refer to Figure 13Step 210 may include: applying a programming disable voltage to bit lines coupled to memory cells programmed to target programming states PV1 to PV7 and memory cells to be programmed to lower programming states PV1 to PV3 (S410); applying a programming enable voltage to bit lines coupled to memory cells in memory cells to be programmed to higher target programming states PV4 to PV7 that are not programmed to the corresponding target programming voltage (S430); applying a programming voltage to word lines coupled to selected memory cells (S450); performing a verification operation on memory cells to be programmed to higher target programming states PV4 to PV7 using fourth to seventh verification voltages VRF4 to VRF7 (S470); and determining whether programming of memory cells to be programmed to higher target programming states PV4 to PV7 is complete (S490).

[0153] like Figure 15 As shown, in the first fine-tuning operation, steps S410, S430, S450, and S470 can be repeated until the memory cells to be programmed to higher target programming states PV4 to PV7 are fully programmed. In other words, the first fine-tuning operation of the selected memory cells can include multiple programming cycles. Each programming cycle can include steps S410, S430, S450, and S470.

[0154] At step S410, as a result of the verification operation performed at step S470 in the previous programming cycle, a programming inhibit voltage can be applied to each bit line coupled to the memory cells fully programmed to the target programming state and the memory cells to be programmed to lower target programming states PV1 to PV3. Additionally, a programming inhibit voltage can be applied to each bit line coupled to the memory cells to be kept in erase state E. In the first fine programming operation, programming operations may not be performed on the memory cells to be programmed to lower target programming states PV1 to PV3. Therefore, all memory cells to be programmed to lower target programming states PV1 to PV3 can be programming inhibited cells. Therefore, a programming inhibit voltage can be applied to the bit lines coupled to the memory cells corresponding to erase state E and the lower first three target programming states PV1 to PV3, and a programming inhibit voltage can be applied to the bit lines coupled to the memory cells corresponding to higher target programming states PV4 to PV7 that have been verified during the verification in the previous programming cycle.

[0155] At step S430, as a result of the verification operation performed at step S470 in the previous programming cycle, a programming allow voltage can be applied to each bit line of the unprogrammed memory cell coupled to the memory cell to be programmed to the higher target programming states PV4 to PV7.

[0156] Figure 13 Step S430 is shown to be executed after step S410. However, this disclosure is not limited thereto. Steps S410 and S430 may relate to the bit line voltage settings of the programming unit and the programming disable unit. Therefore, step S410 may be executed after step S430, or steps S410 and S430 may be executed simultaneously.

[0157] Subsequently, at step S450, a programming voltage can be applied to the word line coupled to the selected memory cell. Therefore, the threshold voltage of the programming cell within the selected memory cell can be increased, while the threshold voltage of the programming disable cell can remain unchanged.

[0158] At step S470, a verification operation can be performed on the selected memory cells that are to be programmed to a higher target programming state PV4 to PV7 by using the fourth to seventh verification voltages VRF4 to VRF7.

[0159] At step S490, it can be determined whether all memory cells in the selected memory cells corresponding to the higher target programming states PV4 to PV7 have been fully programmed. Step S210 can end when the threshold voltage of all memory cells corresponding to the higher target programming states PV4 to PV7 is greater than the verification voltages VRF4, VRF5, VRF6, and VRF7 (S490: Yes). On the other hand, when the threshold voltage of some memory cells in the memory cells corresponding to the higher target programming states PV4 to PV7 is less than the corresponding verification voltage (S490: No), the process can proceed to step S410, and the subsequent programming cycle can be repeated.

[0160] Because the first fine programming operation is based on Figure 13 To execute the steps, such as... Figure 15 As shown, intermediate programming state P IS The threshold voltage distribution can be changed to the fourth to seventh target programming states PV4 to PV7. During the first fine programming operation, it is consistent with the erase state E. IS The threshold voltage of the corresponding memory cell can be maintained.

[0161] Therefore, even if an SPO occurs during the first fine programming operation, the LSB of the selected memory cell can still be accessed by using the intermediate read voltage R. IS Perform an LSB read operation to read the data.

[0162] In the following text, see references Figure 14 and Figure 15 To describe Figure 12 Step S230.

[0163] refer to Figure 14 Step 230 may include: applying a programming disable voltage to bit lines coupled to memory cells programmed to target programming states PV1 to PV7 and memory cells to be programmed to higher programming states PV4 to PV7 (S415); applying a programming enable voltage to bit lines coupled to memory cells among memory cells to be programmed to lower target programming states PV1 to PV3 that are not programmed to the corresponding target programming state (S435); applying a programming voltage to word lines coupled to selected memory cells (S455); performing a verification operation on memory cells to be programmed to lower target programming states PV1 to PV3 using first to third verification voltages VRF1 to VRF3 (S475); and determining whether the programming of memory cells to be programmed to lower target programming states PV1 to PV3 is complete (S495).

[0164] like Figure 15 As shown, in the second fine-tuning operation, steps S415, S435, S455, and S475 can be repeated until the memory cells to be programmed to lower target programming states PV1 to PV3 are fully programmed. In other words, the second fine-tuning operation of the selected memory cells can include multiple programming loops. Each program loop can include steps S415, S435, S455, and S475.

[0165] At step S415, as a result of the verification operation performed at step S475 in the previous programming cycle, a programming inhibit voltage can be applied to each bit line coupled to the memory cell fully programmed to the target programming state and the memory cells to be programmed to higher target programming states PV4 to PV7. As a result of the first fine programming operation performed previously at step S210, the memory cells corresponding to the higher target programming states PV4 to PV7 can be fully programmed. Additionally, at step S415, a programming inhibit voltage can be applied to each bit line coupled to the memory cell to be kept in erase state E. Thus, a programming inhibit voltage can be applied to the bit lines coupled to the memory cells corresponding to erase state E and the higher target programming states PV4 to PV7, and a programming inhibit voltage can be applied to the bit lines coupled to the memory cells corresponding to the lower target programming states PV1 to PV3 that have been verified during the verification in the previous programming cycle.

[0166] At step S435, as a result of the verification operation performed at step S475 in the previous programming cycle, the programming allow voltage can be applied to each bit line of the unprogrammed memory cell coupled to the memory cell to be programmed to the lower target programming states PV1 to PV3.

[0167] Figure 14 Step S435 is shown to be executed after step S415. However, this disclosure is not limited thereto. Steps S415 and S435 may relate to the bit line voltage settings of the programming unit and the disable programming unit. Therefore, step S415 may be executed after step S435, or steps S415 and S435 may be executed simultaneously.

[0168] Subsequently, at step S455, a programming voltage can be applied to the word line coupled to the selected memory cell. Therefore, the threshold voltage of the programming cell within the selected memory cell can be increased, while the threshold voltage of the programming disable cell can remain unchanged.

[0169] At step S475, a verification operation can be performed on the selected memory cells that are to be programmed to a lower target programming state PV1 to PV3 by using the first to third verification voltages VRF1 to VRF3.

[0170] At step S495, it can be determined whether the programming of the memory cells corresponding to the lower target programming states PV1 to PV3 in the selected memory cells is complete. When the threshold voltage of all memory cells corresponding to the lower target programming states PV1, PV2, and PV3 is greater than the verification voltages VRF1, VRF2, and VRF3 (S495: Yes), step S230 can end. On the other hand, when the threshold voltage of some memory cells in the memory cells corresponding to the lower target programming states PV1 to PV3 is less than the corresponding verification voltage (S495: No), the process can proceed to step S415, and the subsequent programming cycle can be repeated.

[0171] Because the second fine programming operation is based on Figure 14 The steps to be performed, such as Figure 15 As shown, compared to the erase state E IS The corresponding threshold voltage distribution can be changed to erase state E and first to third target programming states PV1 to PV3. During the second fine programming operation, the threshold voltage of the memory cells programmed to the fourth to seventh target programming states PV4 to PV7 can be maintained.

[0172] Therefore, even if an SPO occurs during the second fine programming operation, the LSB of the selected memory cell can be read by performing an LSB read operation using the fourth read voltage R4.

[0173] Based on the above references Figures 12 to 15In the described embodiment, after performing a fuzzy programming operation on the selected memory cell, when an SPO occurs during a first fine programming operation or a second fine programming operation, the LSB of the selected memory cell can use the intermediate read voltage R. IS Or the fourth reading voltage R4 is read normally.

[0174] Figure 16 This is a flowchart illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure.

[0175] refer to Figure 16 A method of operating a semiconductor memory device according to an embodiment of the present disclosure may include: using an intermediate verification voltage VRF IS A first fuzzy programming operation is performed on the selected memory cell (S110); a second fuzzy programming operation is performed on the memory cells to be programmed to higher target programming states PV4 to PV7 using a fourth verification voltage VRF4 (S220); and a fine programming operation is performed on the selected memory cell using the first to seventh verification voltages VRF1 to VRF7 (S240).

[0176] At step S110, the threshold voltage distribution of the selected memory cell can be changed from erase state E0 to erase state E IS and the first intermediate programming state P IS .because Figure 16 Step S110 and Figure 7 or Figure 12 Step S100 is basically the same, so its description will be omitted.

[0177] At step S220, with the first intermediate programming state P IS The threshold voltage distribution of the corresponding memory cell can be changed to the second intermediate programming state P. IS '. In the first intermediate programming state P IS The threshold voltage of the memory cell can be greater than the intermediate verification voltage VRF. IS And it is in the second intermediate programming state P IS The threshold voltage of the memory cell can be greater than the fourth verification voltage VRF4. Even when E is in the erase state during step S220. IS The threshold voltage distribution of the memory cell can also maintain the erase state. IS '.

[0178] According to one embodiment, in step S220, only the fourth verification voltage VRF4 can be used. Verification operations using the fourth verification voltage can be performed simultaneously on memory cells to be programmed to the fourth to seventh target programming states. In other words, verification operations using the fourth verification voltage can be performed on memory cells to be programmed to the fifth to seventh target programming states and memory cells to be programmed to the fourth target programming state.

[0179] According to another embodiment, verification voltages VRF4 to VRF7 from the first group, including a fourth verification voltage VRF4, can be used in step S220. A verification voltage corresponding to each memory cell in the memory cells to be programmed to the fourth to seventh target programming states can be applied. In other words, a verification operation using the fourth verification voltage VRF4 can be performed on the memory cells to be programmed to the fourth target programming state PV4, a verification operation using the fifth verification voltage VRF5 can be performed on the memory cells to be programmed to the fifth target programming state PV5, a verification operation using the sixth verification voltage VRF6 can be performed on the memory cells to be programmed to the sixth target programming state PV6, and a verification operation using the seventh verification voltage VRF7 can be performed on the memory cells to be programmed to the seventh target programming state PV7. Reference will be made below. Figure 17 and Figure 19 Let's describe step S220.

[0180] In step S240, the device is in the erase state E. IS The threshold voltage distribution of the memory cell can be changed to erase state E and lower target programming states PV1 to PV3, and is in a second intermediate programming state P. IS The threshold voltage distribution of the memory cell can be changed to the fourth to seventh target programming states PV4 to PV7. The first to seventh verification voltages VRF1 to VRF7 can be used. The verification voltages in the second group can correspond to the lower target programming states PV1 to PV3. At step S240, a fine-tuning operation can be performed on the selected memory cell. The following will refer to... Figure 18 and Figure 19 Let's describe step S240.

[0181] Figure 17 It's a diagram. Figure 16 The flowchart shows an embodiment of step S220. Figure 18 It's a diagram. Figure 16 The flowchart shows an embodiment of step S240. Figure 19 The diagram illustrates when programming operations are performed according to... Figures 16 to 18 The diagram shows the threshold voltage distribution of the selected memory cells when the method is executed.

[0182] In the following text, see references Figure 17 and Figure 19 To describe Figure 16 Step S220.

[0183] refer to Figure 17 Step 220 may include: applying a programming disable voltage to bit lines coupled to memory cells programmed to target programming states PV1 to PV7 and memory cells to be programmed to lower programming states PV1 to PV3 (S510); applying a programming enable voltage to bit lines coupled to memory cells not programmed to the corresponding target programming states among the memory cells to be programmed to higher target programming states PV4 to PV7 (S530); applying a programming voltage to word lines coupled to selected memory cells (S550); performing a verification operation on the memory cells to be programmed to higher target programming states PV4 to PV7 using fourth to seventh verification voltages VRF4 to VRF7 (S570); and determining whether the threshold voltage of all memory cells to be programmed to higher target programming states PV4 to PV7 is greater than the fourth verification voltage VRF4 (S590).

[0184] At step S510, as a result of the verification operation performed at step S570 in the previous programming cycle, a programming inhibit voltage can be applied to each bit line coupled to the memory cell fully programmed to the target programming state and the memory cell to be programmed to the lower target programming states PV1 to PV3. Additionally, at step S510, a programming inhibit voltage can be applied to each bit line coupled to the memory cell to be kept in the erase state E. Therefore, a programming inhibit voltage can be applied to the bit lines coupled to the memory cells corresponding to erase state E and the lower first three target programming states PV1 to PV3, and a programming inhibit voltage can be applied to the bit lines coupled to the memory cells corresponding to the higher target programming states PV4 to PV7 that have been verified during the verification in the previous programming cycle.

[0185] At step S530, as a result of the verification operation performed at step S570 in the previous programming cycle, the programming allow voltage can be applied to each bit line of the unprogrammed memory cell coupled to the memory cell to be programmed to the higher target programming state PV4 to PV7.

[0186] Subsequently, at step S550, a programming voltage can be applied to the word line coupled to the selected memory cell. Therefore, the threshold voltage of the programming cell within the selected memory cell can be increased, while the threshold voltage of the programming disable cell can remain unchanged.

[0187] At step S570, a verification operation can be performed on the selected memory cells that are to be programmed to a higher target programming state PV4 to PV7 by using the fourth to seventh verification voltages VRF4 to VRF7.

[0188] At step S590, it can be determined whether the threshold voltage of the memory cells corresponding to the higher target programming states PV4 to PV7 among the selected memory cells is greater than the fourth verification voltage. Step S220 can end when the threshold voltage of all memory cells corresponding to the higher target programming states PV4 to PV7 is greater than the fourth verification voltage VRF4 (S590: Yes). In other words, although the verification of the memory cells to be programmed to the fifth to seventh target programming states fails, step S220 can end when the threshold voltage of the memory cells corresponding to the higher target programming states PV4 to PV7 is greater than the fourth verification voltage VRF4. According to one embodiment, when the memory cells to be programmed to the fourth target programming state are fully programmed, the threshold voltage of the memory cells to be programmed to the higher target programming state is greater than the fourth verification voltage.

[0189] On the other hand, when the threshold voltage of some memory cells in the memory cells corresponding to the higher target programming states PV4 to PV7 is less than the fourth verification voltage VRF4 (S590: No), the process can proceed to step S510 and the subsequent programming cycle can be repeated.

[0190] Because the second fuzzy programming operation is based on Figure 17 To execute the steps, such as... Figure 19 As shown, the first intermediate programming state P IS The threshold voltage distribution can be changed to the second intermediate programming state P. IS During the second fuzzing operation, with the erase state E IS The threshold voltage of the corresponding memory cell can be maintained.

[0191] Therefore, even if an SPO occurs during the second fine programming operation, the LSB of the selected memory cell can still be accessed by using the intermediate read voltage R. IS Perform an LSB read operation to read the data.

[0192] In the following text, see references Figure 18 and Figure 19 To describe Figure 16 Step S240.

[0193] refer to Figure 18Step S240 may include: applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state PV1 to PV7 (S515); applying a programming enable voltage to a bit line coupled to a memory cell not programmed to a target programming state PV1 to PV7 (S535); applying a programming voltage to a word line coupled to a selected memory cell (S555); performing a verification operation on the selected memory cell using the first to seventh verification voltages VRF1 to VRF7 (S575); and determining whether the selected memory cell is programmed to a target programming state PV1 to PV7 (S595).

[0194] like Figure 19 As shown, steps S515, S535, S555, and S575 can be repeated until the selected memory cell is programmed to the target programming state. In other words, the fine-grained programming operation of the selected memory cell can include multiple programming cycles. Each programming cycle can include steps S515, S535, S555, and S575. Figure 18 Steps S515, S535, S555, and S575 can be respectively connected with Figure 9 Steps S315, S335, S355, and S375 are basically the same. Therefore, Figure 18 The repeated descriptions of steps S515, S535, S555 and S575 will be omitted.

[0195] Because fine programming operations are based on Figure 18 The steps are executed, erasing state E. IS ' and the second intermediate programming state P IS The threshold voltage distribution can be changed to erase state E and the first to seventh target programming states PV1 to PV7. More specifically, with erase state E IS The threshold voltage distribution of the corresponding memory cell can be changed to erase state E and first to third target programming states PV1 to PV3, and intermediate programming state P. IS The threshold voltage distribution can be changed to the fourth to seventh target programming states PV4 to PV7. Therefore, even if an SPO occurs during a fine programming operation, the LSB of the selected memory cell can be read by performing an LSB read operation using the fourth read voltage R4.

[0196] Based on the above references Figures 16 to 19 In the described embodiment, after performing a first fuzzing operation on the selected memory cell, when an SPO occurs during a second fuzzing operation or a fine programming operation, the LSB of the selected memory cell can use the intermediate read voltage R. IS Or the fourth reading voltage R4 is read normally.

[0197] Figure 20 It's a diagram. Figure 7 A flowchart of another embodiment of step S200.

[0198] refer to Figure 20 , Figure 7 Step S200 may include: applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state and a memory cell to be programmed to a lower target programming state (S610); applying a programming enable voltage to a bit line coupled to a memory cell in the memory cell to be programmed to a higher target programming state that is not programmed to a target programming state (S620); applying a first programming voltage to a word line coupled to a selected memory cell (S630); and applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state. The process includes: (S640) applying a programming enable voltage to a bit line coupled to a memory cell to be programmed to a higher target programming state; (S650) applying a second programming voltage to a word line coupled to a selected memory cell; (S660) performing a verification operation on the selected memory cell; and (S670) determining whether all memory cells have been programmed to the target programming state.

[0199] At step S610, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells to be programmed to lower target programming states PV1 to PV3. Additionally, at step S610, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells holding the erase state E. At step S610, a programming inhibit voltage may be applied to the bit lines coupled to the fully programmed memory cells among the memory cells PV4 to PV7 to be programmed to higher target programming states, which are the result of the verification operation performed at step S670 in the previous programming cycle.

[0200] At step S620, a programming disable voltage can be applied to a bit line coupled to a memory cell that was not fully programmed as a result of the verification operation at step S670 in a previous programming cycle, which is to be programmed to a higher target programming state PV4 to PV7.

[0201] At step S630, a first programming voltage can be applied to the selected word line. Therefore, the threshold voltage can be increased only for memory cells that are not fully programmed, among those memory cells to be programmed to higher target programming states PV4 to PV7.

[0202] At step S640, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells to be programmed to higher target programming states PV4 to PV7. Additionally, at step S640, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells holding the erase state E. At step S640, as a result of the verification operation at step S670 in the previous programming cycle, a programming inhibit voltage may be applied to the bit lines coupled to the fully programmed memory cells among the memory cells to be programmed to lower target programming states PV1 to PV3.

[0203] At step S650, as a result of the verification operation at step S670 in the previous programming cycle, a programming allow voltage can be applied to a bit line coupled to an unprogrammed memory cell in the memory cell to be programmed to a lower target programming state PV1 to PV3.

[0204] At step S660, a second programming voltage can be applied to the selected word line. Therefore, the threshold voltage can be increased only for the incompletely programmed memory cells among those memory cells to be programmed to lower target programming states PV1 to PV3. According to one embodiment, the second programming voltage applied to the selected word line at step S660 can have substantially the same magnitude as the first programming voltage applied to the selected word line at step S630. According to another embodiment, the second programming voltage applied to the selected word line at step S660 can be less than the first programming voltage applied to the selected word line at step S630.

[0205] At step S670, the first to seventh verification voltages VRF1 to VRF7 can be used to perform a verification operation on the selected memory cell.

[0206] At step S680, it can be determined whether the programming of the selected memory cells to their respective target programming states has been completed. When the threshold voltage of all selected memory cells is greater than the corresponding verification voltage (S680: Yes), step S200 can end. When the threshold voltage of at least some selected memory cells is less than the corresponding verification voltage (S680: No), the process can proceed to step S610, and the subsequent programming loop can be repeated.

[0207] Figure 21 The diagram illustrates when based on Figure 7 , Figure 8 and Figure 20 The diagram illustrates the threshold voltage distribution of the selected memory cells when the programming operation is performed using the method shown. More specifically, Figure 21 This illustrates the variation in the threshold voltage distribution of the selected memory cell during a programming loop. The following will refer to... Figure 20 and Figure 21 Step S200 will be described as an example of an embodiment according to the present disclosure.

[0208] Through steps S610 and S620, the memory cells corresponding to the erase state E and the lower target programming states PV1 to PV3 can be programmed disabled cells, and the memory cells among the memory cells corresponding to the higher target programming states PV4 to PV7 that have not yet been fully programmed can be programmed cells. Subsequently, when the first programming voltage is applied to the selected memory cell in step S630, only the intermediate programming state P... IS The threshold voltage distribution of the corresponding memory cell can be changed to an intermediate programming state P. IS1 However, compared to the erased state E IS The threshold voltage distribution of the corresponding memory cells can remain unchanged.

[0209] Through steps S640 and S650, the memory cells corresponding to the higher target programming states PV4 to PV7 can be programming disabled cells, and the memory cells among the memory cells corresponding to the lower target programming states PV1 to PV3 that have not yet been fully programmed can be programmed cells. When the second programming voltage is applied to the selected memory cell at step S660, it is only related to the erase state E. IS The threshold voltage distribution of the corresponding memory cell can be changed to the erase state E. IS1 However, with intermediate programming state P IS1 The threshold voltage distribution of the corresponding memory cells can remain unchanged.

[0210] As described above, according to one embodiment, the second programming voltage applied to the selected word line at step S660 may have substantially the same magnitude as the first programming voltage applied to the selected word line at step S630. According to another embodiment, the second programming voltage applied to the selected word line at step S660 may be less than the first programming voltage applied to the selected word line at step S630. When the second programming voltage is less than the first programming voltage, the threshold voltage offset width of the memory cell at step S660 may be less than the threshold voltage offset width of the memory cell at step S630.

[0211] refer to Figure 21During a programming cycle, the threshold voltage of the memory cells corresponding to the higher target programming states PV4 to PV7 can be increased first, and the threshold voltage of the memory cells corresponding to the lower target programming states PV1 to PV3 can then be increased. Therefore, even if an SPO occurs at step S200 during multiple programming cycles, an LSB read operation can be performed by searching for the optimal read voltage. More specifically, when an SPO occurs at step S200 during multiple programming cycles, an intermediate read voltage R can be used. IS To perform an LSB read operation. When using the intermediate read voltage R IS When error correction for LSB data reading fails, a fourth read voltage R4 can be used to perform the LSB read operation. When error correction for LSB data reading using the fourth read voltage R4 fails, the intermediate read voltage R can be determined. IS The LSB read operation can be repeated using any read voltage between the fourth read voltage R4 and the second read voltage R4. For example... Figure 21 As shown, when Figure 20 When fine-grained programming operations are executed, with Figure 11 The memory cell corresponding to the shaded area "A" in the diagram may not occur. Therefore, when performing an LSB read operation using multiple read voltages, the LSB data on the selected memory cell is likely to be read correctly.

[0212] Figure 22 It's a diagram. Figure 7 A flowchart of another embodiment of step S200.

[0213] refer to Figure 22 , Figure 7 Step S200 may include: applying a programming disable voltage to bit lines coupled to memory cells programmed to a target programming state and memory cells to be programmed to a lower target programming state (S615); applying a programming enable voltage to bit lines coupled to memory cells in the memory cells to be programmed to a higher target programming state that are not programmed to a target programming state (S625); applying a first programming voltage to word lines coupled to selected memory cells (S635); applying a programming disable voltage to bit lines coupled to memory cells programmed to a target programming state (S645); applying a programming enable voltage to bit lines coupled to memory cells not programmed to a target programming state (S655); applying a second programming voltage to word lines coupled to selected memory cells (S665); performing a verification operation on selected memory cells using first to seventh verification voltages (S675); and determining whether programming all memory cells to the target programming state has been completed (S685).

[0214] Figure 22Steps S615, S625, and S635 can be respectively connected with Figure 20 Steps S610, S620, and S630 are basically the same. Therefore, Figure 22 The descriptions of steps S615, S625, and S635 will be omitted.

[0215] At step S645, a programming inhibit voltage can be applied to a bit line coupled to the memory cell that remains in the erase state E, and a programming inhibit voltage can be applied to a bit line coupled to the memory cell that has been fully programmed as a result of the verification operation at step S675 in the previous programming cycle.

[0216] At step S655, a programming enable voltage can be applied to a bit line coupled to a memory cell that is not fully programmed as a result of the verification operation at step S670.

[0217] At step S665, a second programming voltage can be applied to the selected word line. Therefore, the threshold voltage of only the unprogrammed memory cells within the selected memory cells can be increased. According to one embodiment, the second programming voltage applied to the selected word line at step S665 can have substantially the same magnitude as the first programming voltage applied to the selected word line at step S635. According to another embodiment, the second programming voltage applied to the selected word line at step S665 can be less than the first programming voltage applied to the selected word line at step S635.

[0218] At step S675, the first to seventh verification voltages VRF1 to VRF7 can be used to perform a verification operation on the selected memory cell.

[0219] At step S685, it can be determined whether the selected memory cells have been fully programmed to their respective target programming states. When the threshold voltage of all selected memory cells is greater than the corresponding verification voltage (S685: Yes), step S200 can end. When the threshold voltage of at least some selected memory cells is less than the corresponding verification voltage (S685: No), the process can proceed to step S615, and the subsequent programming loop can be repeated.

[0220] Figure 23 The diagram illustrates when based on Figure 7 , Figure 8 and Figure 22 The diagram illustrates the threshold voltage distribution of the selected memory cells when the programming operation is performed using the method shown. The following will refer to... Figure 22 and Figure 23 Step S200 will be described as an example of an embodiment according to the present disclosure.

[0221] Through steps S615 and S625, the memory cells corresponding to the erase state E and the lower target programming states PV1 to PV3 can be programmed disabled cells, and the memory cells among the memory cells corresponding to the higher target programming states PV4 to PV7 that have not yet been fully programmed can be programmed cells. Subsequently, when the first programming voltage is applied to the selected memory cell in step S635, only the intermediate programming state P... IS The threshold voltage distribution of the corresponding memory cell can be changed to an intermediate programming state P. IS1 However, compared to the erased state E IS The threshold voltage distribution of the corresponding memory cells can remain unchanged. This can be compared with the reference. Figure 20 and 21 The described embodiments are the same.

[0222] At steps S645 and S655, the memory cell among the selected memory cells that has not yet been fully programmed can be a programming cell. When the second programming voltage is applied to the selected memory cell at step S665, it corresponds to the erase state E. IS The threshold voltage distribution of the corresponding memory cell can be changed to the erase state E. IS1 And with intermediate programming state P IS1 The threshold voltage distribution of the corresponding memory cell can be changed to an intermediate programming state P. IS2 .

[0223] As described above, according to one embodiment, the second programming voltage applied to the selected word line at step S665 may have substantially the same magnitude as the first programming voltage applied to the selected word line at step S635. According to another embodiment, the second programming voltage applied to the selected word line at step S665 may be less than the first programming voltage applied to the selected word line at step S635. When the second programming voltage applied to the selected word line at step S665 is less than the first programming voltage applied to the selected word line at step S635, the threshold voltage offset width of the memory cell at step S665 may be less than the threshold voltage offset width of the memory cell at step S635.

[0224] refer to Figure 23During a programming cycle, the threshold voltage of the memory cells corresponding to the higher target programming states PV4 to PV7 can be increased first, and the threshold voltage of the memory cells corresponding to the higher and lower target programming states PV1 to PV7 can then be increased. Therefore, even if an SPO occurs at step S200 during multiple programming cycles, an LSB read operation can be performed by searching for the optimal read voltage. More specifically, when an SPO occurs at step S200 during multiple programming cycles, an intermediate read voltage R can be used. IS To perform an LSB read operation. When using the intermediate read voltage R IS When error correction for LSB data reading fails, a fourth read voltage R4 can be used to perform the LSB read operation. When error correction for LSB data reading using the fourth read voltage R4 fails, the intermediate read voltage R can be determined. IS The LSB read operation can be repeated using any read voltage between the fourth read voltage R4 and the second read voltage R4. For example... Figure 23 As shown, when Figure 22 When fine-grained programming operations are executed, with Figure 11 The memory cell corresponding to the shaded area "A" in the diagram may not occur. Therefore, when performing an LSB read operation using multiple read voltages, the LSB data on the selected memory cell is likely to be read correctly.

[0225] Figure 24 It's a diagram. Figure 7 A flowchart of another embodiment of step S200.

[0226] refer to Figure 24 , Figure 7Step S200 may include: applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state and a memory cell to be programmed to a higher target programming state (S710); applying a programming enable voltage to a bit line coupled to a memory cell in the memory cell to be programmed to a lower target programming state that is not programmed to a target programming state (S720); applying a first programming voltage to a word line coupled to a selected memory cell (S730); and applying a programming disable voltage to a word line coupled to a memory cell programmed to a target programming state. The process includes: (S740) applying a programming enable voltage to a bit line coupled to a memory cell to be programmed to a lower target programming state; (S750) applying a second programming voltage to a word line coupled to a selected memory cell; (S760) performing a verification operation on the selected memory cell using first to seventh verification voltages; and (S770) determining whether all memory cells have been programmed to the target programming state.

[0227] At step S710, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells to be programmed to higher target programming states PV4 to PV7. Additionally, at step S710, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells holding the erase state E. At step S710, as a result of the verification operation at step S770 in the previous programming cycle, a programming inhibit voltage may be applied to the bit lines coupled to the fully programmed memory cells among the memory cells to be programmed to lower target programming states PV1 to PV3.

[0228] At step S720, as a result of the verification operation at step S770 in the previous programming cycle, a programming inhibit voltage can be applied to the bit line coupled to the memory cell that is not fully programmed in the memory cell to be programmed to the lower target programming states PV1 to PV3.

[0229] At step S730, a first programming voltage can be applied to the selected word line. Therefore, the threshold voltage can be increased only for memory cells that are not fully programmed, among those memory cells to be programmed to lower target programming states PV1 to PV3.

[0230] At step S740, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells to be programmed to lower target programming states PV1 to PV3. Additionally, at step S740, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells holding the erase state E. At step S740, as a result of the verification operation at step S770 in the previous programming cycle, a programming inhibit voltage may be applied to the bit lines coupled to the fully programmed memory cells among the memory cells to be programmed to higher target programming states PV4 to PV7.

[0231] At step S750, as a result of the verification operation at step S770 in the previous programming cycle, a programming allow voltage can be applied to the bit line coupled to the unprogrammed memory cell in the memory cell to be programmed to the higher target programming states PV4 to PV7.

[0232] At step S760, a second programming voltage can be applied to the selected word line. Therefore, the threshold voltage of only the incompletely programmed memory cells among those to be programmed to higher target programming states PV4 to PV7 can be increased. The second programming voltage applied to the selected word line at step S760 can be less than the first programming voltage applied to the selected word line at step S730. Therefore, the threshold voltage offset width of the memory cells to be programmed to higher target programming states PV4 to PV7 at step S760 can be greater than the threshold voltage offset width of the memory cells to be programmed to lower target programming states PV1 to PV3 at step S370. Therefore, even if an SPO occurs at step S200 during multiple programming cycles, an LSB read operation can be performed by searching for the optimal read voltage. More specifically, when an SPO occurs at step S200 during multiple programming cycles, an intermediate read voltage R can be used. IS To perform an LSB read operation. When using the intermediate read voltage R IS When error correction for LSB data reading fails, a fourth read voltage R4 can be used to perform the LSB read operation. When error correction for LSB data reading using the fourth read voltage R4 fails, the intermediate read voltage R can be determined. IS The LSB read operation is repeated using any read voltage between the fourth read voltage R4 and the second read voltage R4. The threshold voltage offset width of the memory cells to be programmed to higher target programming states PV4 to PV7 can be greater than the threshold voltage offset width of the memory cells to be programmed to lower target programming states PV1 to PV3. Therefore, when Figure 24 When fine-grained programming operations are executed, with Figure 11The memory cell corresponding to the shaded area "A" in the diagram may not occur. Therefore, when performing an LSB read operation using multiple read voltages, the LSB data on the selected memory cell is likely to be read correctly.

[0233] At step S770, the first to seventh verification voltages VRF1 to VRF7 can be used to perform a verification operation on the selected memory cell.

[0234] At step S780, it can be determined whether the selected memory cells have been fully programmed to their respective target programming states. When the threshold voltage of all selected memory cells is greater than the corresponding verification voltage (S780: Yes), step S200 can end. When the threshold voltage of at least some selected memory cells is less than the corresponding verification voltage (S780: No), the process can proceed to step S710, and the subsequent programming loop can be repeated.

[0235] Figure 25 It's a diagram. Figure 7 A flowchart of another embodiment of step S200.

[0236] refer to Figure 25 , Figure 7 Step S200 may include: applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state (S715); applying a programming enable voltage to a bit line coupled to a memory cell not programmed to a target programming state (S725); applying a first programming voltage to a word line coupled to a selected memory cell (S735); applying a programming disable voltage to a bit line coupled to a memory cell programmed to a target programming state and a memory cell to be programmed to a lower target programming state (S745); applying a programming enable voltage to a bit line coupled to a memory cell among the memory cells to be programmed to a higher target programming state that is not programmed to a target programming state (S755); applying a second programming voltage to a word line coupled to a selected memory cell (S765); performing a verification operation on the selected memory cell using first to seventh verification voltages (S775); and determining whether all memory cells have been programmed to a target programming state (S785).

[0237] At step S715, a programming inhibit voltage can be applied to a bit line coupled to the memory cell that is in the erase state E, and a programming inhibit voltage can be applied to a bit line coupled to the memory cell that has been fully programmed as a result of the verification operation at step S775 in the previous programming cycle.

[0238] At step S725, a programming enable voltage can be applied to a bit line coupled to a memory cell that has not been fully programmed as a result of the verification operation at step S775 in the previous programming cycle.

[0239] At step S735, a first programming voltage can be applied to the selected word line. The threshold voltage of only the unprogrammed memory cells among the selected memory cells can be increased.

[0240] At step S745, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells to be programmed into lower target programming states PV1 to PV3. Additionally, at step S745, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells holding the erase state E. At step S745, a programming inhibit voltage may be applied to the bit lines coupled to the memory cells to be programmed into higher target programming states PV4 to PV7 that have been fully programmed as a result of the verification operation at step S775 in the previous programming cycle.

[0241] At step S755, a programming enable voltage can be applied to a bit line coupled to a memory cell that is not fully programmed as a result of the verification operation at step S775 in a previous programming cycle, which is to be programmed to a higher target programming state PV4 to PV7.

[0242] At step S765, a second programming voltage can be applied to the selected word line. Therefore, the threshold voltage of only the incompletely programmed memory cells among those to be programmed to higher target programming states PV4 to PV7 can be increased. The second programming voltage applied to the selected word line at step S765 can be less than the first programming voltage applied to the selected word line at step S735. Therefore, the threshold voltage offset width of the memory cells to be programmed to higher target programming states PV4 to PV7 at step S765 can be greater than the threshold voltage offset width of the memory cells to be programmed to higher and lower target programming states PV1 to PV7 at step S735. Therefore, even if an SPO occurs at step S200 during multiple programming cycles, the LSB read operation can be performed by searching for the optimal read voltage. More specifically, when an SPO occurs at step S200 during multiple programming cycles, an intermediate read voltage R can be used. IS To perform an LSB read operation. When using the intermediate read voltage R IS When error correction for LSB data reading fails, a fourth read voltage R4 can be used to perform the LSB read operation. When error correction for LSB data reading using the fourth read voltage R4 fails, the intermediate read voltage R can be determined. ISThe LSB read operation is repeated using any read voltage between the fourth read voltage R4 and the second read voltage R4. Since the threshold voltage offset width of the memory cells to be programmed to higher target programming states PV4 to PV7 in step S765 is greater than the threshold voltage offset width of the memory cells to be programmed to higher and lower target programming states PV1 to PV7, when... Figure 25 When fine-grained programming operations are executed, with Figure 11 The memory cell corresponding to the shaded area "A" in the diagram may not occur. Therefore, when performing an LSB read operation using multiple read voltages, the LSB data on the selected memory cell is likely to be read correctly.

[0243] At step S775, the first to seventh verification voltages VRF1 to VRF7 can be used to perform a verification operation on the selected memory cell.

[0244] At step S785, it can be determined whether the selected memory cells have been fully programmed to their respective target programming states. When the threshold voltage of all selected memory cells is greater than the corresponding verification voltage (S785: Yes), step S200 can end. When the threshold voltage of at least some selected memory cells is less than the corresponding verification voltage (S785: No), the process can proceed to step S715, and the subsequent programming loop can be repeated.

[0245] Figure 26 It's a diagram. Figure 1 A diagram illustrating an embodiment of the controller 200.

[0246] refer to Figure 26 The controller 200 can be coupled to the host and the semiconductor memory device 100. The semiconductor memory device 100 can be as described above. Figure 2 The semiconductor memory device described. In one embodiment, the memory system 1000 may include a controller and a semiconductor memory device.

[0247] In response to a request from the host, the controller 200 can access the semiconductor memory device 100. For example, the controller 200 can control write, read, erase, and background operations of the semiconductor memory device 100. The controller 200 can provide an interface between the semiconductor memory device 100 and the host. The controller 200 can drive firmware for controlling the semiconductor memory device 100.

[0248] The controller 200 may include random access memory (RAM) 210, processing unit 220, host interface 230, memory interface 240, and error correction code (ECC) block 250. RAM 210 may be used as at least one of the following: working memory, cache memory between semiconductor memory device 100 and host, and buffer memory between semiconductor memory device 100 and host.

[0249] The processing unit 220 can control the overall operation of the controller 200.

[0250] The host interface 230 may include protocols for exchanging data between the host and the controller 200. According to one embodiment, the controller 200 may communicate with the host via one or more different protocols such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocols, etc.

[0251] The memory interface 240 can be interfaced with the semiconductor memory device 100. For example, the memory interface 240 may include a NAND interface or a NOR interface.

[0252] ECC block 250 can be configured to detect and correct errors in data received from semiconductor memory device 100. Processing unit 220 can control semiconductor memory device 100 to control the read voltage and perform a reread based on the error detection results.

[0253] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form memory cards such as those from the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) cards, Smart Media Cards (SM or SMC), Memory Sticks, Multimedia Cards (MMC, RS-MMC, or MMCmicro), SD cards (SD, miniSD, microSD, or SDHC), Universal Flash Memory (UFS), etc.

[0254] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid-state drive (SSD). The SSD may include a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of the host coupled to the memory system 1000 can be significantly improved.

[0255] In another example, the memory system 1000, including the controller 200 and the semiconductor memory device 100, can be provided as one of various components of an electronic device such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of sending / receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, an RFID device, etc.

[0256] In one embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various forms of packages. For example, the semiconductor memory device 100 or memory system 1000 can be embedded in packages such as: stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle package die, die-on-chip die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC) package, shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stacked package (WSP), etc.

[0257] Figure 27 It's a diagram. Figure 26 A block diagram illustrating an application example of the memory system 1000.

[0258] refer to Figure 27 The memory system 2000 may include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 may include semiconductor memory chips. The semiconductor memory chips may be divided into multiple groups.

[0259] Figure 27 The diagram illustrates a group communicating with controller 2200 via channels CH1 to CHk (first to kth). Each semiconductor memory chip can communicate with the above reference. Figure 2 The semiconductor memory device 100 described is configured and operated in a substantially the same manner.

[0260] Each group can communicate with controller 2200 through a single common channel. Controller 2200 can communicate with a reference... Figure 26 The controller 200 described is configured in a substantially similar manner and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0261] Figure 28 The diagram includes the references above. Figure 27 A block diagram of the memory system 2000 and the computing system 3000 described.

[0262] The computing system 3000 may include a central processing unit 3100, random access memory (RAM) 3200, user interface 3300, power supply 3400, system bus 3500 and memory system 2000.

[0263] The memory system 2000 can be electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 can be stored in the memory system 2000.

[0264] like Figure 28 As shown, the semiconductor memory device 2100 can be coupled to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can also be directly coupled to the system bus 3500. The central processing unit 3100 and the RAM 3200 can perform the functions of the controller 2200.

[0265] like Figure 28 As shown in the reference Figure 27 The memory system 2000 described above can be provided. However, the memory system 2000 can be derived from the above-mentioned references. Figure 26 The memory system 1000 described herein, which includes a controller 200 and a semiconductor memory device 100, is replaced.

[0266] According to one embodiment of the present disclosure, a semiconductor memory device and a method of operating the same can be provided to improve data reliability.

Claims

1. A method of operating a semiconductor memory device, the method comprising programming selected memory cells to store N bits of data in each of the selected memory cells, the method comprising: Fuzzy programming is used to program the target to the first to (2)th levels by using an intermediate verification voltage. N -1) The (2nd)th step in the target programming state N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state is increased to the intermediate programming state; as well as Fine-grained programming, used by using the first to (2) N -1) Verify the voltage and program the selected memory cell to the target programming state. The fine programming includes: adding the part to be programmed to the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state, and the increase to be programmed to the first to (2) N-1 -1) The threshold voltage of the second memory cell in the target programming state. The threshold voltage for increasing the second memory cell is performed after the threshold voltage for increasing the first memory cell is increased. Where N is a natural number greater than 1, When the fine programming of the first memory cell is paused, a first read operation to resume the fine programming of the first memory cell is performed using a first read voltage between the erase voltage and the intermediate verification voltage, and When the fine programming of the second memory cell is paused, a second read operation for resuming the fine programming of the second memory cell is performed using a second read voltage between the threshold voltage of the first memory cell and the threshold voltage of the second memory cell.

2. The method according to claim 1, wherein the intermediate verification voltage is less than the (2)th... N-1 Verify the voltage.

3. The method according to claim 1, wherein the fuzzy programming comprises: A programming disable voltage is applied to a bit line coupled to a third memory cell within the first memory cell that is programmed to the intermediate programming state. A programming enable voltage is applied to a bit line coupled to a fourth memory cell within the first memory cell that is not fully programmed into the intermediate programming state. A programming voltage is applied to a word line coupled to the selected memory cell; as well as The verification operation is performed on the fourth memory cell by using the intermediate verification voltage.

4. The method of claim 1, wherein the fine programming comprises: By using the (2) N-1 ) to (2) N -1) Verify the voltage, increase the voltage to be programmed to the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state; as well as By using the first to the (2) N-1 -1) Verify the voltage, increase the voltage to be programmed to the first to (2) N-1 -1) Threshold voltage of the second memory cell in the target programming state.

5. The method of claim 4, wherein the addition to be programmed into the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state includes: A programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state within the selected memory cell, and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to memory cells that are not fully programmed in the first memory cell of the target programming state; A programming voltage is applied to a word line coupled to the selected memory cell; as well as By using the (2) N-1 ) to (2) N -1) Verify the voltage, to be programmed to the (2) N-1 ) to (2) N -1) The first memory cell in the target programming state performs a verification operation.

6. The method of claim 4, wherein the addition to be programmed into the first to (2) N-1 -1) The threshold voltage of the second memory cell in the target programming state includes: The programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state in the selected memory cell and to the (2) N-1 ) to (2) N -1) The bit line coupled to the first memory cell corresponding to the target programming state; The programming allows the voltage to be applied to the values ​​corresponding to the first to (2). N-1 -1) Bit lines coupled to memory cells that are not fully programmed in the second memory cell of the target programming state; A programming voltage is applied to a word line coupled to the selected memory cell; as well as By using the first to (2) N-1 -1) Verify the voltage, for the voltage to be programmed to the first to (2) N-1 -1) The second memory cell in the target programming state performs a verification operation.

7. The method of claim 1, wherein the fine programming comprises: A programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state within the selected memory cell, and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to memory cells that are not fully programmed in the first memory cell of the target programming state; A first programming voltage is applied to the word line coupled to the selected memory cell; The programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state in the selected memory cell and to the (2) N-1 ) to (2) N -1) The bit line coupled to the first memory cell corresponding to the target programming state; The programming allows the voltage to be applied to the values ​​corresponding to the first to (2). N-1 -1) Bit lines coupled to memory cells that are not fully programmed in the second memory cell of the target programming state; A second programming voltage, less than the first programming voltage, is applied to the word line coupled to the selected memory cell; as well as By using the first to (2) N -1) Verify the voltage and perform a verification operation on the selected memory cell.

8. The method of claim 1, wherein the fine programming comprises: A programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state within the selected memory cell, and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to memory cells that are not fully programmed in the first memory cell of the target programming state; A first programming voltage is applied to the word line coupled to the selected memory cell; A programming disable voltage is applied to a bit line coupled to a fully programmed memory cell within the selected memory cell. A programming-enabled voltage is applied to a bit line coupled to an unprogrammed memory cell within the selected memory cell. A second programming voltage, less than the first programming voltage, is applied to the word line coupled to the selected memory cell; as well as By using the first to (2) N -1) Verify the voltage and perform a verification operation on the selected memory cell.

9. The method according to claim 1, wherein N is 3 (triple).

10. A method of operating a semiconductor memory device, the method comprising programming selected memory cells to store N bits of data in each of the selected memory cells, the method comprising: Fuzzy programming is used to program the target to the first to (2)th levels by using an intermediate verification voltage. N -1) The (2nd)th step in the target programming state N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state is increased to the intermediate programming state; as well as Fine-grained programming, used by using the first to (2) N -1) Verify the voltage and program the selected memory cell to the target programming state. The fine programming mentioned above includes: adding the programmable elements to the first to (2)th levels. N-1 -1) The threshold voltage of the second memory cell in the target programming state, and the increase to be programmed into the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state. The threshold voltage increase of the first memory cell is performed after the threshold voltage increase of the second memory cell is performed. Where N is a natural number greater than 1, When the fine programming of the first memory cell is paused, a first read operation to resume the fine programming of the first memory cell is performed using a first read voltage between the erase voltage and the intermediate verification voltage, and When the fine programming of the second memory cell is paused, a second read operation for resuming the fine programming of the second memory cell is performed using a second read voltage between the threshold voltage of the first memory cell and the threshold voltage of the second memory cell.

11. The method of claim 10, wherein the fine programming comprises: The programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state in the selected memory cell and to the (2) N-1 ) to (2) N -1) The bit line coupled to the first memory cell corresponding to the target programming state; The programming allows the voltage to be applied to the values ​​corresponding to the first to (2). N-1 -1) Bit lines coupled to memory cells that are not fully programmed in the second memory cell of the target programming state; A first programming voltage is applied to the word line coupled to the selected memory cell; A programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state within the selected memory cell, and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to memory cells that are not fully programmed in the first memory cell of the target programming state; A second programming voltage greater than the first programming voltage is applied to the word line coupled to the selected memory cell; as well as By using the first to (2) N -1) Verify the voltage and perform a verification operation on the selected memory cell.

12. The method of claim 10, wherein the fine programming comprises: A programming disable voltage is applied to a bit line coupled to a fully programmed memory cell within the selected memory cell. A programming-enabled voltage is applied to a bit line coupled to an unprogrammed memory cell within the selected memory cell. A first programming voltage is applied to the word line coupled to the selected memory cell; A programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state within the selected memory cell, and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to memory cells that are not fully programmed in the first memory cell of the target programming state; A second programming voltage greater than the first programming voltage is applied to the word line coupled to the selected memory cell; as well as By using the first to (2) N -1) Verify the voltage and perform a verification operation on the selected memory cell.

13. A method of operating a semiconductor memory device, the method comprising programming selected memory cells to store N bits of data in each of the selected memory cells, the method comprising: The first fuzzy programming is used to program the object to be programmed into the first to (2)th fuzzy programming by using an intermediate verification voltage. N -1) The (2nd)th step in the target programming state N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state is increased to the first intermediate programming state; The second fuzzy programming is used to employ a (2) fuzzy programming method that utilizes a voltage greater than the intermediate verification voltage. N -1) Verify the voltage, and then program the voltage to be used in the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state increases from the first intermediate programming state to the second intermediate programming state; as well as Fine-grained programming, used by using the first to (2) N -1) Verify the voltage and program the selected memory cell to the target programming state. The fine programming mentioned therein includes adding to be programmed into the (2) N-1 ) to (2) N -1) The threshold voltage of the first memory cell in the target programming state, and increase the voltage to be programmed into the first to (2) N-1 -1) The threshold voltage of the second memory cell in the target programming state. Where N is a natural number greater than 1, and When the fine programming is paused, the read operation to resume the fine programming is performed using a read voltage between the threshold voltage of the first memory cell and the threshold voltage of the second memory cell.

14. The method of claim 13, wherein the first fuzzy programming comprises: A programming disable voltage is applied to a bit line coupled to a third memory cell that has been programmed into the first intermediate programming state; A programming enable voltage is applied to a bit line coupled to a fourth memory cell within the first memory cell that is not fully programmed to the first intermediate programming state. A programming voltage is applied to a word line coupled to the selected memory cell; as well as The verification operation is performed on the fourth memory cell by using an intermediate verification voltage.

15. The method of claim 14, wherein the second fuzzy programming comprises: The programming disable voltage is applied to the memory cell that is fully programmed to the corresponding target programming state in the selected memory cell and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) Bit lines coupled to memory cells that are not fully programmed in the first memory cell of the target programming state; A programming voltage is applied to a word line coupled to the selected memory cell; as well as By using the (2) N-1 ) to (2) N -1) Verify the voltage, to be programmed to the (2) N-1 ) to (2) N -1) The first memory cell in the target programming state performs a verification operation.

16. The method of claim 15, wherein the second fuzzing further comprises: After performing the verification operation, determine the (2) N-1 ) to (2) N -1) Whether the threshold voltage of all the first memory cells corresponding to the target programming state is greater than the (2) N-1 Verify the voltage.

17. The method of claim 16, wherein the second fuzzing is in response to determining the relationship with the (2) N-1 ) to (2) N -1) The threshold voltage of all the first memory cells corresponding to the target programming state is greater than the threshold voltage of the (2) N-1 The process ends after verifying the voltage.

18. The method of claim 16, wherein in response to determining the (2) N-1 ) to (2) N -1) At least one of the threshold voltages of the first memory cell corresponding to the target programming state is less than the threshold voltage of the (2) N-1 To verify the voltage, the second fuzzy programming repeats the following operations: The programming disable voltage is applied to the memory cell in the selected memory cell that is fully programmed to the corresponding target programming state, and to the first to (2)th memory cells. N-1 -1) The bit line coupled to the second memory cell corresponding to the target programming state; The programming-enabled voltage is applied to the voltage corresponding to the (2) N-1 ) to (2) N -1) The bit line coupled to the memory cell that is not fully programmed in the first memory cell of the target programming state; The programming voltage is applied to the word line coupled to the selected memory cell; as well as By using the (2) N-1 ) to (2) N -1) Verify the voltage, to be programmed to the (2) N-1 ) to (2) N -1) The first memory cell in the target programming state performs the verification operation.

19. The method of claim 13, wherein the fine programming comprises: A programming disable voltage is applied to a bit line coupled to a memory cell that is fully programmed to the corresponding target programming state within the selected memory cell. A programming enable voltage is applied to a bit line coupled to a memory cell that is not fully programmed to the corresponding target programming state within the selected memory cell; A programming voltage is applied to a word line coupled to the selected memory cell; as well as By using the first to (2) N -1) Verify the voltage and perform a verification operation on the selected memory cell.

20. The method of claim 13, wherein the intermediate verification voltage is less than the (2) N-1 Verify the voltage.

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