Test methods and apparatus for semiconductor structures

Abstract

This application relates to a testing method and apparatus for semiconductor structures. The testing method for semiconductor structures includes the following steps: providing a memory array, which includes multiple memory cells, multiple word lines, and multiple bit lines arranged in an array, the bit lines being electrically connected to multiple sense amplifiers; repeatedly executing the following first loop steps until all memory cells in the memory array are filled with 0; the first loop steps include: selecting a word line as a first target word line and turning on the first target word line; turning on the sense amplifiers after a first preset time delay from the turn-on of the first target word line; turning off the first target word line and the sense amplifiers after a second preset time delay from the turn-on of the first target word line, and using the next word line adjacent to the first target word line as the first target word line for the next first loop step. This application improves the accuracy and efficiency of detecting short-circuit defects between word lines and bit lines.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a testing method and testing apparatus for semiconductor structures. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] Semiconductor structures such as Dynamic Random Access Memory (DRAM) include word lines and bit lines. Current word lines mostly use buried word lines (BWL), and bit lines are electrically connected to the source of transistors via bit line plugs. Due to variations in manufacturing processes, short circuits may occur between the buried word line and the bit line contact (BLC), resulting in a cross-failure. A short circuit between the buried word line and the bit line contact leads to bit line failure, severely impacting the electrical performance of the semiconductor structure. However, there is currently no effective method to detect short-circuit defects between the buried word line and the bit line contact, thus limiting improvements to semiconductor structures.

[0004] Therefore, how to effectively detect short-circuit defects between word lines and bit lines and improve the electrical performance of semiconductor structures is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The semiconductor structure testing method and testing apparatus provided in some embodiments of this application are used to solve the problem of not being able to effectively detect short-circuit defects between word lines and bit lines, so as to improve the electrical performance of semiconductor structures.

[0006] According to some embodiments, this application provides a method for testing semiconductor structures, including the following steps:

[0007] A memory array is provided, comprising a plurality of memory cells arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, wherein the plurality of bit lines are electrically connected to a plurality of inductive amplifiers, and the first direction and the second direction intersect.

[0008] The first loop step is executed repeatedly until all the memory cells in the memory array are filled with 0;

[0009] The first loop step includes:

[0010] Select a character line as the first target character line and enable the first target character line;

[0011] The induction amplifier is activated after the first target word line is turned on and after a first preset time delay.

[0012] After the first target word line is turned on and delayed for a second preset time, the first target word line and the induction amplifier are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step.

[0013] In some embodiments, the following steps are included before performing the loop steps:

[0014] All the memory cells in the memory array are filled with 0;

[0015] Refresh the storage array.

[0016] In some embodiments, the specific steps of filling all the memory cells in the memory array with 0s before performing the loop step include:

[0017] The second loop step is executed repeatedly until all the memory cells in the memory array are filled with 0. The second loop step includes:

[0018] Select a character line as the second target character line and enable the second target character line;

[0019] Write sequentially from 0 to all the memory cells connected to the second target word line;

[0020] Close the second target word line, and use the next word line adjacent to the second target word line as the second target word line for the next second cycle step.

[0021] In some embodiments, the first loop step includes:

[0022] Select a bitline as the target bitline and enable the target bitline;

[0023] The first sub-loop step is executed sequentially for multiple of the aforementioned word lines;

[0024] The target bit line is turned off, and the next bit line adjacent to the target bit line is used as the target bit line for the next first loop step.

[0025] The first sub-loop step includes:

[0026] Select a word line as the first target word line, enable the first target word line, and write 0 to the memory cell that is electrically connected to both the first target word line and the target bit line;

[0027] After the first target word line is turned on and after a first preset time delay, the induction amplifier electrically connected to the target bit line is turned on.

[0028] After the first target word line is turned on and delayed for a second preset time, the first target word line and the inductive amplifier electrically connected to the target bit line are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step.

[0029] In some embodiments, the first loop step includes:

[0030] Select a word line as the first target word line, and perform the second sub-loop step on the first target word line;

[0031] After performing the second sub-loop step on the first target word line, the next word line adjacent to the first target word line is taken as the first target word line for the next first loop step;

[0032] The second sub-loop step includes:

[0033] Enable the first target word line;

[0034] Enable several bit lines and write 0 to several memory cells connected to the first target word line and several bit lines;

[0035] After the first target word line is turned on and after a first preset time delay, the sensing amplifier electrically connected to the plurality of bit lines is turned on.

[0036] After the first target word line is turned on and after a second preset time delay, the first target word line and the sensing amplifier electrically connected to the plurality of bit lines are turned off.

[0037] In some embodiments, the first loop step includes:

[0038] Select a character line as the first target character line and enable the first target character line;

[0039] Enable all the bit lines and write 0 to all the memory cells connected to the first target word line;

[0040] After the first target word line is turned on and after a first preset time delay, the sensing amplifier that is electrically connected to all the bit lines is turned on.

[0041] After the first target word line is turned on and delayed for a second preset time, the first target word line and the sensing amplifier electrically connected to all the bit lines are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step.

[0042] In some embodiments, the first preset time is 10ns to 400ns.

[0043] In some embodiments, the second preset time is 100ns to 1000ns.

[0044] In some embodiments, the number of storage arrays is multiple; after all the storage cells in a storage array are filled with 0, the following steps are further included:

[0045] Refresh the storage array that is currently filled with 0s;

[0046] The first loop step is performed on the next storage array until all the storage cells in the next storage array are filled with 0.

[0047] In some embodiments, after all the memory cells in the memory array are filled with 0, the following steps are further included:

[0048] Read all the storage cells in the storage array;

[0049] Determine whether the read values ​​of all the memory cells are 0. If not, confirm that the word line and the bit line at the memory cell where the read value is not 0 are electrically connected.

[0050] In some embodiments, the specific steps for reading all the storage cells in the storage array include:

[0051] The third loop step is executed multiple times until all the storage cells in the storage array have been read. The third loop step includes:

[0052] Select a word line as the third target word line, and read all memory cells connected to the third target word line;

[0053] After all memory cells connected to the third target word line have been read, the next word line adjacent to the third target word line is used as the third target word line for the next third loop step.

[0054] According to other embodiments, this application also provides a semiconductor structure testing apparatus, comprising:

[0055] The write module is used to execute the following first loop step multiple times until all the memory cells in the memory array are filled with 0; the memory array includes multiple memory cells arranged in an array, multiple word lines arranged in parallel along a first direction, and multiple bit lines arranged in parallel along a second direction, the multiple bit lines being electrically connected to multiple sense amplifiers, the first direction and the second direction intersecting; the first loop step includes: selecting a word line as a first target word line and turning on the first target word line; after the first target word line is turned on for a first preset time, turning on the sense amplifier; after the first target word line is turned on for a second preset time, turning off the first target word line and the sense amplifier, and using the next word line adjacent to the first target word line as the first target word line for the next first loop step.

[0056] In some embodiments, the semiconductor structure testing apparatus further includes:

[0057] A refresh module is used to refresh the storage array that has been filled with 0s.

[0058] In some embodiments, it also includes:

[0059] The read module is used to read all the storage cells in the storage array;

[0060] The judgment module is used to determine whether the read values ​​of all the memory cells are 0. If not, it is confirmed that the memory array has a defect of short circuit between the bit line and the word line.

[0061] In some embodiments, the first preset time is 10ns to 400ns.

[0062] In some embodiments, the second preset time is 100ns to 1000ns.

[0063] The semiconductor structure testing method and apparatus provided in some embodiments of this application fill all memory cells of the memory array with 0s, and use the voltage difference generated between the high potential of the word line when it is turned on and the low potential of the bit line to simulate the phenomenon of short circuit between word lines and bit lines. Some embodiments of this application turn on the sensing amplifier after the target word line is turned on and delayed for a first preset time, and turn off the target word line after the target word line is turned on and delayed for a second preset time. This prolongs the time from the target word line turning on to the sensing amplifier turning on, and the time the target word line is in the active state. Therefore, once a short circuit occurs between the word line and the bit line, the sensing amplifier can fully detect the defect, improving the accuracy and efficiency of short circuit defect detection between word lines and bit lines. Attached Figure Description

[0064] Appendix Figure 1This is a flowchart of a testing method for a semiconductor structure in a specific embodiment of this application;

[0065] Appendix Figure 2 This is a schematic diagram of the storage array structure in a specific embodiment of this application;

[0066] Appendix Figure 3 This is a schematic diagram of a test method for the first semiconductor structure in a specific embodiment of this application;

[0067] Appendix Figure 4 This is a schematic diagram of the testing method for the second semiconductor structure in a specific embodiment of this application;

[0068] Appendix Figure 5 This is a schematic diagram of a test method for the third semiconductor structure in a specific embodiment of this application;

[0069] Appendix Figure 6 This is a structural block diagram of a semiconductor structure testing device in a specific embodiment of this application. Detailed Implementation

[0070] The following detailed description, in conjunction with the accompanying drawings, illustrates the specific implementation methods and apparatus for testing semiconductor structures provided in this application.

[0071] This specific embodiment provides a method for testing semiconductor structures, with appended... Figure 1 This is a flowchart of the testing method for the semiconductor structure in a specific embodiment of this application, attached. Figure 2 This is a schematic diagram of the storage array structure in a specific embodiment of this application, attached. Figure 3 This is a schematic diagram of a testing method for the first semiconductor structure in a specific embodiment of this application. For example... Figure 1 , Figure 2 and Figure 3 As shown, the testing method for the semiconductor structure includes the following steps:

[0072] Step S11: Provide a memory array, which includes a plurality of memory cells 20 arranged in an array, a plurality of word lines WL arranged in parallel along a first direction, and a plurality of bit lines BL arranged in parallel along a second direction. The plurality of bit lines BL are electrically connected to a plurality of inductive amplifiers. The first direction and the second direction intersect.

[0073] Specifically, the first direction and the second direction can intersect at an angle or perpendicularly. The semiconductor structure can be, but is not limited to, DRAM; correspondingly, the memory array can be a memory array within a DRAM. The memory array is located on a substrate, which has multiple active regions arranged in an array. Each active region includes a bit line contact region and a capacitor contact region. The word line WL can be an embedded word line located within the substrate. The bit line BL is electrically connected to the bit line contact region within the substrate via a bit line contact plug. When there is a deviation in the manufacturing process, the bit line contact plug may come into contact with the word line, resulting in a short circuit between the bit line BL and the word line WL. Figure 2 Taking the schematic diagram of the storage array shown as an example, each word line WL extends along the X-axis, and multiple word lines WL are arranged in parallel along the Y-axis. Each bit line BL extends along the Y-axis, and multiple bit lines BL are arranged in parallel along the X-axis. Figure 2 In the structure shown, the intersection of each word line WL and each bit line BL forms a memory cell 20. In this specific embodiment, "multiple" refers to two or more.

[0074] Multiple sense amplifiers are electrically connected to multiple bit lines BL in a one-to-one correspondence. Each memory cell 20 is electrically connected to one bit line BL, and one bit line BL is electrically connected to multiple memory cells arranged parallel to the Y-axis. Therefore, one sense amplifier is electrically connected to multiple memory cells 20, and one memory cell 20 is electrically connected to only one sense amplifier. When the bit line BL is electrically connected to the word line WL, the sense amplifier electrically connected to the shorted bit line BL can detect the leakage current generated by the short circuit between the bit line BL and the word line WL, thereby realizing the detection of the short circuit defect between the bit line BL and the word line WL. The specific electrical connection method between the sense amplifier and the bit line BL can be selected by those skilled in the art according to actual needs, as long as it can realize the detection of the leakage current generated when the bit line BL and the word line WL are shorted.

[0075] Step S12: Execute the following first loop step multiple times until all the storage cells 20 in the storage array are filled with 0;

[0076] The first loop step includes:

[0077] Select a character line as the first target character line and enable the first target character line;

[0078] The induction amplifier is activated after the first target word line is turned on and after a first preset time delay.

[0079] After the first target word line is turned on and delayed for a second preset time, the first target word line and the induction amplifier are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step.

[0080] Specifically, during defect detection of the memory array, all memory cells 20 in the memory array are filled with 0s. The voltage difference between the high potential of the word line when it is enabled and the low potential of the bit line is used to simulate a short circuit between the word line and the bit line. By sequentially enabling each word line WL and sequentially writing 0s into the memory cells 20 electrically connected to the enabled word lines, the leakage current detected by the sensing amplifier electrically connected to the memory cell 20 after the write operation is completed can confirm whether the word line WL connected to the memory cell 20 after the write operation is completed is short-circuited (i.e., short-connected). For example, when the leakage current detected by the sensing amplifier is greater than a threshold, it is confirmed that the bit line BL electrically connected to the sensing amplifier is short-circuited with the enabled word line WL. The specific value of the threshold can be set by those skilled in the art according to actual needs, such as according to the specific structure of the memory cell 20.

[0081] This specific embodiment activates the sensing amplifier after the target word line is activated and delayed for a first preset time, and then deactivates the target word line after the target word line is activated and delayed for a second preset time. This extends the time from when the target word line is activated to when the sensing amplifier is activated, as well as the time when the target word line is in an active state. This ensures that the sensing amplifier can fully detect the defect in the event of a short circuit between the word line and the bit line, thereby improving the accuracy and efficiency of short circuit defect detection between the word line and the bit line.

[0082] In some embodiments, the first preset time is 10ns to 400ns. For example, the first preset time is 10ns, 50ns, 100ns, 200ns, or 400ns.

[0083] In some embodiments, the second preset time is 100ns to 1000ns. For example, the second preset time is 100ns, 300ns, 500ns, 700ns, or 1000ns.

[0084] In some embodiments, the following steps are included before performing the loop steps:

[0085] All the memory cells 20 in the memory array are filled with 0, such as Figure 3 As shown in (a) in the text;

[0086] Refresh the storage array, such as Figure 3 As shown in (b) of the diagram.

[0087] In some embodiments, the specific steps of filling all the memory cells 20 in the memory array with 0s before performing the loop step include:

[0088] The second loop step is executed repeatedly until all the memory cells 20 in the memory array are filled with 0. The second loop step includes:

[0089] Select a word line WL as the second target word line and enable the second target word line;

[0090] Write sequentially to all the memory cells 20 connected to the second target word line from 0;

[0091] The second target word line is closed, and the next word line WL adjacent to the second target word line is used as the second target word line for the next second cycle step.

[0092] For example, the second loop step is executed for the first time: the word line WL located in the first row of the memory array is selected as the second target word line; then, the second target word line and all the bit lines BL are turned on, so that all memory cells 20 electrically connected to the second target word line are filled with 0; then, the second target word line is turned off. The second loop step is executed for the second time: the word line WL located in the second row of the memory array is selected as the second target word line; then, the second target word line and all the bit lines BL are turned on, so that all memory cells 20 electrically connected to the second target word line are filled with 0; then, the second target word line is turned off. The second loop step is executed for the third time: the word line WL located in the third row of the memory array is selected as the second target word line; then, the second target word line and all the bit lines BL are turned on, so that all memory cells 20 electrically connected to the second target word line are filled with 0; then, the second target word line is turned off. And so on, by executing the second loop step multiple times, all the word lines WL in the memory array are turned on and off, so that the memory array is filled with 0.

[0093] In this specific embodiment, before entering the test mode and executing the first loop step multiple times, the second loop step is executed multiple times to fill the memory array with 0s. This avoids the influence of other defects in the memory array and ensures that the leakage current detected by the sensing amplifier is caused by the short circuit between the word line WL and the bit line BL, thereby further improving the accuracy and reliability of the test results.

[0094] In other embodiments, the first loop step includes:

[0095] Select a bitline as the target bitline and enable the target bitline;

[0096] The first sub-loop step is executed sequentially for multiple of the aforementioned word lines;

[0097] The target bit line is turned off, and the next bit line adjacent to the target bit line is used as the target bit line for the next first loop step.

[0098] The first sub-loop step includes:

[0099] Select a word line WL as the first target word line, enable the first target word line, and write 0 to the memory cell that is electrically connected to both the first target word line and the target bit line;

[0100] After the first target word line is turned on and after a first preset time delay, the induction amplifier electrically connected to the target bit line is turned on.

[0101] After the first target word line is turned on and delayed for a second preset time, the first target word line and the inductive amplifier electrically connected to the target bit line are turned off, and the next word line WL adjacent to the first target word line is taken as the first target word line for the next first cycle step.

[0102] For example, after entering test mode, the first loop step is executed for the first time: the bit line BL located in the first column of the memory array is selected as the target bit line, and the target bit line is turned on. Then, the first sub-loop step is executed for the first time: the word line WL located in the first row of the memory array is selected as the first target word line, the first target word line is turned on, and 0 is written to a memory cell that is electrically connected to both the first target word line and the target bit line; after the first target word line is turned on for a first preset time, the sensing amplifier electrically connected to the target bit line is turned on; after the first target word line is turned on for a second preset time, the first target word line and the sensing amplifier electrically connected to the target bit line are turned off. Next, the first sub-loop step is executed for the second time: the word line WL located in the second row of the storage array is selected as the first target word line, and the first target word line is turned on, and 0 is written to a storage cell electrically connected to both the first target word line and the target bit line; after the first target word line is turned on for a first preset time, the sense amplifier electrically connected to the target bit line is turned on; after the first target word line is turned on for a second preset time, the first target word line and the sense amplifier electrically connected to the target bit line are turned off. This process is repeated until multiple word lines WL have completed the first sub-loop step, thereby ensuring that all storage cells 20 electrically connected to the target bit line have completed the operation of writing 0, such as... Figure 3 As shown in (c) in the figure.

[0103] After the target bit line is turned off, the first loop step is executed a second time: the bit line BL located in the second column of the storage array is selected as the target bit line, and the target bit line is turned on. Then, the first sub-loop step is executed multiple times, so that all the storage cells 20 electrically connected to the target bit line complete the write operation of 0. The specific operation of executing the first sub-loop step multiple times is the same as the operation of executing the first sub-loop step multiple times in the first execution of the first loop step.

[0104] By repeating this process multiple times, all bit lines BL in the storage array have completed the first loop step sequentially, and the storage array is filled with 0s.

[0105] In other embodiments, the first loop step includes:

[0106] Select a word line WL as the first target word line, and perform the second sub-loop step on the first target word line;

[0107] After performing the second sub-loop step on the first target word line, the next word line WL adjacent to the first target word line is taken as the first target word line for the next first loop step;

[0108] The second sub-loop step includes:

[0109] Enable the first target word line;

[0110] Enable several bit lines and write 0 to several memory cells connected to the first target word line and several bit lines;

[0111] After the first target word line is turned on and after a first preset time delay, the sensing amplifier electrically connected to the plurality of bit lines is turned on.

[0112] After the first target word line is turned on and after a second preset time delay, the first target word line and the sensing amplifier electrically connected to the plurality of bit lines are turned off.

[0113] Appendix Figure 4 This is a schematic diagram of the testing method for the second semiconductor structure in a specific embodiment of this application. Figure 4 Operations (a) and (b) in the text are related to Figure 3 Operations (a) and (b) are the same, the only difference being the first loop step ( Figure 4 (c) and Figure 3 The first loop step ( Figure 3 (c) is different. In Figure 4In the illustrated embodiment, after entering the test mode, the first loop step is executed for the first time: the word line WL located in the first row of the memory array is selected as the first target word line. Then, the second sub-loop step is executed for the first target word line for the first time: the first target word line is turned on for the first time; a preset number of bit lines BL are turned on, and 0 is written to a preset number of memory cells 20 connected to the first target word line and the bit lines; after the first target word line is turned on for a first preset time, the sensing amplifier electrically connected to the bit lines BL is turned on; after the first target word line is turned on for a second preset time, the first target word line and the sensing amplifier electrically connected to the bit lines BL are turned off. Next, the second sub-loop step is executed for the first target word line for the second time: the first target word line is turned on for the second time; the next preset number of bit lines BL adjacent to the bit line BL that was turned on in the first execution of the second sub-loop step are turned on, and 0 is written into the next preset number of memory cells 20 connected to the first target word line and the next preset number of bit lines; after the first target word line is turned on for a first preset time delay, the sense amplifier electrically connected to the next preset number of bit lines BL is turned on; after the first target word line is turned on for a second preset time delay, the first target word line and the sense amplifier electrically connected to the next preset number of bit lines BL are turned off. This process is repeated until all memory cells 20 connected to the first target word line are filled with 0.

[0114] The first loop step is executed a second time: the word line WL located in the second row of the storage array is selected as the first target word line. Then, the second sub-loop step is executed multiple times, ensuring that all storage cells 20 electrically connected to the target word line complete the write operation to 0. The specific operation of executing the second sub-loop step multiple times is the same as the operation of executing the second sub-loop step multiple times during the first execution of the first loop step.

[0115] In other embodiments, the first loop step includes:

[0116] Select a word line WL as the first target word line and enable the first target word line;

[0117] Enable all the bit lines and write 0 to all the memory cells connected to the first target word line;

[0118] After the first target word line is turned on and after a first preset time delay, the sensing amplifier that is electrically connected to all the bit lines is turned on.

[0119] After the first target word line is turned on and delayed for a second preset time, the first target word line and the sensing amplifier electrically connected to all the bit lines are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step.

[0120] Appendix Figure 5 This is a schematic diagram of a test method for the third semiconductor structure in a specific embodiment of this application. Figure 5 Operations (a) and (b) in the text are related to Figure 3 Operations (a) and (b) are the same, the only difference being the first loop step ( Figure 5 (c) and Figure 3 The first loop step ( Figure 3 (c) is different. In Figure 5 In the illustrated embodiment, after entering the test mode, the first loop step is executed for the first time: the word line WL located in the first row of the memory array is selected as the first target word line, and the first target word line is turned on; all the bit lines BL are turned on, and 0 is written to all the memory cells 20 connected to the first target word line; after the first target word line is turned on for a first preset time, the sensing amplifier electrically connected to all the bit lines BL is turned on; after the first target word line is turned on for a second preset time, the first target word line and the sensing amplifier electrically connected to all the bit lines BL are turned off.

[0121] The first loop step is executed a second time: the word line WL located in the second row of the memory array is selected as the first target word line, and the first target word line is turned on; all bit lines BL are turned on, and 0 is written to all memory cells 20 connected to the first target word line; after a first preset time delay from the turn on of the first target word line, the sense amplifiers electrically connected to all bit lines BL are turned on; after a second preset time delay from the turn on of the first target word line, the first target word line and the sense amplifiers electrically connected to all bit lines BL are turned off. This process is repeated multiple times, ensuring that all word lines WL in the memory array complete the turn-on and turn-off operations, so that the memory array is filled with 0.

[0122] In some embodiments, the number of storage arrays is multiple; after all the storage cells in a storage array are filled with 0, the method further includes the following steps:

[0123] Refresh the storage array that is currently filled with 0s;

[0124] The first loop step is performed on the next storage array until all the storage cells in the next storage array are filled with 0.

[0125] like Figure 3 , Figure 4 and Figure 5 As shown, there are multiple storage arrays, and these arrays are arranged in parallel along the Z-axis. After all the storage cells in one of the storage arrays are filled with 0s, the test mode is exited (i.e.,...). Figure 3 (d) operation in Figure 4 (d) operation and Figure 4 (d) operation), and refresh the memory array that is already filled with 0s (i.e. Figure 3 Operation (e) in Figure 4 operation (e) in and Figure 4 (e) operation). Then, the test mode is performed again, executing the first loop step () on the next memory array. Figure 3 (c) operation in Figure 4 (c) operation and Figure 4 The test mode continues in step (c) until all the memory cells in the next memory array are filled with 0. After the next memory array is filled with 0, the test mode is exited, and a refresh operation is performed on the memory arrays that were filled with 0 in the test mode. This process continues until multiple memory arrays have completed the operation of filling with 0 through multiple iterations of the first loop step.

[0126] In some embodiments, after all the storage cells 20 in the storage array are filled with 0, the following steps are further included:

[0127] Read all the storage cells 20 in the storage array ( Figure 3 (f) operation in Figure 4 The (f) operation and Figure 4 (f) operation in the middle;

[0128] Determine whether the read values ​​of all the memory cells 20 are 0. If not, confirm that the word line WL and the bit line BL are electrically connected at the memory cell 20 where the read value is not 0.

[0129] In some embodiments, the specific steps for reading all the storage cells 20 in the storage array include:

[0130] The third loop step is executed multiple times until all the storage cells 20 in the storage array have been read. The third loop step includes:

[0131] Select a word line WL as the third target word line, and read all memory cells 20 connected to the third target word line;

[0132] After all the memory cells 20 connected to the third target word line have been read, the next word line WL adjacent to the third target word line is used as the third target word line for the next third loop step.

[0133] For example, after all the memory arrays have completed the operation of writing 0s by executing the first loop step multiple times, the third loop step is executed for the first time: the word line WL located in the first row of one of the memory arrays is selected as the third target word line, and all memory cells 20 connected to the target word line are read. Then, the third loop step is executed for the second time: the word line WL located in the second row of one of the memory arrays is selected as the third target word line, and all memory cells 20 connected to the target word line are read. This process is repeated row by row until all memory cells 20 in all the memory arrays have been read.

[0134] Since the value written to memory cell 20 during a write operation is 0, if the word line WL and the bit line BL are shorted, the leakage current generated by the shorting will be transmitted to the capacitor electrically connected to the bit line BL. During a read operation, the leakage current in the capacitor will be transmitted to the memory cell 20, which is electrically connected to both the shorted word line WL and the bit line BL, thus causing the read value of the memory cell 20 to become 1. Therefore, by determining whether the read values ​​of all memory cells 20 are 0, it can be confirmed whether the word line WL and the bit line BL at memory cell 20 are shorted.

[0135] According to other embodiments, this specific embodiment also provides a testing apparatus for semiconductor structures. Figure 6 This is a structural block diagram of a semiconductor structure testing apparatus according to a specific embodiment of this application. The semiconductor structure testing apparatus provided in this specific embodiment can be adopted... Figures 1-5 The method shown is used to test semiconductor structures. For example... Figures 1-6 As shown, the testing apparatus for the semiconductor structure includes:

[0136] The write module 61 is used to execute the following first loop step multiple times until all the memory cells in the memory array are filled with 0; the memory array includes multiple memory cells arranged in an array, multiple word lines arranged in parallel along a first direction, and multiple bit lines arranged in parallel along a second direction, the multiple bit lines being electrically connected to multiple sense amplifiers, the first direction and the second direction intersecting; the first loop step includes: selecting a word line as a first target word line and turning on the first target word line; after the first target word line is turned on for a first preset time, turning on the sense amplifier; after the first target word line is turned on for a second preset time, turning off the first target word line and the sense amplifier, and using the next word line adjacent to the first target word line as the first target word line for the next first loop step.

[0137] In some embodiments, the semiconductor structure testing apparatus further includes:

[0138] The refresh module 62 is used to refresh the storage array that has been filled with 0s.

[0139] In some embodiments, it also includes:

[0140] Read module 63 is used to read all the storage cells in the storage array;

[0141] The judgment module 64 is used to determine whether the read values ​​of all the memory cells are 0. If not, it is confirmed that the memory array has a defect of short circuit between the bit line and the word line.

[0142] The semiconductor structure testing device may further include a control module 60, which is connected to the write module 61, the refresh module 62, the read module 63, and the judgment module 64. The control module 60 may be a host computer, used to receive user operation instructions and control the write module 61, the refresh module 62, the read module 63, and the judgment module 64 to perform corresponding operations.

[0143] The semiconductor structure testing method and apparatus provided in this specific embodiment are implemented by writing 0s to all memory cells in the memory array, and using the voltage difference generated between the high potential of the word line and the low potential of the bit line when the word line is turned on to simulate the short circuit phenomenon between the word line and the bit line. In some embodiments of this application, the sensing amplifier is turned on after the target word line is turned on and delayed for a first preset time, and then turned off after the target word line is turned on and delayed for a second preset time. This prolongs the time from the turn-on of the target word line to the turn-on of the sensing amplifier and the time the target word line is in an active state. This ensures that once a short circuit occurs between the word line and the bit line, the sensing amplifier can fully detect the defect, improving the accuracy and efficiency of short circuit defect detection between the word line and the bit line.

[0144] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for testing semiconductor structures, characterized in that, Includes the following steps: A memory array is provided, comprising a plurality of memory cells arranged in an array, a plurality of word lines arranged in parallel along a first direction, and a plurality of bit lines arranged in parallel along a second direction, wherein the plurality of bit lines are electrically connected to a plurality of inductive amplifiers, and the first direction and the second direction intersect. The first loop step is executed repeatedly until all the memory cells in the memory array are filled with 0; The first loop step includes: Select a character line as the first target character line and enable the first target character line; Enable all the bit lines and write 0 to all the memory cells connected to the first target word line; The induction amplifier is activated after the first target word line is turned on and after a first preset time delay. After the first target word line is turned on and delayed for a second preset time, the first target word line and the induction amplifier are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step. Read all the storage cells in the storage array; Determine whether the read values ​​of all the memory cells are 0. If not, short-circuit the bit line and word line at the memory cell where the read value is not 0.

2. The method for testing semiconductor structures according to claim 1, characterized in that, The first loop step includes: Select a bitline as the target bitline and enable the target bitline; The first sub-loop step is executed sequentially for multiple of the aforementioned word lines; The target bit line is turned off, and the next bit line adjacent to the target bit line is used as the target bit line for the next first loop step. The first sub-loop step includes: Select a word line as the first target word line, enable the first target word line, and write 0 to the memory cell that is electrically connected to both the first target word line and the target bit line; After the first target word line is turned on and after a first preset time delay, the induction amplifier electrically connected to the target bit line is turned on. After the first target word line is turned on and delayed for a second preset time, the first target word line and the inductive amplifier electrically connected to the target bit line are turned off, and the next word line adjacent to the first target word line is used as the first target word line for the next first cycle step.

3. The method for testing semiconductor structures according to claim 1, characterized in that, The first loop step includes: Select a word line as the first target word line, and perform the second sub-loop step on the first target word line; After performing the second sub-loop step on the first target word line, the next word line adjacent to the first target word line is taken as the first target word line for the next first loop step; The second sub-loop step includes: Enable the first target word line; Enable several bit lines and write 0 to several memory cells connected to the first target word line and several bit lines; After the first target word line is turned on and after a first preset time delay, the sensing amplifier electrically connected to the plurality of bit lines is turned on. After the first target word line is turned on and after a second preset time delay, the first target word line and the sensing amplifier electrically connected to the plurality of bit lines are turned off.

4. The method for testing semiconductor structures according to claim 1, characterized in that, The first preset time is 10ns~400ns.

5. The method for testing semiconductor structures according to claim 1, characterized in that, The second preset time is 100ns~1000ns.

6. The method for testing semiconductor structures according to claim 1, characterized in that, The number of storage arrays is multiple; after all the storage cells in a storage array are filled with 0, the following steps are also included: Refresh the storage array that is currently filled with 0s; The first loop step is performed on the next storage array until all the storage cells in the next storage array are filled with 0.

7. The method for testing semiconductor structures according to claim 1, characterized in that, The specific steps for reading all the storage cells in the storage array include: The third loop step is executed multiple times until all the storage cells in the storage array have been read. The third loop step includes: Select a word line as the third target word line, and read all memory cells connected to the third target word line; After all memory cells connected to the third target word line have been read, the next word line adjacent to the third target word line is used as the third target word line for the next third loop step.

8. A testing apparatus for semiconductor structures, characterized in that, include: The write module is used to execute the following first loop step multiple times until all memory cells in the memory array are filled with 0; the memory array includes multiple memory cells arranged in an array, multiple word lines arranged in parallel along a first direction, and multiple bit lines arranged in parallel along a second direction, the multiple bit lines being electrically connected to multiple inductive amplifiers, and the first direction and the second direction intersecting; The first loop step includes: selecting a word line as a first target word line and turning on the first target word line; turning on all the bit lines and writing 0 to all the memory cells connected to the first target word line; turning on the sensing amplifier after a first preset time delay from when the first target word line is turned on; turning off the first target word line and the sensing amplifier after a second preset time delay from when the first target word line is turned on, and using the next word line adjacent to the first target word line as the first target word line for the next first loop step. The read module is used to read all the storage cells in the storage array; The judgment module is used to determine whether the read values ​​of all the memory cells are 0. If not, it confirms that the word line and the bit line at the memory cell where the read value is not 0 are electrically connected.

9. The semiconductor structure testing apparatus according to claim 8, characterized in that, The testing apparatus for the semiconductor structure also includes: A refresh module is used to refresh the storage array that has been filled with 0s.

10. The semiconductor structure testing apparatus according to claim 9, characterized in that, The first preset time is 10ns~400ns.

11. The semiconductor structure testing apparatus according to claim 9, characterized in that, The second preset time is 100ns~1000ns.

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