Testing method for semiconductor structure, semiconductor test structure and preparation method thereof

Abstract

The present invention relates to a testing method for a semiconductor structure, a semiconductor test structure and a preparation method thereof. The semiconductor test structure includes: a substrate including a bulk active region and an isolation region, the bulk active region having a first test terminal and a second test terminal; a dummy gate; a first dielectric layer; a first metal layer including a first test line and a second test line isolated from each other; a test contact pair including a first test contact and a second test contact, the first test terminal being electrically connected to the first test line through the first test contact, and the second test terminal being electrically connected to the second test line through the second test contact; a second dielectric layer; a dummy contact pair including a first dummy contact and a second dummy contact, the first dummy contact being electrically connected to the first test line, the second dummy contact being electrically connected to the second test line, and an orthographic projection of the dummy contact pair on the substrate and an orthographic projection of the dummy gate on the substrate having an overlapping part. The present invention can test whether a PID problem occurs in the contact structure.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a method for testing a semiconductor structure, a semiconductor test structure, and a preparation method thereof. Background Art

[0002] A dynamic random access memory (DRAM) is a commonly used semiconductor structure in electronic devices such as computers. A DRAM is composed of multiple memory cells, and each memory cell usually includes a transistor and a capacitor.

[0003] With the development of semiconductor technologies, low-power, high-density, and high-performance semiconductor memory devices have become a development trend, thus prompting the continuous miniaturization of memory cells. With the miniaturization of memory cells, the loading effect of plasma etching has become increasingly serious, and the problem of plasma induced damage (PID) has emerged.

[0004] The problem of PID has a greater impact on the contact structure. However, there is currently no relevant method to test whether the contact structure has the problem of PID. Summary of the Invention

[0005] Based on this, it is necessary to provide a method for testing a semiconductor structure, a semiconductor test structure, and a preparation method thereof for the problem in the prior art that it is impossible to test whether the contact structure has the problem of PID.

[0006] To achieve the above object, in a first aspect, the present invention provides a semiconductor test structure, which includes:

[0007] A substrate, including a bulk active region and an isolation region located outside the bulk active region, where the bulk active region has a first test terminal and a second test terminal;

[0008] A dummy gate, located on the surface of the isolation region;

[0009] A first dielectric layer, covering the substrate and the dummy gate;

[0010] A first metal layer, including a first test line and a second test line that are isolated from each other, where the first test line and the second test line are located on the first dielectric layer;

[0011] A test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact penetrate through the first dielectric layer respectively. The first test terminal is electrically connected to the first test line through the first test contact, and the second test terminal is electrically connected to the second test line through the second test contact;

[0012] A second dielectric layer is located on the first metal layer and the first dielectric layer;

[0013] A dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact and the second dummy contact penetrate through at least the second dielectric layer. The first dummy contact is electrically connected to the first test line, the second dummy contact is electrically connected to the second test line, and the orthographic projection of the dummy contact pair on the substrate and the orthographic projection of the dummy gate on the substrate have an overlapping part.

[0014] In one embodiment, the semiconductor test structure further includes:

[0015] A second metal layer is disposed on the dummy gate, and the first dielectric layer coats the second metal layer.

[0016] In one embodiment, the horizontal distance between the first dummy contact and the first test contact is equal to the horizontal distance between the second dummy contact and the second test contact.

[0017] In one embodiment, the horizontal distance between the first dummy contact and the second dummy contact is equal to the horizontal distance between the first test contact and the second test contact.

[0018] In one embodiment, the semiconductor test structure includes two dummy gates and two dummy contact pairs. The bulk active region is located between the two dummy gates, and the orthographic projections of the two dummy contact pairs on the substrate and the orthographic projections of the two dummy gates on the substrate have overlapping parts respectively.

[0019] In one embodiment, the distances between the two dummy gates and the bulk active region are equal.

[0020] In one embodiment, the semiconductor test structure further includes:

[0021] An insulating layer is located between the dummy gate and the substrate.

[0022] In a second aspect, the present invention further provides a method for manufacturing a semiconductor test structure. The method includes:

[0023] Providing a substrate, the substrate includes a bulk active region and an isolation region located outside the bulk active region. The bulk active region has a first test terminal and a second test terminal;

[0024] A dummy gate, a first dielectric layer, a test contact pair, and a first metal layer are formed on the substrate. The dummy gate is located on the surface of the isolation region. The first dielectric layer covers the substrate and the dummy gate. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate through the first dielectric layer. The first metal layer includes a first test line and a second test line that are isolated from each other. The first test line and the second test line are located on the surface of the first dielectric layer. The first test terminal is electrically connected to the first test line through the first test contact. The second test terminal is electrically connected to the second test line through the second test contact;

[0025] A second dielectric layer and a dummy contact pair that at least penetrates through the second dielectric layer are sequentially formed. The second dielectric layer is located on the first metal layer and the first dielectric layer. The dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact is electrically connected to the first test line. The second dummy contact is electrically connected to the second test line. And the orthographic projection of the dummy contact pair on the substrate and the orthographic projection of the dummy gate on the substrate have an overlapping part.

[0026] In one embodiment, the steps of forming a dummy gate, a first dielectric layer, a test contact pair, and a first metal layer on the substrate include:

[0027] A first dielectric layer and a dummy gate are formed on the substrate, and the first dielectric layer covers the dummy gate;

[0028] A first through hole extending to the first test terminal and a second through hole extending to the second test terminal are formed in the first dielectric layer;

[0029] A first metal material is deposited. The first metal material forms a first test contact in the first through hole, forms a second test contact in the second through hole, and forms a first metal layer on the first dielectric layer.

[0030] In one embodiment, the method further includes:

[0031] A third through hole extending to the dummy gate is formed in the first dielectric layer;

[0032] A second metal layer is formed in the third through hole;

[0033] A third dielectric layer is formed on the second metal layer and the first dielectric layer. The first test contact and the second test contact respectively penetrate through the third dielectric layer;

[0034] Wherein, the first metal layer is located on the third dielectric layer, and the second dielectric layer covers the first metal layer and the third dielectric layer.

[0035] In a third aspect, the present invention further provides a method for testing a semiconductor structure, the method comprising:

[0036] Providing a semiconductor structure, the semiconductor structure comprising a chip region and a test region, the test region being provided with the semiconductor test structure according to any one of claims 1-7, the chip region being provided with a gate and a contact structure, the gate and the dummy gate being formed simultaneously, and the contact structure and the dummy contact pair being formed simultaneously;

[0037] Testing the sheet resistance of the bulk active region through the first test line and the second test line;

[0038] Determining whether the contact structure penetrates the first dielectric layer according to the sheet resistance of the bulk active region.

[0039] In one embodiment, the step of determining whether the contact structure penetrates the first dielectric layer according to the sheet resistance of the bulk active region comprises:

[0040] If the sheet resistance of the bulk active region is less than a set resistance, it is determined that the contact structure penetrates the first dielectric layer;

[0041] If the sheet resistance of the bulk active region is greater than or equal to the set resistance, it is determined that the contact structure does not penetrate the first dielectric layer.

[0042] In one embodiment, the step of providing a semiconductor structure comprises:

[0043] Providing a substrate, the substrate comprising a chip region and a test region, the test region comprising a bulk active region and an isolation region surrounding the bulk active region, the bulk active region having a first test end and a second test end;

[0044] Forming a gate, a dummy gate and a first dielectric layer on the substrate, the first dielectric layer covering the gate and the dummy gate;

[0045] Opening a first through hole extending to the first test end and a second through hole extending to the second test end in the first dielectric layer;

[0046] Depositing a first metal material, the first metal material forming a first test contact in the first through hole, the first metal material forming a second test contact in the second through hole, and the first metal material forming a first metal layer on the first dielectric layer;

[0047] A second dielectric layer is formed on the first metal layer and the first dielectric layer;

[0048] A contact structure and a dummy contact pair are formed simultaneously. The dummy contact pair includes a first dummy contact and a second dummy contact. The contact structure, the first dummy contact, and the second dummy contact penetrate at least the second dielectric layer.

[0049] In one embodiment, a horizontal distance between the first dummy contact and the first test contact is equal to a horizontal distance between the second dummy contact and the second test contact.

[0050] In one embodiment, the semiconductor structure includes two of the dummy gates and two of the dummy contact pairs. The bulk active region is located between the two dummy gates. Orthogonal projections of the two dummy contact pairs on the substrate are respectively located within orthogonal projections of the two dummy gates on the substrate.

[0051] The test method of the semiconductor structure, the semiconductor test structure, and the manufacturing method thereof according to the present invention have the following beneficial effects:

[0052] The semiconductor test structure of the present invention includes a substrate, a dummy gate, a first dielectric layer, a first metal layer, a test contact pair, a second dielectric layer, and a dummy contact pair. The substrate includes a bulk active region and an isolation region located outside the bulk active region. The bulk active region has a first test terminal and a second test terminal. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate the first dielectric layer on the substrate. The first metal layer on the first dielectric layer includes a first test line and a second test line that are isolated from each other. The first test line is electrically connected to the first test terminal through the first test contact, and the second test line is electrically connected to the second test terminal through the second test contact. Therefore, through the first test line and the second test line, the resistance of the bulk active region between the first test terminal and the second test terminal can be measured. A dummy gate is provided on the surface of the isolation region, and the first dielectric layer covers the dummy gate. A second dielectric layer is provided on the first dielectric layer and the first metal layer. The dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact and the second dummy contact at least penetrate the second dielectric layer. The first dummy contact is electrically connected to the first test line, and the second dummy contact is electrically connected to the second test line. And the orthographic projection of the dummy contact pair on the substrate and the orthographic projection of the dummy gate on the substrate have an overlapping part. If the dummy contact pair also penetrates the first dielectric layer, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, in addition to the bulk active region, the first test terminal and the second test terminal are also connected through the dummy contact pair and the dummy gate. In this way, the resistance measured between the first test terminal and the second test terminal through the first test line and the second test line will be greatly reduced. If the dummy contact pair does not penetrate the first dielectric layer, the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test terminal and the second test terminal. In this way, the resistance measured between the first test terminal and the second test terminal through the first test line and the second test line is relatively large. Therefore, according to the magnitude of the resistance measured by the first test line and the second test line, the depth condition of the dummy contact pair can be determined, so as to determine whether there is a PID problem in the contact structure formed simultaneously with the dummy contact pair;

[0053] Method for preparing semiconductor test structure of the present invention: First, provide a substrate, and form a dummy gate, a first dielectric layer, a test contact pair, and a first metal layer on the substrate. The substrate includes a bulk active region and an isolation region located outside the bulk active region. The dummy gate is located on the surface of the isolation region. The first dielectric layer covers the substrate and the dummy gate. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate the first dielectric layer. The first metal layer includes a first test line and a second test line that are isolated from each other. The first test line and the second test line are located on the surface of the first dielectric layer. Then, form a second dielectric layer and a dummy contact pair that at least penetrates the second dielectric layer in sequence. The second dielectric layer is located on the first metal layer and the first dielectric layer, thereby forming a semiconductor test structure. The bulk active region has a first test end and a second test end. The first test end is electrically connected to the first test line through the first test contact, and the second test end is electrically connected to the second test line through the second test contact. Through the first test line and the second test line, the resistance of the bulk active region between the first test end and the second test end can be measured. The dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact is electrically connected to the first test line, and the second dummy contact is electrically connected to the second test line. The orthographic projection of the dummy contact pair on the substrate has an overlapping part with the orthographic projection of the dummy gate on the substrate. If the dummy contact pair also penetrates the first dielectric layer, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, in addition to the bulk active region, the first test end and the second test end are also connected through the dummy contact pair and the dummy gate. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line will be greatly reduced. If the dummy contact pair does not penetrate the first dielectric layer, the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test end and the second test end. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line is relatively large. Therefore, according to the resistance value measured by the first test line and the second test line, the depth of the dummy contact pair can be determined, so as to determine whether there is a PID problem in the contact structure formed simultaneously with the dummy contact pair;

[0054] Testing method for semiconductor structure of the present invention. First, a semiconductor structure is provided. The semiconductor structure includes a chip region and a test region. The test region is provided with the above-mentioned semiconductor test structure. The chip region is provided with a gate and a contact structure. The gate and the dummy gate are formed simultaneously. The contact structure and the dummy contact pair are formed simultaneously. If the contact structure also penetrates the first dielectric layer, the dummy contact pair also penetrates the first dielectric layer and is electrically connected to the dummy gate, that is, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, between the first test terminal and the second test terminal, in addition to the bulk active region, they are also connected through the dummy contact degree and the dummy gate. In this way, the resistance between the first test terminal and the second test terminal measured through the first test line and the second test line will be greatly reduced. If the contact structure does not penetrate the first dielectric layer, the dummy contact pair does not penetrate the first dielectric layer, and the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test terminal and the second test terminal. In this way, the resistance between the first test terminal and the second test terminal measured through the first test line and the second test line is relatively large. Therefore, by testing the sheet resistance of the bulk active region through the first test line and the second test line, it is possible to determine whether the contact structure penetrates the first dielectric layer according to the sheet resistance of the bulk active region, and further determine whether there is a PID problem with the contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0056] Figure 1 Top view of a semiconductor test structure provided in an embodiment;

[0057] Figure 2 For an embodiment provided Figure 1 Cross-sectional view of the section intercepted by line AA in;

[0058] Figure 3 For an embodiment provided Figure 1 Cross-sectional view of the section intercepted by line BB in;

[0059] Figure 4 Flowchart of the preparation method of a semiconductor test structure provided in an embodiment;

[0060] Figure 5 Cross-sectional schematic diagram of the structure obtained in step 401 in the preparation method of a semiconductor test structure provided in an embodiment;

[0061] Figure 6Schematic cross-sectional view of the structure obtained in step 402 in the preparation method of a semiconductor test structure provided in an embodiment;

[0062] Figure 7 Schematic cross-sectional view of the structure obtained in step 403 in the preparation method of a semiconductor test structure provided in an embodiment;

[0063] Figure 8 Flowchart of step 402 in the preparation method of a semiconductor test structure provided in an embodiment;

[0064] Figure 9 Schematic cross-sectional view of the structure obtained in step 801 in the preparation method of a semiconductor test structure provided in an embodiment;

[0065] Figure 10 Schematic cross-sectional view of the structure obtained in step 802 in the preparation method of a semiconductor test structure provided in an embodiment;

[0066] Figure 11 Schematic cross-sectional view of the structure obtained in step 803 in the preparation method of a semiconductor test structure provided in an embodiment;

[0067] Figure 12 Flowchart of step 403 in the preparation method of a semiconductor test structure provided in an embodiment;

[0068] Figure 13 Flowchart of the preparation method of a semiconductor test structure provided in an embodiment;

[0069] Figure 14 Flowchart of step 1301 in the preparation method of a semiconductor test structure provided in an embodiment;

[0070] Figure 15 Flowchart of step 1302 in the preparation method of a semiconductor test structure provided in an embodiment;

[0071] Figure 16 Schematic cross-sectional view of the structure obtained in step 1501 in the preparation method of a semiconductor test structure provided in an embodiment;

[0072] Figure 17 Schematic cross-sectional view of the structure obtained in step 1502 in the preparation method of a semiconductor test structure provided in an embodiment;

[0073] Figure 18 Schematic cross-sectional view of the structure obtained in step 1303 in the preparation method of a semiconductor test structure provided in an embodiment;

[0074] Figure 19 Flowchart of the preparation method of a semiconductor test structure provided in an embodiment;

[0075] Figure 20 It is a cross-sectional schematic view of the structure obtained in step 1901 in the manufacturing method of a semiconductor test structure provided in an embodiment;

[0076] Figure 21 It is a cross-sectional schematic view of the structure obtained in step 1902 in the manufacturing method of a semiconductor test structure provided in an embodiment;

[0077] Figure 22 It is a flowchart of the testing method of a semiconductor structure provided in an embodiment;

[0078] Figure 23 It is a flowchart of step 2201 in the testing method of a semiconductor structure provided in an embodiment.

[0079] Description of reference numerals:

[0080] 10. Substrate, 11. Bulk active region, 12. Isolation region;

[0081] 20. dummy gate;

[0082] 31. First dielectric layer, 311. First via hole and second via hole, 312. Third via hole, 32. Second dielectric layer, 33. Third dielectric layer, 331. Fifth via hole;

[0083] 40. Metal material layer, 41. First metal layer, 411. First test line, 412. Second test line, 42. Second metal layer;

[0084] 50. Test contact pair, 51. First test contact, 52. Second test contact;

[0085] 60. dummy contact pair, 61. First dummy contact, 62. Second dummy contact;

[0086] 70. Insulating layer. Detailed implementation manners

[0087] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0089] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be denoted as the second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0090] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as a 90-degree rotation or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0091] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0092] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown, for example, due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations, for example, due to manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0093] A DRAM is composed of a plurality of memory cells, and each memory cell generally includes a transistor and a capacitor. As the memory cells are miniaturized, the capacitor becomes longer and longer, and the contact structure arranged on the same layer as the capacitor also becomes longer and longer. Currently, the length of the contact is as high as 1600 nm, the aspect ratio is greater than 50, and the loading effect brought by plasma etching during the formation process is relatively serious, resulting in the problem of Plasma Induced Damage (PID for short). Due to the large number and high density of contacts, the high-energy ion bombardment during the etching process of the contacts will bring serious PID problems, ultimately leading to performance shift or even failure of the device.

[0094] In the related art, an Electro-Static Discharge (ESD) protection circuit can be designed in a DRAM chip to release the charge of the bulk part. A protect diode can also be designed on the test key structure to release a single charge. However, due to the limitation of the chip area, the above methods cannot effectively release the charge, and the PID problem still occurs. However, there is currently no relevant method to detect whether a relatively serious PID problem has occurred.

[0095] In view of the above problems, embodiments of the present invention provide a method for testing a semiconductor structure, a semiconductor test structure, and a preparation method thereof. The semiconductor test structure includes a substrate, a dummy gate formed simultaneously with a gate, and a dummy contact pair formed simultaneously with a contact structure. The orthographic projection of the dummy contact pair on the substrate overlaps with the orthographic projection of the dummy gate on the substrate. By detecting whether there is an electrical connection between the dummy contact pair and the dummy gate, the punchthrough condition of the contact structure can be detected, and further, it can be analyzed whether a relatively serious PID problem occurs and causes a shift in device performance.

[0096] The semiconductor test structure further includes a first dielectric layer, a first metal layer, a test contact pair, and a second dielectric layer. The substrate includes a bulk active region and an isolation region located outside the bulk active region. The bulk active region has a first test end and a second test end. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate the first dielectric layer on the substrate. The first metal layer on the first dielectric layer includes a first test line and a second test line that are isolated from each other. The first test line is electrically connected to the first test end through the first test contact, and the second test line is electrically connected to the second test end through the second test contact. The resistance between the first test end and the second test end can be measured through the first test line and the second test line.

[0097] If the dummy contact pair also penetrates the first dielectric layer, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, in addition to the bulk active region, the first test end and the second test end are also connected through the dummy contact pair and the dummy gate. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line will decrease significantly. If the dummy contact pair does not penetrate the first dielectric layer, the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test end and the second test end. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line is relatively large. Therefore, by testing the sheet resistance of the bulk active region through the first test line and the second test line, it can be determined whether the dummy contact pair penetrates the first dielectric layer, thereby determining whether the contact structure penetrates the first dielectric layer, and further analyzing whether a relatively serious PID problem occurs in the contact structure and causes a shift in device performance.

[0098] Figure 1 is a top view of the semiconductor test structure provided by the embodiment of the present invention, Figure 2 is provided by the embodiment of the present invention Figure 1 is a cross-sectional view of the section intercepted by line AA in Figure 3 is provided by the embodiment of the present invention Figure 1 is a cross-sectional view of the section intercepted by line BB in Figure 1 - 3, the present invention provides a semiconductor test structure, which includes a substrate 10, a dummy gate 20, a first dielectric layer 31, a first metal layer 41, a test contact pair 50, a second dielectric layer 32, and a dummy contact pair 60. The substrate 10 includes a bulk active region 11 and an isolation region 12 located outside the bulk active region 11. The bulk active region 11 has a first test end and a second test end (not shown in the figure). The dummy gate 20 is located on the surface of the isolation region 12. The first dielectric layer 31 covers the substrate 10 and the dummy gate 20. The first metal layer 41 includes a mutually isolated first test line 411 and a second test line 412, and the first test line 411 and the second test line 412 are located on the first dielectric layer 31. The test contact pair 50 includes a first test contact 51 and a second test contact 52. The first test contact 51 and the second test contact 52 respectively penetrate the first dielectric layer 31. The first test end is electrically connected to the first test line 411 through the first test contact 51, and the second test end is electrically connected to the second test line 412 through the second test contact 52. The second dielectric layer 32 is located on the first metal layer 41 and the first dielectric layer 31. The dummy contact pair 60 includes a first dummy contact 61 and a second dummy contact 62. The first dummy contact 61 and the second dummy contact 62 at least penetrate the second dielectric layer 32. The first dummy contact 61 is electrically connected to the first test line 411, and the second dummy contact 62 is electrically connected to the second test line 412. And the orthographic projection of the dummy contact pair 60 on the substrate 10 and the orthographic projection of the dummy gate 20 on the substrate 10 have an overlapping part.

[0099] Wherein, a shallow trench isolation structure (Shallow Trench Isolation, abbreviated as STI) may be formed in the substrate 10, and the shallow trench isolation structure may isolate a plurality of spaced-apart active regions (Active Area, abbreviated as AA) in the substrate. The bulk active region 11 is an AA isolated by the STI, and the isolation region 12 is the STI.

[0100] The dummy gate 20 is a structure formed simultaneously with the gate. The difference between the dummy gate 20 and the gate is that the gate is formed on the active region (Active Area, abbreviated as AA) and can form a transistor structure with the source region and the drain region; while the dummy gate 20 is formed on the shallow trench isolation structure (Shallow Trench Isolation, abbreviated as STI) and is a separate structure.

[0101] The first dielectric layer 31 respectively wraps outside the gate and the dummy gate 20, separating the gate and the dummy gate 20. The second dielectric layer 32 respectively wraps outside the contact structure and the dummy contact pair 60, separating the contact structure and the dummy contact pair 60. The first metal layer 41 is located between the first dielectric layer 31 and the second dielectric layer 32 to transfer the contact structure.

[0102] The bulk active region 11 has a first test terminal and a second test terminal, and the sheet resistance of the bulk active region 11 can be tested through the first test terminal and the second test terminal. The first test contact 51 and the second test contact 52 in the test contact pair 50 respectively penetrate through the first dielectric layer 31. The first metal layer 41 on the first dielectric layer 31 includes a first test line 411 and a second test line 412 that are isolated from each other. The first test line 411 is electrically connected to the first test terminal through the first test contact 51, and the second test line 412 is electrically connected to the second test terminal through the second test contact 52, so that the test of the sheet resistance can be led out from the bulk active region 11 to the first metal layer 41.

[0103] The dummy contact pair 60 is a structure formed simultaneously with the contact structure. The difference between the dummy contact pair 60 and the contact structure is that the contact structure is located above the gate, and the orthographic projection of the contact structure on the substrate 10 and the orthographic projection of the gate on the substrate 10 have an overlapping part; while the dummy contact pair 60 is located above the dummy gate 20, and the orthographic projection of the dummy contact pair 60 on the substrate 10 and the orthographic projection of the dummy gate 20 on the substrate 10 have an overlapping part.

[0104] The dummy contact pair 60 includes a first dummy contact 61 and a second dummy contact 62. The orthographic projections of the first dummy contact 61 and the second dummy contact 62 on the substrate 10 respectively have an overlapping part with the orthographic projection of the dummy gate 20 on the substrate 10. If punch through occurs in the dummy contact pair 60, the first dummy contact 61 and the second dummy contact 62 respectively contact the dummy gate 20, so as to achieve electrical connection through the dummy gate 20. At this time, the measured sheet resistance is much smaller than the resistance of the bulk active region 10. For example, the resistance of the bulk active region 10 is 20 to 50 times the measured sheet resistance. It is possible to judge whether punch through occurs in the dummy contact pair 60 according to the size of the measured sheet resistance, so as to judge whether punch through occurs in the contact structure, and further analyze whether a relatively serious PID problem occurs and causes a shift in device performance.

[0105] If punch through does not occur in the contact structure, the contact structure extends to the first metal layer 41 and is transferred to the source region or the drain region through the first metal layer 41, and will not be electrically connected to the gate. If punch through occurs in the contact structure, the contact structure will penetrate below the first metal layer 41 and be electrically connected to the gate. At this time, the contact structure is also transferred to the source region or the drain region through the first metal layer 41, resulting in electrical connection between the source region or the drain region and the gate, affecting the function realization of the transistor.

[0106] The above semiconductor test structure includes a substrate, a dummy gate, a first dielectric layer, a first metal layer, a test contact pair, a second dielectric layer, and a dummy contact pair. The substrate includes a bulk active region and an isolation region located outside the bulk active region. The bulk active region has a first test end and a second test end. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate the first dielectric layer on the substrate. The first metal layer on the first dielectric layer includes a first test line and a second test line that are isolated from each other. The first test line is electrically connected to the first test end through the first test contact, and the second test line is electrically connected to the second test end through the second test contact. Therefore, through the first test line and the second test line, the resistance of the bulk active region between the first test end and the second test end can be measured. A dummy gate is provided on the surface of the isolation region, and the first dielectric layer covers the dummy gate. A second dielectric layer is provided on the first dielectric layer and the first metal layer. The dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact and the second dummy contact penetrate at least the second dielectric layer. The first dummy contact is electrically connected to the first test line, and the second dummy contact is electrically connected to the second test line. And the orthographic projection of the dummy contact pair on the substrate and the orthographic projection of the dummy gate on the substrate have an overlapping part. If the dummy contact pair also penetrates the first dielectric layer, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, in addition to the bulk active region, the first test end and the second test end are also connected through the dummy contact pair and the dummy gate. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line will be greatly reduced. If the dummy contact pair does not penetrate the first dielectric layer, the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test end and the second test end. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line is relatively large. Therefore, according to the resistance value measured by the first test line and the second test line, the depth condition of the dummy contact pair can be determined, so as to determine whether there is a problem of PID in the contact structure formed simultaneously with the dummy contact pair.

[0107] In some embodiments, as Figure 1 shown, the horizontal distance a between the first dummy contact 61 and the first test contact 51 is equal to the horizontal distance b between the second dummy contact 62 and the second test contact 52.

[0108] In the above embodiment, the horizontal distance a between the first dummy contact 61 and the first test contact 51 is equal to the horizontal distance b between the second dummy contact 62 and the second test contact 52, which is convenient for calculating the resistance value measured by the first test line and the second test line when the contact structure undergoes punch through, so as to judge whether the contact structure undergoes punch through according to the resistance value measured by the first test line and the second test line.

[0109] In some embodiments, as Figure 1As shown, the horizontal distance c between the first pseudo-contact 61 and the second pseudo-contact 62 is equal to the horizontal distance d between the first test contact 51 and the second test contact 52.

[0110] In the above embodiment, the horizontal distance c between the first pseudo-contact 61 and the second pseudo-contact 62 is equal to the horizontal distance d between the first test contact 51 and the second test contact 52, which is convenient for calculating the resistance values measured by the first test line and the second test line when the contact structure undergoes punch through, so as to determine whether the contact structure undergoes punch through according to the resistance values measured by the first test line and the second test line.

[0111] In some embodiments, as Figure 1 shown, the semiconductor test structure includes two pseudo-gates 20 and two pseudo-contact pairs 60. The bulk active region 11 is located between the two pseudo-gates 20. The positive projections of the two pseudo-contact pairs 60 on the substrate 10 respectively have overlapping portions with the positive projections of the two pseudo-gates 20 on the substrate 10.

[0112] Among them, the two pseudo-gates 20 and the two pseudo-contact pairs 60 correspond one by one. The positive projection of each pseudo-contact pair 60 on the substrate 10 has an overlapping portion with the positive projection of the corresponding pseudo-gate 20 on the substrate 10.

[0113] In the above embodiment, the numbers of the pseudo-gate 20 and the pseudo-contact pair 60 are both two. The resistance between the first test terminal and the second test terminal measured by the first test line and the second test line when the pseudo-contact pair 60 penetrates the first dielectric layer 31 can be further reduced, and it can be more obvious to identify whether the contact structure has undergone punch through. Moreover, the two pseudo-gates 20 are located on both sides of the bulk active region 11, which is convenient for calculating the resistance values measured by the first test line and the second test line when the contact structure undergoes punch through, so as to determine whether the contact structure undergoes punch through according to the resistance values measured by the first test line and the second test line.

[0114] In some embodiments, as Figure 1 shown, the distances e between the two pseudo-gates 20 and the bulk active region 11 are equal.

[0115] In the above embodiment, the distances e between the two pseudo-gates 20 and the bulk active region 11 are equal, and the two pseudo-gates 20 are symmetrically arranged with respect to the bulk active region 11, which is convenient for calculating the resistance values measured by the first test line and the second test line when the contact structure undergoes punch through, so as to determine whether the contact structure undergoes punch through according to the resistance values measured by the first test line and the second test line.

[0116] In some embodiments, asFigure 2 As shown, the semiconductor test structure further includes a second metal layer 42, the second metal layer 42 is disposed on the dummy gate 20, and the first dielectric layer 31 coats the second metal layer 42.

[0117] In the above embodiment, a second metal layer 42 is added on the dummy gate 20, and the second metal layer 42 is higher than the gate. In this way, when the contact structure penetrates to be electrically connected to the gate, it can be ensured that the dummy contact pair 60 penetrates to be electrically connected to the second metal layer 42 and the dummy gate. According to the resistance measured by the first test line and the second test line, it is certain that punch through of the contact structure can be identified. At the same time, the second metal layer 42 can further reduce the resistance measured by the first test line and the second test line, and it can be more obvious to identify whether punch through of the contact structure has occurred.

[0118] Exemplarily, the orthographic projection of the second metal layer 42 on the substrate 10 coincides with the orthographic projection of the second metal layer 42 on the substrate 10.

[0119] In some embodiments, as Figure 2 shown, the semiconductor test structure further includes an insulating layer 70, and the insulating layer 70 is located between the dummy gate 20 and the substrate 10.

[0120] In the above embodiment, an insulating layer 70 is added between the substrate 10 and the dummy gate 20, which can separate the dummy gate 20 from the substrate 10, avoid the electrical connection between the dummy gate 20 and the substrate 10 from affecting the device performance, and will not affect the original device.

[0121] Exemplarily, the substrate 10 may be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Again, the substrate may be a layered substrate including, for example, Si / SiGe, Si / SiC, Silicon On Insulator (SOI for short), or silicon germanium on insulator.

[0122] The substrate 10 can be N-type or P-type. When the substrate 10 is N-type, P-type ions can be implanted in the active region to form the source region and the drain region, and then together with the gate on the active region, a Positive-channel Metal Oxide Semiconductor (PMOS) device is formed. Among them, the P-type ions can include but are not limited to any one or several of Boron (B) ions, Magnesium (Mg) ions, Indium (In) ions, etc. When the substrate 10 is P-type, N-type ions can be implanted in the active region to form the source region and the drain region, and then together with the gate on the active region, a Negative channel Metal Oxide Semiconductor (NMOS) device is formed. Among them, the N-type ions can include but are not limited to one or several of Phosphorus (P) ions, Arsenic (As) ions, Antimony (Sb) ions.

[0123] The gate and the dummy gate 20 can include but are not limited to any one or several of a Titanium nitride (TiN) layer, a Titanium (Ti) layer, a Tungsten silicide (Si 2 W) layer, and a Tungsten (W) layer, etc.

[0124] The first dielectric layer 31 and the second dielectric layer 32 include but are not limited to at least one of a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), and a silicon oxynitride layer (SiON).

[0125] The materials of the first metal layer 41, the second metal layer 42, the test contact pair 50, the dummy contact pair 60, and the contact structure can include but are not limited to metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0126] The insulating layer 70 can be formed of a material with a high-k dielectric constant, such as silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide (Ta2 O 5 ) or titanium oxide (TiO 2 ) or strontium titanate (SrTiO 3 ).

[0127] Based on the same inventive concept, please refer to Figure 4 , the present invention further provides a method for preparing a semiconductor test structure, the preparation method comprising the following steps:

[0128] Step 401, providing a substrate.

[0129] Wherein, the substrate includes a bulk active region and an isolation region located outside the bulk active region, and the bulk active region has a first test terminal and a second test terminal.

[0130] Figure 5 FIG. is a cross-sectional schematic view of the structure obtained in Step 401 of the method for preparing a semiconductor test structure provided by an embodiment of the present invention. Please refer to Figure 5 , the substrate 10 includes a bulk active region 11 and an isolation region 12, and the isolation region 12 is located outside the bulk active region 11.

[0131] Step 402, forming a dummy gate, a first dielectric layer, a test contact pair, and a first metal layer on the substrate.

[0132] Wherein, the dummy gate is located on the surface of the isolation region, the first dielectric layer covers the substrate and the dummy gate, the test contact pair includes a first test contact and a second test contact, the first test contact and the second test contact respectively penetrate through the first dielectric layer, the first metal layer includes a first test line and a second test line that are isolated from each other, the first test line and the second test line are located on the surface of the first dielectric layer, the first test terminal is electrically connected to the first test line through the first test contact, and the second test terminal is electrically connected to the second test line through the second test contact.

[0133] Figure 6 FIG. is a cross-sectional schematic view of the structure obtained in Step 402 of the method for preparing a semiconductor test structure provided by an embodiment of the present invention. Please refer to Figure 6 , a dummy gate 20, a first dielectric layer 31, a test contact pair 50, and a first metal layer 41 are formed on the substrate 10, the dummy gate 20 is located on the isolation region 12, the first dielectric layer 31 is located on the region of the substrate 10 except the dummy gate 20 and covers the dummy gate 20, the test contact pair 50 penetrates through the first dielectric layer 31, and the first metal layer 41 is located on the first dielectric layer 31 and is electrically connected to the test contact pair 50.

[0134] Step 403, sequentially forming a second dielectric layer and a dummy contact pair that at least penetrates through the second dielectric layer.

[0135] Among them, the second dielectric layer is located on the first metal layer and the first dielectric layer. The pseudo-contact pair includes a first pseudo-contact and a second pseudo-contact. The first pseudo-contact is electrically connected to the first test line, and the second pseudo-contact is electrically connected to the second test line. Moreover, the orthographic projection of the pseudo-contact pair on the substrate and the orthographic projection of the pseudo-gate on the substrate have an overlapping part.

[0136] Figure 7 It is a cross-sectional schematic diagram of the structure obtained in step 403 in the manufacturing method of the semiconductor test structure provided by the embodiment of the present invention. Please refer to Figure 7 , a second dielectric layer 32 and a pseudo-contact pair 60 are formed on the first metal layer 41. The pseudo-contact pair 60 at least penetrates through the second dielectric layer 32 and is electrically connected to the first metal layer 41. Moreover, the orthographic projection of the pseudo-contact pair 60 on the substrate 10 and the orthographic projection of the pseudo-gate 20 on the substrate 10 have an overlapping part.

[0137] The preparation method of the above semiconductor test structure is as follows: First, a substrate is provided, and a dummy gate, a first dielectric layer, a test contact pair, and a first metal layer are formed on the substrate. The substrate includes a bulk active region and an isolation region located outside the bulk active region. The dummy gate is located on the surface of the isolation region. The first dielectric layer covers the substrate and the dummy gate. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate the first dielectric layer. The first metal layer includes a first test line and a second test line that are isolated from each other. The first test line and the second test line are located on the surface of the first dielectric layer. Then, a second dielectric layer and a dummy contact pair that at least penetrates the second dielectric layer are formed in sequence. The second dielectric layer is located on the first metal layer and the first dielectric layer, thereby forming a semiconductor test structure. The bulk active region has a first test end and a second test end. The first test end is electrically connected to the first test line through the first test contact, and the second test end is electrically connected to the second test line through the second test contact. Through the first test line and the second test line, the resistance of the bulk active region between the first test end and the second test end can be measured. The dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact is electrically connected to the first test line, and the second dummy contact is electrically connected to the second test line. The orthographic projection of the dummy contact pair on the substrate has an overlapping part with the orthographic projection of the dummy gate on the substrate. If the dummy contact pair also penetrates the first dielectric layer, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, in addition to the bulk active region, the first test end and the second test end are also connected through the dummy contact pair and the dummy gate. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line will be greatly reduced. If the dummy contact pair does not penetrate the first dielectric layer, the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test end and the second test end. In this way, the resistance measured between the first test end and the second test end through the first test line and the second test line is relatively large. Therefore, according to the resistance value measured by the first test line and the second test line, the depth of the dummy contact pair can be determined, and thus whether there is a PID problem in the contact structure formed simultaneously with the dummy contact pair can be determined.

[0138] In some embodiments, referring to Figure 8 , S402 includes the following steps:

[0139] Step 801: Form a first dielectric layer and a dummy gate on the substrate, and the first dielectric layer covers the dummy gate.

[0140] Figure 9 FIG. is a cross-sectional schematic diagram of the structure obtained in step 801 in the preparation method of the semiconductor test structure provided by the embodiment of the present invention. Referring to Figure 9 , a first dielectric layer 31 and a dummy gate 20 are formed on the substrate 10, and the first dielectric layer 31 covers the dummy gate 20.

[0141] Step 802: Form a first through hole extending to the first test end and a second through hole extending to the second test end in the first dielectric layer.

[0142] Figure 10 It is a cross-sectional schematic diagram of the structure obtained in step 802 of the preparation method of the semiconductor test structure provided by the embodiment of the present invention. Please refer to Figure 10 , at least a first through hole extending to the bulk active region 11 and a second through hole 311 are formed in the first dielectric layer 31.

[0143] Step 803: Deposit a first metal material. The first metal material forms a first test contact in the first through hole, the first metal material forms a second test contact in the second through hole, and the first metal material forms a first metal layer on the first dielectric layer.

[0144] Figure 11 It is a cross-sectional schematic diagram of the structure obtained in step 803 of the preparation method of the semiconductor test structure provided by the embodiment of the present invention. Please refer to Figure 11 , the first metal material in the first dielectric layer 31 forms a test contact pair 50, and the first metal material on the first dielectric layer 31 forms a first metal layer 41.

[0145] In some embodiments, please refer to Figure 12 , S403 includes the following steps:

[0146] Step 1201: Form a second dielectric layer on the first metal layer.

[0147] Step 1202: Form a fourth through hole extending to the first metal layer in the second dielectric layer.

[0148] Step 1203: Form a dummy contact pair in the fourth through hole.

[0149] In some embodiments, please refer to Figure 13 , the preparation method further includes the following steps:

[0150] Step 1301: Form a third through hole extending to the dummy gate in the first dielectric layer.

[0151] Exemplarily, step 1301 can be implemented synchronously with step 802.

[0152] Figure 14 It is a cross-sectional schematic diagram of the structure obtained in step 1301 of the preparation method of the semiconductor test structure provided by the embodiment of the present invention. Please refer to Figure 14 , a third through hole 312 extending to the dummy gate 20, as well as a first through hole and a second through hole 311 extending to the bulk active region 11 are simultaneously formed in the first dielectric layer 31.

[0153] Step 1302: Form a second metal layer in the third through hole.

[0154] Specifically, please refer to Figure 15 , step 1302 includes the following steps:

[0155] Step 1501, deposit a metal material layer on and within the first dielectric layer.

[0156] Figure 16 is a cross-sectional schematic view of the structure obtained in step 1501 in the method for preparing a semiconductor test structure provided by an embodiment of the present invention. Please refer to Figure 16 , a metal material layer 40 is deposited both inside and outside the first dielectric layer 31. The metal material layer 40 fills the third through-hole 312, the first through-hole, and the second through-hole 311, and covers the first dielectric layer 31.

[0157] Step 1502, planarize the metal material layer until the first dielectric layer is exposed.

[0158] Figure 17 is a cross-sectional schematic view of the structure obtained in step 1502 in the method for preparing a semiconductor test structure provided by an embodiment of the present invention. Please refer to Figure 17 , the metal material layer 40 on the first dielectric layer 31 is removed, and the metal material layer 40 in the third through-hole 312 forms a second metal layer 42, and the metal material layer 40 in the first through-hole and the second through-hole 311 forms a test contact pair 50.

[0159] Step 1303, form a third dielectric layer on the second metal layer and the first dielectric layer, and the first test contact and the second test contact respectively penetrate the third dielectric layer.

[0160] Among them, the first metal layer is located on the third dielectric layer, and the second dielectric layer covers the first metal layer and the third dielectric layer.

[0161] Figure 18 is a cross-sectional schematic view of the structure obtained in step 1303 in the method for preparing a semiconductor test structure provided by an embodiment of the present invention. Please refer to Figure 18 , the third dielectric layer 33 covers the second metal layer 42 and the first dielectric layer 31.

[0162] Correspondingly, please refer to Figure 19 , the preparation method further includes the following steps:

[0163] Step 1901, form a fifth through-hole extending to the test contact pair within the third dielectric layer.

[0164] Figure 20 is a cross-sectional schematic view of the structure obtained in step 1901 in the method for preparing a semiconductor test structure provided by an embodiment of the present invention. Please refer to Figure 20, a fifth via hole 331 extending to the test contact pair 50 is formed in the third dielectric layer 33.

[0165] Step 1902, form a first metal layer in the fifth via hole and on the third dielectric layer.

[0166] Figure 21 It is a cross-sectional schematic diagram of the structure obtained in step 1902 in the preparation method of the semiconductor test structure provided by the embodiment of the present invention. Please refer to Figure 21 , the first metal layer 41 is formed on the third dielectric layer 33 and in the fifth via hole 331.

[0167] Based on the same inventive concept, please refer to Figure 22 , the present invention also provides a test method for a semiconductor structure, and the test method includes the following steps:

[0168] Step 2201, provide a semiconductor structure.

[0169] Wherein, the semiconductor structure includes a chip area and a test area. The test area is provided with the semiconductor test structure provided by the present invention. The chip area is provided with a gate and a contact structure. The gate and the dummy gate are formed simultaneously, and the contact structure and the dummy contact pair are formed simultaneously.

[0170] Step 2202, test the sheet resistance of the bulk active region through the first test line and the second test line.

[0171] Step 2203, determine whether the contact structure penetrates the first dielectric layer according to the sheet resistance of the bulk active region.

[0172] In the above test method for a semiconductor structure, first provide a semiconductor structure. The semiconductor structure includes a chip area and a test area. The test area is provided with the above semiconductor test structure. The chip area is provided with a gate and a contact structure. The gate and the dummy gate are formed simultaneously, and the contact structure and the dummy contact pair are formed simultaneously. If the contact structure also penetrates the first dielectric layer, the dummy contact pair also penetrates the first dielectric layer and is electrically connected to the dummy gate, that is, the first dummy contact and the second dummy contact are electrically connected through the dummy gate. At this time, between the first test end and the second test end, in addition to the bulk active region, it is also connected through the dummy contact degree and the dummy gate. In this way, the resistance between the first test end and the second test end measured through the first test line and the second test line will be greatly reduced. If the contact structure does not penetrate the first dielectric layer, the dummy contact pair does not penetrate the first dielectric layer, and the first dummy contact and the second dummy contact are not connected. At this time, only the bulk active region exists between the first test end and the second test end. In this way, the resistance between the first test end and the second test end measured through the first test line and the second test line is relatively large. Therefore, by testing the sheet resistance of the bulk active region through the first test line and the second test line, it is possible to determine whether the contact structure penetrates the first dielectric layer according to the sheet resistance of the bulk active region, and further determine whether there is a PID problem with the contact structure.

[0173] In some embodiments, referring to Figure 23 , step 2201 includes the following steps:

[0174] Step 2301, providing a substrate.

[0175] Wherein, the substrate includes a chip region and a test region, the test region includes a bulk active region and an isolation region located outside the bulk active region, and the bulk active region has a first test terminal and a second test terminal.

[0176] Step 2302, forming a gate, a dummy gate, and a first dielectric layer on the substrate, and the first dielectric layer covers the gate and the dummy gate.

[0177] Step 2303, opening a first via hole extending to the first test terminal and a second via hole extending to the second test terminal in the first dielectric layer.

[0178] Step 2304, depositing a first metal material, the first metal material forms a first test contact in the first via hole, the first metal material forms a second test contact in the second via hole, and the first metal material forms a first metal layer on the first dielectric layer.

[0179] Step 2305, forming a second dielectric layer on the first metal layer and the first dielectric layer.

[0180] Step 2306, simultaneously forming a contact structure and a dummy contact pair, the dummy contact pair includes a first dummy contact and a second dummy contact, and the contact structure, the first dummy contact, and the second dummy contact at least penetrate the second dielectric layer.

[0181] In some embodiments, step 2203 includes the following steps: if the sheet resistance of the bulk active region is less than a set resistance, it is determined that the contact structure penetrates the first dielectric layer; if the sheet resistance of the bulk active region is greater than or equal to the set resistance, it is determined that the contact structure does not penetrate the first dielectric layer.

[0182] In some embodiments, the horizontal distance between the first dummy contact and the first test contact is equal to the horizontal distance between the second dummy contact and the second test contact.

[0183] In some embodiments, the semiconductor structure includes two dummy gates and two dummy contact pairs, the bulk active region is located between the two dummy gates, and the orthographic projections of the two dummy contact pairs on the substrate are respectively located within the orthographic projections of the two dummy gates on the substrate.

[0184] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0185] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor test structure, characterized in that, the semiconductor test structure includes: a substrate including a bulk active region and an isolation region located outside the bulk active region, the bulk active region having a first test terminal and a second test terminal; a dummy gate located on the surface of the isolation region; a first dielectric layer covering the substrate and the dummy gate; a first metal layer including a first test line and a second test line isolated from each other, the first test line and the second test line being located on the first dielectric layer; a test contact pair including a first test contact and a second test contact, the first test contact and the second test contact respectively penetrating the first dielectric layer, the first test terminal being electrically connected to the first test line through the first test contact, and the second test terminal being electrically connected to the second test line through the second test contact; a second dielectric layer located on the first metal layer and the first dielectric layer; a dummy contact pair including a first dummy contact and a second dummy contact, the first dummy contact and the second dummy contact at least penetrating the second dielectric layer, the first dummy contact being electrically connected to the first test line, the second dummy contact being electrically connected to the second test line, and a positive projection of the dummy contact pair on the substrate and a positive projection of the dummy gate on the substrate having an overlapping part.

2. The semiconductor test structure according to claim 1, characterized in that, the semiconductor test structure further includes: a second metal layer disposed on the dummy gate, and the first dielectric layer covering the second metal layer.

3. The semiconductor test structure according to claim 1 or 2, characterized in that, a horizontal distance between the first dummy contact and the first test contact is equal to a horizontal distance between the second dummy contact and the second test contact.

4. The semiconductor test structure according to claim 1 or 2, characterized in that, a horizontal distance between the first dummy contact and the second dummy contact is equal to a horizontal distance between the first test contact and the second test contact.

5. The semiconductor test structure according to claim 1 or 2, characterized in that, the semiconductor test structure includes two of the dummy gates and two of the dummy contact pairs, the bulk active region being located between the two dummy gates, and positive projections of the two dummy contact pairs on the substrate and positive projections of the two dummy gates on the substrate respectively having overlapping parts.

6. The semiconductor test structure according to claim 5, characterized in that, distances between the two dummy gates and the bulk active region are equal.

7. The semiconductor test structure according to claim 1 or 2, characterized in that, the semiconductor test structure further includes: an insulating layer located between the dummy gate and the substrate.

8. A method for manufacturing a semiconductor test structure, characterized in that, the method includes: providing a substrate including a bulk active region and an isolation region located outside the bulk active region, the bulk active region having a first test terminal and a second test terminal; Form a dummy gate, a first dielectric layer, a test contact pair, and a first metal layer on the substrate. The dummy gate is located on the surface of the isolation region. The first dielectric layer covers the substrate and the dummy gate. The test contact pair includes a first test contact and a second test contact. The first test contact and the second test contact respectively penetrate through the first dielectric layer. The first metal layer includes a first test line and a second test line that are isolated from each other. The first test line and the second test line are located on the surface of the first dielectric layer. The first test terminal is electrically connected to the first test line through the first test contact. The second test terminal is electrically connected to the second test line through the second test contact; Form a second dielectric layer and a dummy contact pair that at least penetrates through the second dielectric layer in sequence. The second dielectric layer is located on the first metal layer and the first dielectric layer. The dummy contact pair includes a first dummy contact and a second dummy contact. The first dummy contact is electrically connected to the first test line. The second dummy contact is electrically connected to the second test line. And the orthographic projection of the dummy contact pair on the substrate and the orthographic projection of the dummy gate on the substrate have an overlapping part.

9. The method according to claim 8, wherein, The step of forming a dummy gate, a first dielectric layer, a test contact pair, and a first metal layer on the substrate includes: Form a first dielectric layer and a dummy gate on the substrate. The first dielectric layer covers the dummy gate; Form a first through hole extending to the first test terminal and a second through hole extending to the second test terminal in the first dielectric layer; Deposit a first metal material. The first metal material forms a first test contact in the first through hole. The first metal material forms a second test contact in the second through hole. The first metal material forms a first metal layer on the first dielectric layer.

10. The method according to claim 9, wherein, The method further includes: Form a third through hole extending to the dummy gate in the first dielectric layer; Form a second metal layer in the third through hole; Form a third dielectric layer on the second metal layer and the first dielectric layer. The first test contact and the second test contact respectively penetrate through the third dielectric layer; wherein, the first metal layer is located on the third dielectric layer. The second dielectric layer covers the first metal layer and the third dielectric layer.

11. A method for testing a semiconductor structure, wherein, The method includes: Provide a semiconductor structure. The semiconductor structure includes a chip region and a test region. The test region is provided with the semiconductor test structure according to any one of claims 1-7. The chip region is provided with a gate and a contact structure. The gate is formed simultaneously with the dummy gate. The contact structure is formed simultaneously with the dummy contact pair; Test the sheet resistance of the bulk active region through the first test line and the second test line; Determine whether the contact structure penetrates through the first dielectric layer according to the sheet resistance of the bulk active region.

12. The method according to claim 11, wherein, The step of determining whether the contact structure penetrates through the first dielectric layer according to the sheet resistance of the block-shaped active region includes: If the sheet resistance of the block-shaped active region is less than a set resistance, it is determined that the contact structure penetrates through the first dielectric layer; If the sheet resistance of the block-shaped active region is greater than or equal to the set resistance, it is determined that the contact structure does not penetrate through the first dielectric layer.

13. The method according to claim 11 or 12, wherein, The step of providing a semiconductor structure includes: Providing a substrate, the substrate includes a chip region and a test region, the test region includes a block-shaped active region and an isolation region located outside the block-shaped active region, and the block-shaped active region has a first test terminal and a second test terminal; Forming a gate, a dummy gate and a first dielectric layer on the substrate, and the first dielectric layer covers the gate and the dummy gate; Opening a first through hole extending to the first test terminal and a second through hole extending to the second test terminal in the first dielectric layer; Depositing a first metal material, the first metal material forms a first test contact in the first through hole, the first metal material forms a second test contact in the second through hole, and the first metal material forms a first metal layer on the first dielectric layer; Forming a second dielectric layer on the first metal layer and the first dielectric layer; Simultaneously forming a contact structure and a dummy contact pair, the dummy contact pair includes a first dummy contact and a second dummy contact, and the contact structure, the first dummy contact and the second dummy contact at least penetrate through the second dielectric layer.

14. The method according to claim 11 or 12, wherein, The horizontal distance between the first dummy contact and the first test contact is equal to the horizontal distance between the second dummy contact and the second test contact.

15. The method according to claim 11 or 12, wherein, The semiconductor structure includes two dummy gates and two dummy contact pairs, the block-shaped active region is located between the two dummy gates, and the positive projections of the two dummy contact pairs on the substrate are respectively located within the positive projections of the two dummy gates on the substrate.

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