Wafer flattening structure, apparatus and method

Abstract

The application discloses a wafer flattening structure, which comprises an outer shell, a pressing device arranged on the upper portion of the outer shell and a separation pad, the bottom of the outer shell and the pressing device can accommodate a warped wafer stack, and the pressing device is used for pressing the warped wafer stack; the warped wafer stack comprises a plurality of warped wafers and the separation pad arranged between any two adjacent warped wafers. The application further discloses a wafer flattening device and method. The warped wafers can be simultaneously flattened by arranging the separation pads between the warped wafers, the wafer sticking can be prevented, the wafer flattening efficiency is greatly improved, and the industrialization cost of enterprises is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a multi-wafer leveling structure, apparatus, and method. Background Technology

[0002] In existing chip packaging technologies, various package structures connected to the chip's internal pads are typically fabricated on carriers of different materials or on silicon wafers with integrated circuits. This interconnects the small chip integrated circuit output pins with the larger package substrate (or PCB). However, the fabrication process of these package structures requires various packaging materials with different coefficients of thermal expansion (CTE), including underfill and molding filler. Especially in the fabrication of RDLs for high-density fan-out package structures, when using the Die-Last process, multiple RDL layers need to be fabricated on the carrier first, followed by chip interconnection, underfill, and molding processes. RDL fabrication typically uses polyimide negative photoresist with a high CTE, and electroplating or electroless plating to prepare copper conductive layers. In chip packaging structures, silicon, which accounts for the largest volume percentage, has a CTE of 2.3 ppm / ℃, while copper has a CTE of 17.5 ppm / ℃. The CTEs of polyimide negative photoresist, underfill, and molding compound are related to their composition ratios, but their CTEs also fluctuate within the range of 6-90 ppm / ℃. This shows that the CTEs of both the packaging materials and interconnect materials (i.e., copper) involved in chip packaging are greater than those of silicon. Therefore, any heat treatment involved in chip packaging will generate warpage and corresponding CTE thermal mismatch stress in the chip packaging structure. Warpage is detrimental to subsequent chip packaging processes, while CTE thermal mismatch stress can lead to failure and / or reliability issues in the chip packaging structure.

[0003] However, in existing technologies, the warp correction and stress relief processes for wafers typically involve leveling each individual warped wafer, which has low leveling efficiency and is not conducive to reducing process costs. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a wafer leveling structure, apparatus, and method that can solve the problem of low efficiency in leveling warped wafers in existing technologies.

[0005] In a first aspect, a wafer leveling structure includes a housing, a pressing device disposed on the upper part of the housing, and an isolation pad, wherein a warped wafer stack can be accommodated between the bottom of the housing and the pressing device, and the pressing device is used to apply pressure to the warped wafer stack; the warped wafer stack includes a plurality of warped wafers and the isolation pad disposed between any two adjacent warped wafers.

[0006] As an optimization, the warped wafers in the warped wafer stack are arranged in the same direction of convex or concave warped wafers.

[0007] As an optimization, the warped wafers in the warped wafer stack are arranged in a mixed configuration of convex or concave warped wafers.

[0008] As an optimization, the isolation pad is also disposed on one side of the upper surface of the warped wafer at the top of the warped wafer stack.

[0009] As an optimization, the isolation pad is made of high-temperature resistant isolation paper.

[0010] As an optimization, the pressing device includes a pressing mechanism with adjustable stroke and a pressure plate disposed below the pressing mechanism for applying pressure to the warped wafer stack.

[0011] As a further optimization, the pressing mechanism includes a helical rod, two sliding blocks connected to the helical rod by threads, and two sets of connecting rods respectively hinged to the two sliding blocks. The two sets of connecting rods are respectively hinged to two sets of lugs fixed on the pressure plate; the two sliding blocks move in opposite directions.

[0012] As an optimization, the system also includes a pressure sensing device disposed at the bottom of the housing and a pressure display screen disposed on the side wall of the housing. The pressure sensing device is used to transmit the pressure value of the pressure applied by the pressing device to the warped wafer stack at room temperature to the pressure display screen.

[0013] As a further optimization, when the warped wafers in the warped wafer stack are in a pre-leveling state, the pressure value ranges from 2*10. 5 ~6*10 5 Pa.

[0014] As a further optimization, the pressure sensing device is provided with a pressure sensing point group, which includes: a central pressure sensing point group located in the central region of the pressure sensing device corresponding to the central region of the warped wafer, and an edge pressure sensing point group distributed in the edge region of the pressure sensing device corresponding to the edge region of the warped wafer.

[0015] As a further optimization, the central pressure sensing point group includes an absolute center point located at the center of the pressure sensing device and a first circular array of points surrounding the absolute center point; and / or

[0016] The edge pressure sensing point group includes a second circular array of points arranged circumferentially along the edge region of the pressure sensing device.

[0017] In a second aspect, a wafer leveling apparatus includes any of the wafer leveling structures described in the first aspect, and further includes a heating device for accommodating the wafer leveling structure.

[0018] Thirdly, a wafer leveling method employs a wafer leveling structure as described in the first aspect, including multiple preset target temperatures from low to high, and further includes the following steps:

[0019] The warped wafer stack is placed in the wafer leveling structure;

[0020] The pressing device is pressed down to bring the warped wafers in the warped wafer stack to a pre-leveling state.

[0021] The wafer leveling structure is placed into the heating device;

[0022] Heating step: The heating device starts the heating process; when the heating process reaches one of the preset target temperatures, the warped wafer stack is held at the preset target temperature for a corresponding preset time;

[0023] If the highest preset target temperature is not reached, the heating step will be repeated; otherwise, the cooling step will be initiated.

[0024] Cooling step: The internal temperature of the heating device gradually decreases to room temperature;

[0025] Release the pressure applied by the pressure-reducing device to the warped wafer stack.

[0026] As an optimization, when the warped wafer stack is in a pre-leveling state, the displacement made by the pressing device is no greater than the sum of the longitudinal warping heights of all the warped wafers.

[0027] Another wafer leveling method, employing a wafer leveling structure as described in the first aspect, includes the following steps:

[0028] The warped wafer stack is placed in the wafer leveling structure;

[0029] The pressing device is pressed down to bring the warped wafers in the warped wafer stack to a pre-leveling state.

[0030] The wafer leveling structure is placed into the heating device;

[0031] The heating device begins the heating process; when the heating process reaches the preset target temperature, the warped wafer stack is maintained at the preset target temperature for a preset time;

[0032] The internal temperature of the heating device gradually decreases to room temperature;

[0033] Release the pressure applied by the pressure-reducing device to the warped wafer stack.

[0034] As an optimization scheme, the preset target temperature is 150-200℃; the preset time is 60-600min.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. By placing spacers between warped wafers, multiple warped wafers can be leveled simultaneously, and adhesion can be prevented, greatly improving the leveling efficiency of warped wafers and reducing the industrialization cost for enterprises.

[0037] 2. By setting at least one segmented heating and cooling curve, more internal stress can be released when the warped wafer is absolutely flattened, thereby reducing the reliability risk of chip packaging products. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a three-dimensional schematic diagram of a wafer flattening structure according to the present invention;

[0040] Figure 2 This is a schematic diagram of the structure of the warped wafer stack M1 in the wafer leveling structure of the present invention;

[0041] Figure 3 This is a schematic diagram of the structure of the warped wafer stack M2 in the wafer leveling structure of the present invention;

[0042] Figure 4 This is a schematic diagram of the structure of the warped wafer stack M3 in the wafer leveling structure of the present invention;

[0043] Figure 5 This is a schematic diagram showing the correspondence between the warped wafer and the pressure sensing device in a wafer leveling structure of the present invention.

[0044] Figure 6 This is a schematic diagram of the first type of pressure sensing point group arrangement in a wafer leveling structure according to the present invention.

[0045] Figure 7 This is a schematic diagram of the second type of pressure sensing point group arrangement in a wafer leveling structure according to the present invention.

[0046] Figure 8 This is a schematic diagram of the third type of pressure sensing point group arrangement in a wafer leveling structure according to the present invention.

[0047] Figure 9 This is a schematic flowchart of an embodiment of the wafer leveling method of the present invention;

[0048] Figure 10 This is a schematic diagram of temperature-time variation in one embodiment of a wafer leveling method according to the present invention;

[0049] Figure 11 This is a schematic diagram of the longitudinal warpage height of the center point of the warped wafer in a wafer leveling method of the present invention;

[0050] Figure 12 This is a schematic flowchart of another embodiment of the wafer leveling method of the present invention. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0053] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the application. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] First aspect: A wafer planarization structure, such as Figures 1-4 As shown, the device includes a housing 10, a pressing device disposed on the upper part of the housing 10, and a spacer 31. A warped wafer stack can be accommodated between the bottom of the housing 10 and the pressing device. The pressing device is used to apply pressure to the warped wafer stack. The warped wafer stack includes a plurality of warped wafers 32 and a spacer 31 disposed between any two adjacent warped wafers 32.

[0055] The warped wafer stacks M1-M3 include neatly stacked isolation pads 31 and warped wafers 32. The warped wafers 32 may include convex warped wafers 32a and / or concave warped wafers 32b. The isolation pads 31 are spaced apart between the warped wafers 32 to isolate them and prevent them from sticking together during high-temperature heat treatment. Additionally, the isolation pads 31 may also be disposed on the upper surface of the uppermost warped wafer 32 in the warped wafer stacks M1-M3.

[0056] This device can simultaneously flatten multiple warped wafers. The warped wafers 32 are isolated from each other by spacers 31. The convex warped wafers 32a and concave warped wafers 32b in the warped wafer stack can be placed in any manner. For example, such as... Figures 2-4As shown, the placement of the warped wafer stacks can include: stacking convex warped wafers 32a in warped wafer stack M1, stacking concave warped wafers 32b in warped wafer stack M2, or a mixed stacking of convex and concave warped wafers 32a and 32b in warped wafer stack M3. Specifically, the warped wafers 32 in the warped wafer stacks M1 and M2 are arranged with unidirectional warping, meaning they are either all convex warped wafers 32a or all concave warped wafers 32b.

[0057] In this embodiment, by placing the isolation pads 31 at intervals between the warped wafers 32, multiple warped wafers can be leveled simultaneously, which greatly improves the leveling efficiency of the warped wafers and reduces the industrialization cost for enterprises.

[0058] In a preferred embodiment, the insulating pad 31 is made of high-temperature resistant insulating paper.

[0059] In this embodiment, the insulating pad is made of high-temperature resistant insulating paper. The low thermal conductivity and excellent thermal stability of aluminum silicate in the high-temperature resistant insulating paper are utilized to achieve isolation and heat preservation of the warped wafer. During the high-temperature heat treatment of the warped wafer, the packaging material involved in the warped wafer contains polymers. The Tg (Glass Transition Temperature) of the polymers is usually within the heat treatment temperature range of the warped wafer. If an insulating pad is not used, the warped wafers will stick together, which is not conducive to the separation of the flattened wafers.

[0060] As a preferred embodiment, such as Figures 1-4 As shown, the pressing device includes a pressing mechanism with adjustable stroke and a pressure plate 30 disposed below the pressing mechanism for applying pressure to the warped wafer stack M1-M3.

[0061] The adjustable stroke of the pressing device refers to the ability to precisely adjust the displacement of the pressing plate, allowing the internal stress of the warped wafer 32 at room temperature to increase slowly, preventing stress concentration within the warped wafer 32 and thus avoiding irreparable cracks. The size of the pressing plate 30 can be adapted to the wafer size, ensuring a more even pressure on the warped wafer stack M1-M3 during the pressing process, resulting in a smoother pressing process and preventing stress concentration within the warped wafer 32.

[0062] As a further preferred embodiment, such as Figures 1-4As shown, the pressing mechanism includes a helical rod 20, two sliding blocks 21a connected to the helical rod 20 by threads, and two sets of connecting rods 21b respectively hinged to the two sliding blocks 21a. The two sets of connecting rods 21b are respectively hinged to two sets of lugs 21c. One set of lugs 21c and the corresponding set of connecting rods 21b can be hinged together through both ends of a support rod 21d. The two sliding blocks 21a move in opposite directions.

[0063] The connecting rod 21b can be hinged to the pressure plate 30 via a lug 21c, wherein the lug 21c can be fixedly connected to the pressure plate 30. The two sliding blocks 21a move in opposite directions, which can be achieved by providing opposite threads on both sides of the screw rod 20. That is, the two sliding blocks 21a are respectively connected to two threaded segments with opposite threads on the screw rod 20. A rotating handle 22 connected to the screw rod 20 can also be provided.

[0064] In this embodiment, reference Figure 2 The rotating handle 22 can rotate to drive the screw rod 20, and the threads on the screw rod 20 push the two sliding blocks 21a to move towards the center of the screw rod 20. Under the drive of the sliding blocks 21a, the connecting rod 21b and the lug 21c move downward, thereby transmitting the downward force to the pressure plate 30, realizing the downward movement of the pressure plate 30. When the pressure plate 30 contacts the isolation pad 31 located at the top of the warped wafer stack, the entire leveling device can start to heat up to complete the leveling process of the warped wafer during high-temperature heat treatment, as well as the cooling process to room temperature.

[0065] As a preferred embodiment, such as Figures 2-4 As shown, it also includes a pressure sensing device 11 disposed at the bottom of the housing and a display screen 12 disposed on the side wall of the housing 10 and connected to the pressure sensing device 11.

[0066] When the pressure device moves downward, the bottom warped wafer 32 or the isolation pad 31 of the warped wafer stack undergoes several minute displacements to reach a pre-leveled state. The warped wafer in the pre-leveled state contacts the pressure sensing device 11 and transmits the pressure value sensed at room temperature to the pressure display screen 12. The pressure value can be converted into a pressure contour map and displayed on the pressure display screen 12.

[0067] As a further preferred embodiment, such as Figures 5-8As shown, the pressure sensing device 11 is provided with a plurality of pressure sensing points 110, thereby forming a pressure sensing point group. The pressure sensing point group includes: a central pressure sensing point group R0 located in the central region of the pressure sensing device 11 corresponding to the central region of the warped wafer 32, and an edge pressure sensing point group R1 distributed in the edge region of the pressure sensing device 11 corresponding to the edge region of the warped wafer 32.

[0068] In this embodiment, the pressure sensing device 11 can be disc-shaped. When the warped wafer 32, which has reached a pre-leveled state, contacts the pressure sensing device 11, the central region and the edge region of the warped wafer 32 respectively contact the central pressure sensing point group R0 and the edge pressure sensing point group R1 located on the pressure sensing device 11, and generate corresponding pressure values. When the warped wafers in the warped wafer stack are in a pre-leveled state, the pressure value can range from 2*10. 5 ~6*10 5 Pa, where, at room temperature, if the pressure applied by the pressing device to the warped wafer 32 is too large, excessive internal stress will be generated inside the warped wafer, especially in areas where the wafer warps significantly, leading to stress concentration, which in turn causes failure sites or potential failure sites such as cracks, microcracks, and crystal structure dislocations. If the pressure applied by the pressing device to the warped wafer 32 is too small, the warped wafer will not achieve the desired leveling effect.

[0069] In one embodiment, such as Figures 5-8 As shown, the central pressure sensing point group R0 is located at the center point of the pressure sensing device.

[0070] In one embodiment, such as Figure 6 As shown, the edge pressure sensing point group R1 may include 4 edge pressure sensing point groups R1.

[0071] In one embodiment, such as Figure 7 As shown, the central pressure sensing point group R0 includes a center point C0 located on the pressure sensing disk and a first circular array R0′ surrounding the center point. The first circular array can be composed of any number of points.

[0072] In one embodiment, such as Figure 8 As shown, the edge pressure sensing point group R1 includes a second circular array R1′ arranged circumferentially along the edge of the pressure sensing disk, and the second circular array R1′ can be composed of any number of points.

[0073] In a second aspect, a wafer leveling apparatus includes the wafer leveling structure described in the first aspect, and further includes a heating device for accommodating the wafer leveling structure.

[0074] The heating device is exemplified by an oven (not shown in the attached drawings). The wafer leveling structure is located inside the oven. The heat source provided by the oven heats the air medium between the inner wall of the oven and the leveling structure to achieve heat transfer between the oven and the wafer leveling structure, thereby achieving the effect of heating the wafer during leveling.

[0075] Thirdly, one embodiment of a wafer leveling method employs a wafer leveling structure as described in the first aspect, including multiple preset target temperatures from low to high, such as... Figure 9 As shown, the specific steps include the following:

[0076] S101: Place the warped wafer stack in the wafer leveling structure.

[0077] S102: Press down the pressing device until the warped wafers in the warped wafer stack are in a pre-leveling state.

[0078] In this step, specifically, the pressing device applies downward pressure along the longitudinal direction of the warped wafer stack. First, the pressing device is pressed down to a position where it contacts the warped wafer stack. Then, the pressing device continues to press down until each wafer in the warped wafer stack is in a pre-leveled state. The pre-leveled state refers to a state of temporary leveling under pressure.

[0079] S103: Place the warped wafer stack in the pre-leveled state into the heating device.

[0080] S104: Heating Step: The heating device begins the heating process, accompanied by a stress release process of the warped wafer stack. When the heating process reaches one of the preset target temperatures, the warped wafer stack is held at the preset target temperature for a corresponding preset time to slowly release the stress accumulated in the pre-leveled warped wafer stack at room temperature; if the highest preset target temperature is not reached, the heating step is repeated; otherwise, the cooling step is initiated.

[0081] S105: Cooling step: The internal temperature of the heating device gradually decreases to room temperature;

[0082] S106: Release the pressure applied by the pressing device to the warped wafer stack to obtain a flattened wafer.

[0083] In this embodiment, the heating step is referred to Figure 3 The temperature rise and fall curves of the warped wafer are used to control the downward movement of the pressure plate 30 in conjunction with the heating process. Taking four preset target temperatures as an example... Figure 10 As shown, the specific explanation is as follows:

[0084] In the first heating range, when the temperature reaches the first target temperature T1, it is held for time t1 to allow the warped wafer to release some of its internal stress. The working principle is as follows: the first target temperature T1 causes the atoms in the warped wafer to have a vibrational frequency f1 and a vibrational amplitude v1. Furthermore, the atomic vibrational frequency f1 at temperature T1 is greater than the atomic vibrational frequency f0 at room temperature, and the atomic vibrational amplitude v1 at the first target temperature T1 is greater than the atomic vibrational amplitude v0 at room temperature. Therefore, all the materials within the warped wafer are under accelerated atomic vibrational frequencies and increased atomic vibrational amplitudes, enabling the constituent atoms of each material in the warped wafer to repair some of the stress caused by the misalignment of the crystal lattice at room temperature.

[0085] In the second heating range, the temperature rises to the second target temperature T2 and is maintained for a second duration t2, allowing the warped wafer to release some of its internal stress.

[0086] In the third heating interval, the temperature rises to the third target temperature T3 and is maintained for a third duration t3, allowing the warped wafer to further release some of its internal stress.

[0087] In the fourth heating interval, the temperature rises to the fourth target temperature T4 and is maintained for a fourth duration t4, allowing the warped wafer to further release some of its internal stress.

[0088] Among them, the first target temperature T1 < the second target temperature T2 < the third target temperature T3 < the fourth target temperature T4.

[0089] Once the warped wafer has completed the leveling process after heating, cooling can begin. Depending on the specific requirements, cooling can be achieved through natural cooling or by employing measures to accelerate heat dissipation.

[0090] This embodiment only shows a typical heating curve. In order to more fully release the internal stress of the warped wafer, enterprises can set several heating ranges according to actual process requirements.

[0091] As a preferred embodiment, such as Figure 11 As shown, in the heating step, the preset displacement made by the pressing device at room temperature is not greater than the sum of the longitudinal warp heights Z of all the warped wafers.

[0092] It should be added that the longitudinal warp height Z of a warped wafer is defined as the difference between the longitudinal height of the warped wafer and the longitudinal height after absolute flattening. When the warped wafer is a convex warped wafer, refer to... Figure 11The longitudinal warp height Z of a warped wafer is the difference in longitudinal height between the highest point in the central region of the warped wafer and the lowest point in the edge region of the warped wafer. When the warped wafer is a concave warped wafer, the longitudinal warp height Z of the warped wafer is the difference in longitudinal height between the highest point in the edge region of the warped wafer and the lowest point in the central region of the warped wafer.

[0093] Another embodiment of a wafer leveling method employs a wafer leveling structure as described in the first aspect, such as... Figure 12 As shown, the specific steps include the following:

[0094] S201: Place the warped wafer stack in the wafer leveling structure.

[0095] S202: Press down the pressing device until the warped wafers in the warped wafer stack are in a pre-leveled state;

[0096] In this step, specifically, the pressing device applies downward pressure along the direction of the warped wafer stack. First, the pressing device is pressed down to a position that contacts the warped wafer stack. Then, the pressing device continues to press down and makes a preset displacement at room temperature until each wafer in the warped wafer stack is in a pre-flattened state, thereby obtaining a pre-flattened warped wafer stack at room temperature.

[0097] The preset displacement made by the pressing device at room temperature is not greater than the sum of the longitudinal warp heights Z of all the warped wafers.

[0098] S203: Place the wafer leveling structure having the pre-leveled warped wafer stack into a heating device;

[0099] S204: Heating step: The heating device starts the heating process, which is accompanied by the stress release process of the warped wafer stack; when the heating process reaches the preset target temperature, the warped wafer stack is held at the preset target temperature for a corresponding preset time, while slowly releasing the stress accumulated in the pre-leveled warped wafer stack at room temperature.

[0100] S205: Cooling step: The internal temperature of the heating device gradually decreases to room temperature.

[0101] S206: Release the pressure applied by the pressing device to the warped wafer stack to obtain a flattened wafer.

[0102] In this embodiment, the heating curve of the warped wafer includes only one heating range, the preset target temperature of which can be 150-200℃, and the preset time for which the pressing device holds the temperature can be 60min-600min.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A wafer leveling structure, characterized in that, The device includes a housing, a pressing device disposed on the upper part of the housing, and a spacer. A warped wafer stack can be accommodated between the bottom of the housing and the pressing device. The pressing device is used to apply pressure to the warped wafer stack. The warped wafer stack includes a plurality of warped wafers and the spacer disposed between any two adjacent warped wafers. The warped wafers include convex warped wafers and / or concave warped wafers. The spacers are placed between multiple warped wafers to isolate them. The convex warped wafers and / or concave warped wafers in the warped wafer stack are placed in any manner. The spacers are made of high-temperature resistant release paper.

2. The wafer leveling structure as described in claim 1, characterized in that: The warped wafers in the warped wafer stack are arranged in the same direction of warping, either convex or concave.

3. The wafer planarization structure as described in claim 1, characterized in that: The warped wafers in the warped wafer stack are arranged in a mixed configuration of convex and concave warped wafers.

4. The wafer leveling structure as described in claim 1, characterized in that: The isolation pad is also disposed on one side of the upper surface of the warped wafer at the top of the warped wafer stack.

5. The wafer leveling structure as described in claim 1, characterized in that: The pressing device includes a stroke-adjustable pressing mechanism and a pressure plate disposed below the pressing mechanism for applying pressure to the warped wafer stack.

6. The wafer leveling structure as described in claim 5, characterized in that: The pressing mechanism includes a helical rod, two sliding blocks connected to the helical rod by threads, and two sets of connecting rods respectively hinged to the two sliding blocks. The two sets of connecting rods are respectively hinged to two sets of lugs fixed on the pressure plate. The two sliding blocks move in opposite directions.

7. The wafer planarization structure as described in claim 1, characterized in that: It also includes a pressure sensing device disposed at the bottom of the housing and a pressure display screen disposed on the side wall of the housing. The pressure sensing device is used to transmit the pressure value of the pressure applied by the pressing device to the warped wafer stack at room temperature to the pressure display screen.

8. The wafer planarization structure as described in claim 7, characterized in that: When the warped wafers in the warped wafer stack are in a pre-leveling state, the pressure value ranges from 2*10. 5 ~6*10 5 Pa.

9. A wafer leveling structure as described in claim 7, characterized in that: The pressure sensing device is provided with a pressure sensing point group, which includes: a central pressure sensing point group located in the central region of the pressure sensing device corresponding to the central region of the warped wafer, and an edge pressure sensing point group distributed in the edge region of the pressure sensing device corresponding to the edge region of the warped wafer.

10. A wafer planarization structure as described in claim 9, characterized in that: The central pressure sensing point group includes an absolute center point located at the center of the pressure sensing device and a first circular array of points surrounding the absolute center point; and / or The edge pressure sensing point group includes a second circular array of points arranged circumferentially along the edge region of the pressure sensing device.

11. A wafer leveling device, characterized in that, The wafer leveling structure includes any one of claims 1-10, and further includes a heating device for accommodating the wafer leveling structure.

12. A wafer leveling method, employing a wafer leveling structure as described in any one of claims 1-10, comprising a plurality of preset target temperatures from low to high, and further comprising the following steps: The warped wafer stack is placed in the wafer leveling structure; The pressing device is pressed down to bring the warped wafers in the warped wafer stack to a pre-leveling state. The wafer leveling structure is placed into the heating device; Heating step: The heating device starts the heating process; when the heating process reaches one of the preset target temperatures, the warped wafer stack is held at the preset target temperature for a corresponding preset time; If the highest preset target temperature is not reached, the heating step will be repeated; otherwise, the cooling step will be initiated. Cooling step: The internal temperature of the heating device gradually decreases to room temperature; Release the pressure applied by the pressure-reducing device to the warped wafer stack.

13. A wafer leveling method as described in claim 12, characterized in that: When the warped wafer stack is in a pre-leveled state, the displacement made by the pressing device is no greater than the sum of the longitudinal warping heights of all the warped wafers.

14. A wafer leveling method, employing a wafer leveling structure as described in any one of claims 1-10, comprising the following steps: The warped wafer stack is placed in the wafer leveling structure; The pressing device is pressed down to bring the warped wafers in the warped wafer stack to a pre-leveling state. The wafer leveling structure is placed into the heating device; The heating device begins the heating process; when the heating process reaches the preset target temperature, the warped wafer stack is maintained at the preset target temperature for a preset time; The internal temperature of the heating device gradually decreases to room temperature; Release the pressure applied by the pressure-reducing device to the warped wafer stack.

15. A wafer leveling method as described in claim 14, characterized in that: The preset target temperature is 150~200℃; the preset time is 60~600min.

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