Method for forming floating contact hole and semiconductor device

Abstract

The present invention relates to a method for forming a floating contact hole and a semiconductor device. The method comprises: obtaining a substrate having a tunnel oxide layer and multiple gates formed thereon; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; photolithographically obtaining a photoresist pattern on the interlayer dielectric layer, the photoresist pattern including a small stripe in the middle of the floating contact hole; and etching the floating contact hole using the photoresist pattern as an etching mask. The present invention controls exposure conditions to obtain a stripe having a thickness smaller than that of the remaining photoresist. The stripe slows down the etching rate of the floating contact hole. Therefore, the metal silicide barrier layer does not need to be thickened to ensure that the oxide layer at the bottom of the floating contact hole has a sufficient thickness, thereby ensuring sufficient device withstand voltage. Furthermore, the thin metal silicide barrier layer helps avoid the formation of voids between adjacent gates in logic devices / memory devices with small line widths, thereby achieving the minimum area and the optimal economic benefits.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a method for forming a floating contact hole, and also to a semiconductor device. Background Art

[0002] Floating contact (hereinafter referred to as Floating CT) can achieve the RESURF (reduced surface electric field) effect and is an important means to improve device performance. In order to achieve the RESURF effect, there are requirements for the size of the Floating CT, which is generally 30-40% of the drift region length. The Floating CT is actually a relatively large deep trench, and the etching rate is much faster than that of ordinary small holes. In order to ensure sufficient device withstand voltage, a sufficiently thick oxide layer needs to be retained at the bottom of the Floating CT hole. Therefore, in order to ensure a sufficient process window, the oxide layer thickness of the SAB (Silicide Area Block, metal silicide barrier layer) needs to be significantly increased to ensure sufficient withstand voltage of the Floating CT.

[0003] In order to improve the performance of integrated circuits and reduce the area, the integration of BCD (Bipolar-CMOS-DMOS) technology with logic devices and memory is the future development direction. In order to achieve the maximum economic benefits, the line width of logic devices and memory is getting smaller and smaller. The spacing between the polysilicon gates (GT) of logic devices (or memory) is very small. The increase in the oxide layer thickness of SAB will cause voids to appear between the polysilicon gates. See Figure 1 . Figure 1 The left side shows an electron microscope photo of an exemplary (BL) device cross section, and the right side shows that the oxide layer of the SAB deposited during the manufacturing process is thicker than the left side. The electron microscope photo of the device cross section (all other conditions are the same as the left device) shows that the thickness of the SAB oxide layer increases. A void forms at the location of the oval frame. This void affects circuit performance and results in poor quality. To ensure sufficient device withstand voltage, the SAB oxide layer thickness must be increased. However, increasing the SAB oxide layer thickness introduces voids, which impacts device electrical performance. Summary of the Invention

[0004] Based on this, it is necessary to provide a method for forming a floating contact hole that can avoid forming a cavity between adjacent gates.

[0005] A method for forming a floating contact hole comprises: obtaining a substrate on which a tunnel oxide layer and a plurality of gates are formed; depositing, photolithographically etching, and etching a metal silicide barrier layer, thereby forming a metal silicide barrier layer on the tunnel oxide layer, on the gates, and between adjacent gates; forming a self-aligned metal silicide at a position where the metal silicide barrier layer is not formed; forming an interlayer dielectric layer on the gates, on the metal silicide barrier layer, and on the self-aligned metal silicide; coating a photoresist on the interlayer dielectric layer, exposing the photoresist through a contact hole photomask, and then The contact hole photoresist comprises a floating contact hole pattern, the floating contact hole pattern comprises a photoresist reserved area, the light transmittance of the photoresist reserved area is opposite to the light transmittance of the remaining area of the floating contact hole pattern, the photoresist pattern corresponding to the exposure of the remaining area is removed during development, and the exposure conditions are controlled so that the photoresist pattern corresponding to the exposure of the photoresist reserved area is partially removed during development; the interlayer dielectric layer and the metal silicide barrier layer are etched using the photoresist pattern as an etching mask layer to obtain a floating contact hole.

[0006] In one embodiment, the photoresist is a positive photoresist, the photoresist reserved area is a light-shielding area, and the remaining area is a light-transmitting area; the exposure conditions are controlled so that the photoresist pattern corresponding to the exposure of the photoresist reserved area is partially removed during development, including over-exposure of the photoresist.

[0007] In one embodiment, the width of the photoresist reserved area accounts for 30% to 40% of the width of the entire floating contact hole pattern.

[0008] In one embodiment, the floating contact hole is formed above the drift region of the LDMOS field effect transistor.

[0009] In one embodiment, at least a portion of the floating contact hole is located above the drift region.

[0010] In one embodiment, the width of the floating contact hole is 30% to 40% of the length of the drift region, and the width direction of the floating contact hole is parallel to the length direction of the drift region.

[0011] In one embodiment, in the step of forming a metal silicide barrier layer on the tunnel oxide layer, on the gate and between adjacent gates, the metal silicide barrier layer includes a first oxide layer having a thickness of

[0012] In one embodiment, in the step of obtaining a substrate, the thickness of the tunnel oxide layer formed on the substrate is

[0013] In one embodiment, each of the gates includes a gate oxide layer and a polysilicon gate on the gate oxide layer.

[0014] In one embodiment, the substrate obtained in the step of obtaining a substrate further has sidewalls formed on both sides of each gate.

[0015] In one embodiment, the method is applied in a BCD process.

[0016] In one embodiment, the step of etching the interlayer dielectric layer and the metal silicide barrier layer is dry etching, and the etching gas includes C4F8 and O2.

[0017] In one embodiment, the step of etching the metal silicide barrier layer adopts an etching endpoint detection method.

[0018] In one embodiment, the method further includes filling the floating contact hole with a conductive material.

[0019] In one embodiment, the conductive material filled in the floating contact hole is a tungsten plug.

[0020] In one embodiment, each of the gates is a gate of a logic device and / or a memory.

[0021] There is also a need to provide a semiconductor device.

[0022] A semiconductor device, wherein a floating contact hole is formed by the method for forming a floating contact hole according to any of the above embodiments, the semiconductor device further comprises a conductive material filled in the floating contact hole, the metal silicide barrier layer comprises a first oxide layer, and the thickness of the first oxide layer is

[0023] In the above-mentioned floating contact hole formation method and semiconductor device, the floating contact hole pattern is provided with a photoresist retention area with a light transmittance opposite to that of the remaining areas. By controlling the exposure conditions, the photoresist corresponding to the exposure of the photoresist retention area is partially removed during development, resulting in a strip of photoresist with a thickness smaller than that of the remaining photoresist. This small strip of photoresist slows the etching rate during floating contact hole etching. At the same time, this small strip of photoresist is consumed during the floating contact hole etching process, thereby still achieving a stable floating contact hole morphology. Since the etching rate of the floating contact hole is slowed by the small strip of photoresist, the metal silicide barrier layer does not need to be thick to ensure that the oxide layer at the bottom of the floating contact hole has a sufficient thickness to ensure sufficient device withstand voltage. The thin metal silicide barrier layer is also beneficial in preventing the formation of voids between adjacent gates of logic devices (or memories) with small line widths. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0025] Figure 1 This is an electron microscope photo of voids appearing between adjacent gates after the SAB oxide layer is thickened;

[0026] Figure 2 is a flow chart of a method for forming a floating contact hole in one embodiment;

[0027] Figure 3 is a schematic cross-sectional view of the semiconductor structure at a position corresponding to the floating contact hole after step S220 is completed;

[0028] Figure 4 is a schematic cross-sectional view of the semiconductor structure at a position corresponding to the floating contact hole after step S240 is completed;

[0029] Figure 5 is a schematic cross-sectional view of the semiconductor structure at a position corresponding to the floating contact hole after step S250 is completed;

[0030] Figure 6 is a schematic cross-sectional view of the semiconductor structure at a position corresponding to the floating contact hole after step S260 is completed;

[0031] Figure 7 is a flowchart of the sub-steps of step S210 in one embodiment;

[0032] Figure 8 FIG. 1 is a flow chart of device manufacturing steps after step S260 in one embodiment. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0039] As described in the background, increasing the oxide thickness of the silicide barrier (SAB) layer can lead to voids between polysilicon gates. This is because, as the SAB oxide thickens, the amount of silicon substrate lost to overetching increases to completely remove the SAB required to form the self-aligned silicide (salicide) layer. Consequently, the aspect ratio of the empty trench between the polysilicon gates increases after the SAB etching is completed. During the subsequent interlayer dielectric (ILD) deposition, these high-aspect-ratio empty trenches are difficult to fill, resulting in voids.

[0040] For example, in the BCD (Bipolar-CMOS-DMOS) process, void formation can be avoided by integrating logic devices and / or memories with larger line widths, while ensuring that the BCD devices have sufficient withstand voltage (by increasing the thickness of the oxide layer deposited by SAB). However, integrating logic devices and / or memories with large line widths in BCD increases chip area, increases chip cost, and affects economic benefits.

[0041] By changing the design of the floating contact hole, the present application ensures that the thickness of the SAB deposited oxide layer does not need to be very thick to ensure sufficient voltage resistance and no voids will appear, thereby integrating logic devices and / or memories with smaller line widths, reducing chip area, reducing chip costs, and improving economic benefits.

[0042] Figure 2 FIG. 1 is a flow chart of a method for forming a floating contact hole according to an embodiment, comprising the following steps:

[0043] S210, obtaining a substrate.

[0044] A tunnel oxide layer (Tunnel Oxide) 20 and a plurality of gates are formed on the substrate 10. In one embodiment of the present application, the substrate 10 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. Figure 3 In the embodiment shown, the substrate 10 is formed of single crystal silicon. Devices, such as NMOS and / or PMOS transistors, may be formed on the substrate 10. Similarly, conductive components may be formed in the substrate 10. The conductive components may be the source or drain of the transistor, or may be metal interconnect structures electrically connected to the transistor, etc. In addition, isolation structures such as STI (shallow trench isolation) may be formed on the substrate 10. In one embodiment of the present application, the material of the tunnel oxide layer 20 may be silicon oxide, such as silicon dioxide.

[0045] In one embodiment of the present application, the gate includes a gate dielectric layer and a gate layer on the gate dielectric layer. The gate dielectric layer may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment of the present application, the gate dielectric layer is a gate oxide layer, the material of which is silicon dioxide. In one embodiment of the present application, the gate layer is a polysilicon material, and in other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate layer.

[0046] In one embodiment of the present application, a method for forming a floating contact hole is applied in a BCD process.

[0047] In one embodiment of the present application, the gate is a gate of a logic device and / or a memory.

[0048] In one embodiment of the present application, spacers are further formed on both sides of the gate, and the material of the spacers can be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0049] S220 , forming a metal silicide barrier layer.

[0050] Self-aligned silicide (Salicide) is a relatively simple and convenient contact metallization process. However, during the fabrication of semiconductor devices, some areas require the salicide process, while others require the non-salicide process. For devices requiring the non-salicide process, the properties of salicide are utilized to cover the non-salicide areas with a material that does not react with metal. This material used to cover non-salicide devices is called SAB.

[0051] In one embodiment of the present application, SAB is deposited on the semiconductor structure obtained in step S210 , and then photolithography and etching of the SAB are performed, thereby forming a metal silicide barrier layer 30 on the tunnel oxide layer 20 , on the gate, and between adjacent gates. Figure 3 is a schematic cross-sectional view of the semiconductor structure at the position corresponding to the floating contact hole after step S220 is completed. Figure 3 In the embodiment shown, no gate is provided at the location of the floating contact hole, so Figure 3 The gate is not shown.

[0052] In one embodiment of the present application, the metal silicide barrier layer 30 includes an oxide layer, such as silicon dioxide. Furthermore, the metal silicide barrier layer 30 may also be a multilayer structure, for example, including an oxide layer and a nitride layer on the oxide layer. In one embodiment of the present application, the nitride layer is silicon nitride. In one embodiment of the present application, the thickness of the oxide layer of the metal silicide barrier layer 30 is

[0053] S230 , forming a self-aligned metal silicide at a location where the metal silicide barrier layer is not formed.

[0054] In one embodiment of the present application, the material of the self-aligned metal silicide may be CoSix, NiSix, PtSix, or a combination of these compounds.

[0055] S240 , forming an interlayer dielectric layer.

[0056] In one embodiment of the present application, an interlayer dielectric layer 40 is deposited on the semiconductor structure obtained in step S230 .

[0057] The interlayer dielectric (ILD) can be a silicon oxide layer, such as a doped or undoped silicon oxide layer formed using a thermal chemical vapor deposition (thermal CVD) or high-density plasma chemical vapor deposition (HDPCVD) process. Specifically, it can be undoped silicate glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). Furthermore, the interlayer dielectric can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS). In one embodiment of the present application, a silicon nitride layer can be deposited before depositing the ILD.

[0058] S250 , photolithography is performed on the interlayer dielectric layer to obtain a photoresist pattern.

[0059] Photoresist is coated on the interlayer dielectric layer 40, exposed through a contact hole photomask, and then developed. According to the pattern of the contact hole photomask, part of the photoresist is dissolved by the developer to form a photoresist pattern. The contact hole photomask includes a floating contact hole pattern.

[0060] In one embodiment of the present application, the floating contact hole pattern includes a photoresist retention area located in the middle of the floating contact hole pattern, and the light transmittance of the photoresist retention area is opposite to the light transmittance of the remaining areas of the floating contact hole pattern (i.e., the photoresist retention area is opaque and the remaining areas are translucent, or the photoresist retention area is translucent and the remaining areas are opaque). Due to the provision of the photoresist retention area, the floating contact hole pattern on the contact hole photomask is not a large hole groove pattern, but is divided into two small hole groove patterns by the photoresist retention area. The photoresist area corresponding to the exposure of the floating contact hole pattern other than the photoresist retention area is dissolved by the developer during development, while the photoresist area corresponding to the exposure of the photoresist retention area is partially dissolved by the developer during development, thereby leaving a glue strip 52, see Figure 5 . The partial dissolution of the photoresist area corresponding to the exposure of the photoresist reserved area is achieved by controlling the exposure conditions during exposure. In one embodiment of the present application, the photoresist is a positive photoresist, the photoresist reserved area is a light-shielding area, and the remaining area of the floating contact hole pattern is a light-transmitting area. During exposure, by increasing the exposure energy, that is, using energy greater than the normal exposure energy for exposure, the photoresist is overexposed, so that the photoresist area corresponding to the exposure of the photoresist reserved area will also be partially dissolved during development, thereby forming a strip 52 with a thickness less than the remaining photoresist retained after development.

[0061] In another embodiment of the present application, the photoresist may also be a negative photoresist, the photoresist reserved area is a light-transmitting area, and the remaining area of the floating contact hole pattern is a light-shielding area. The exposure energy is reduced during exposure, that is, energy smaller than the normal exposure energy is used for exposure, thereby underexposing the photoresist.

[0062] S260 , using the photoresist pattern as an etching mask layer, etching to obtain a floating contact hole.

[0063] See also Figure 6 Using the photoresist pattern obtained after the photolithography in step S250 as an etching mask, the interlayer dielectric layer 40 and the metal silicide barrier layer 30 are etched to form the floating contact hole 11. The strip 52 can slow down the etching rate during the floating contact hole etching. At the same time, the strip 52 (positive resist) has a small thickness due to overexposure and will be consumed during the floating contact hole etching process, thereby still obtaining a stable floating contact hole morphology.

[0064] For the embodiment in which the photoresist is a negative photoresist, the strip 52 has a smaller thickness due to underexposure and will also be consumed during the floating contact hole etching process, thereby still being able to obtain a stable floating contact hole morphology.

[0065] In the above-mentioned floating contact hole formation method, a floating contact hole pattern is provided with a photoresist retention area having a light transmittance opposite to that of the remaining areas. By controlling the exposure conditions, the photoresist corresponding to the exposure of the photoresist retention area is partially removed during development, resulting in a strip of photoresist having a thickness smaller than that of the remaining photoresist. This small strip of photoresist slows down the etching rate during floating contact hole etching. Simultaneously, the small strip of photoresist is consumed during the floating contact hole etching process, thereby still obtaining a stable floating contact hole morphology. Since the etching rate of the floating contact hole is slowed down by the small strip of photoresist, the metal silicide barrier layer does not need to be thickened to ensure that the oxide layer at the bottom of the floating contact hole has a sufficient thickness to ensure sufficient device withstand voltage. The thin metal silicide barrier layer helps to avoid the formation of voids between adjacent gates of logic devices (or memories) with small line widths, thereby allowing the integration of logic devices and / or memories with smaller line widths into the chip, reducing chip area, reducing chip cost, and improving economic benefits.

[0066] In one embodiment of the present application, the floating contact hole 11 is filled with a conductive medium, which acts as a field plate to improve the surface electric field (RESURF) of the drift region. Accordingly, step S260 is followed by a step of filling the floating contact hole 11 with a conductive medium.

[0067] exist Figure 5 In the embodiment shown, the floating contact hole pattern is divided into two small hole groove patterns by a photoresist reserved area. In other embodiments, the floating contact hole pattern can also be provided with two or more photoresist reserved areas, for example, the floating contact hole pattern is divided into three small hole groove patterns by two photoresist reserved areas.

[0068] In one embodiment of the present application, the width of the photoresist reserved area on the contact hole photomask accounts for 30% to 40% of the width of the entire floating contact hole pattern.

[0069] In one embodiment of the present application, a floating contact hole 11 is formed above the drift region of a laterally diffused metal oxide semiconductor field effect transistor (LDMOS). In another embodiment of the present application, a portion of the floating contact hole 11 may extend outside the drift region in the width direction. For example, a portion of the floating contact hole 11 may be located above the drift region and a portion may be located above the gate structure. Having at least a portion of the floating contact hole located above the drift region can also improve the surface electric field of the drift region.

[0070] In one embodiment of the present application, the width of the floating contact hole 11 is 30% to 40% of the length of the drift region of the LDMOS. The width direction of the floating contact hole 11 refers to the length direction of the drift region, i.e. Figure 6 Horizontal in.

[0071] In one embodiment of the present application, the thickness of the tunnel oxide layer 20 is

[0072] In one embodiment of the present application, the etching in step S260 is dry etching. In one embodiment of the present application, the etching gas of the dry etching includes C4F8 and O2.

[0073] In one embodiment of the present application, the step of etching the metal silicide barrier layer adopts an etching endpoint detection method, that is, monitoring the material at the bottom of the etched hole during etching, and stopping etching when it is detected that the etching reaches the material of the expected etch stop layer.

[0074] In one embodiment of the present application, after depositing the ILD in step S240 , the step of planarizing the interlayer dielectric layer 40 is further included. Specifically, the planarization process of the interlayer dielectric layer 40 can be performed by CMP (chemical mechanical polishing).

[0075] In one embodiment of the present application, in addition to the floating contact holes, other contact hole patterns may be provided on the contact hole photomask. Accordingly, the photolithography step S250 also patterns the photoresist at the locations of the other contact holes, and the etching step S260 also forms the other contact holes.

[0076] See also Figure 7 In one embodiment of the present application, step S210 includes the following steps:

[0077] S301, active area photolithography and etching.

[0078] The substrate is subjected to photolithography and etching of the active area.

[0079] S303, isolation structure photolithography and etching.

[0080] In one embodiment of the present application, the isolation structure is an STI (shallow trench isolation) structure.

[0081] S305 , planarizing the isolation structure.

[0082] In one embodiment of the present application, the STI is planarized by CMP (chemical mechanical polishing).

[0083] S307, well region doping.

[0084] In one embodiment of the present application, ion implantation is performed into the substrate to form a well region.

[0085] S309, tunnel oxide layer deposition.

[0086] A tunnel oxide layer is deposited on the semiconductor structure obtained in step S307 .

[0087] S311, tunnel oxide layer lithography and etching.

[0088] The tunnel oxide layer is used to improve the withstand voltage of the LDMOS. The tunnel oxide layer at the position where the tunnel oxide layer is not needed is etched away.

[0089] S313, forming a gate oxide layer.

[0090] The gate oxide layer can be formed by thermal oxidation growth or deposition of an oxide layer.

[0091] S315, depositing polysilicon.

[0092] Polysilicon is deposited on the semiconductor structure obtained in step S315.

[0093] S317, polysilicon gate lithography and etching.

[0094] Photolithography and etching are performed to form a plurality of polysilicon gates.

[0095] S319, LDD injection.

[0096] A lightly doped drain (LDD) implantation is performed on the semiconductor structure obtained in step S317.

[0097] S321, sidewall deposition.

[0098] A spacer material is deposited on the semiconductor structure obtained in step S319 .

[0099] S323, sidewall etching.

[0100] The sidewall material is etched to form sidewalls (spacers) on both sides of each gate.

[0101] S325, source and drain doping.

[0102] NSD doping and PSD doping are performed.

[0103] See also Figure 8 In one embodiment of the present application, step S260 further includes the following steps:

[0104] S471, contact hole filling.

[0105] A conductive material is deposited to fill the contact holes (including floating contact holes). The conductive material can be any suitable contact hole conductive material known to those skilled in the art, including but not limited to metal materials; the metal material can include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al. In one embodiment of the present application, the filled conductive material includes tungsten.

[0106] S473, contact hole planarization.

[0107] The conductive material deposited in step S471 is planarized, specifically by CMP.

[0108] S475, Metal Deposition.

[0109] A metal is deposited on the semiconductor structure obtained in step S473. The metal material may include aluminum.

[0110] S477, metal layer photolithography and etching.

[0111] The metal deposited in step S475 is subjected to photolithography and etching to obtain metal interconnects. At least part of the metal interconnects is electrically connected to the tungsten plugs filled in part of the contact holes.

[0112] The present application accordingly provides a semiconductor device, wherein a floating contact hole is formed by the method for forming a floating contact hole according to any of the aforementioned embodiments, and the floating contact hole is filled with a conductive material, such as a tungsten plug. The metal silicide barrier layer of the semiconductor device includes an oxide layer, and the thickness of the oxide layer is In one embodiment of the present application, the semiconductor device includes an LDMOS, and a floating contact hole is provided above the drift region of the LDMOS. In one embodiment of the present application, the width of the floating contact hole is 30% to 40% of the length of the drift region of the LDMOS. In one embodiment of the present application, the thickness of the tunnel oxide layer at the bottom of the floating contact hole is

[0113] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0114] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for forming a floating contact hole, comprising: Obtaining a substrate on which a tunnel oxide layer and a plurality of gates are formed; Depositing, photolithography and etching a metal silicide barrier layer, thereby forming a metal silicide barrier layer on the tunnel oxide layer, on the gate and between adjacent gates; forming a self-aligned metal silicide at a position where the metal silicide barrier layer is not formed; forming an interlayer dielectric layer on the gate, the metal silicide barrier layer and the self-aligned metal silicide; Coating a photoresist on the interlayer dielectric layer, exposing the photoresist through a contact hole photomask and then developing the photoresist to obtain a photoresist pattern; The contact hole photomask includes a floating contact hole pattern, the floating contact hole pattern includes a photoresist reserved area, the light transmittance of the photoresist reserved area is opposite to the light transmittance of the remaining area of the floating contact hole pattern, the photoresist pattern corresponding to the exposure of the remaining area is removed during development, and the exposure conditions are controlled so that the photoresist pattern corresponding to the exposure of the photoresist reserved area is partially removed during development; The interlayer dielectric layer and the metal silicide barrier layer are etched using the photoresist pattern as an etching mask layer to obtain a floating contact hole.

2. The method for forming a floating contact hole according to claim 1, wherein: The photoresist is a positive photoresist, the photoresist reserved area is a light-shielding area, and the remaining area is a light-transmitting area; The controlling of the exposure conditions so that the photoresist pattern corresponding to the exposure of the photoresist reserved area is partially removed during development includes over-exposure of the photoresist.

3. The method for forming a floating contact hole according to claim 1, wherein: The width of the photoresist reserved area accounts for 30% to 40% of the width of the entire floating contact hole pattern.

4. The method for forming a floating contact hole according to claim 1, wherein: The floating contact hole is formed above the drift region of the LDMOS field effect transistor.

5. The method for forming a floating contact hole according to claim 4, wherein: The width of the floating contact hole is 30% to 40% of the length of the drift region, and the width direction of the floating contact hole is parallel to the length direction of the drift region.

6. The method for forming a floating contact hole according to claim 1, wherein: In the step of forming a metal silicide barrier layer on the tunnel oxide layer, on the gate and between adjacent gates, the metal silicide barrier layer includes a first oxide layer having a thickness of 7. The method for forming a floating contact hole according to claim 1, wherein: In the step of obtaining the substrate, the thickness of the tunnel oxide layer formed on the substrate is 8. The method for forming a floating contact hole according to claim 1, wherein: Each of the gates includes a gate oxide layer and a polysilicon gate on the gate oxide layer. The substrate obtained in the step of obtaining the substrate also has sidewalls formed on both sides of each of the gates.

9. The method for forming a floating contact hole according to claim 1, wherein: The method is applied in the BCD process.

10. A semiconductor device, characterized in that: The floating contact hole is formed by the method for forming a floating contact hole according to any one of claims 1 to 5 and 7 to 9, wherein the semiconductor device further comprises a conductive material filled in the floating contact hole, the metal silicide barrier layer comprises a first oxide layer, and the thickness of the first oxide layer is

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