A junction barrier schottky diode and a method of manufacturing the same

Abstract

Embodiments of the present application provide a junction barrier Schottky diode and a preparation method thereof. The preparation method comprises: providing a substrate with an epitaxial layer on a surface, the substrate being heavily doped N-type, and the epitaxial layer being lightly doped N-type; forming a first region of P-type doping in the epitaxial layer; forming a second region of P-type heavy doping in the first region, wherein the doping concentration of P-type ions in the second region is greater than the doping concentration of P-type ions in the first region, the size of the second region is smaller than the size of the first region along the thickness direction perpendicular to the substrate, and the surface away from the substrate of the second region is rougher than the surface away from the substrate of the epitaxial layer and the surface away from the substrate of the first region; and forming a metal layer on the side of the epitaxial layer away from the substrate, wherein the metal layer forms a Schottky contact with the epitaxial layer, and the metal layer forms an ohmic contact with the first region and the second region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a junction barrier Schottky diode and its fabrication method. Background Technology

[0002] Existing technologies for fabricating junction barrier Schottky diodes suffer from problems such as high ohmic contact resistance and easy metal peeling from the ohmic contact. Summary of the Invention

[0003] The first aspect of this application provides a method for fabricating a junction barrier Schottky diode. The method for fabricating the junction barrier Schottky diode includes:

[0004] A substrate having an epitaxial layer on its surface is provided, wherein the substrate is heavily N-type doped and the epitaxial layer is lightly N-type doped;

[0005] A first region with P-type doping is formed within the epitaxial layer;

[0006] A second region heavily doped with P-type ions is formed within the first region, wherein the doping concentration of P-type ions in the second region is greater than that in the first region; the size of the second region is smaller than that of the first region along the thickness direction perpendicular to the substrate; and the surface of the second region away from the substrate is rougher than the surface of the epitaxial layer away from the substrate and the surface of the first region away from the substrate.

[0007] A metal layer is formed on the side of the epitaxial layer away from the substrate, wherein the metal layer forms a Schottky contact with the epitaxial layer and an ohmic contact with the first region and the second region.

[0008] In the fabrication method of the junction barrier Schottky diode according to the embodiments of this application, on the one hand, the second region has a roughened surface, which increases the surface contact area between the metal layer and the semiconductor, and can effectively reduce the contact resistance between the metal and the semiconductor. On the other hand, the second region has a higher P-type ion doping concentration than the first region, which can further reduce the contact resistance between the metal and the semiconductor. In addition, compared with the smooth metal-semiconductor contact interface, the surface of the second region in contact with the metal layer is roughened, which is beneficial to improving the bonding performance between the metal layer and the second region with a higher P-type ion doping concentration, that is, the metal layer has good adhesion and is not easy to fall off.

[0009] A second aspect of this application provides a junction barrier Schottky diode. The junction barrier Schottky diode includes:

[0010] N-type heavily doped substrate;

[0011] An N-type lightly doped epitaxial layer is located on the substrate;

[0012] The first region, which is p-type doped, is located within the epitaxial layer;

[0013] A second heavily p-type doped region is located within the first region, and the doping concentration of p-type ions in the second region is greater than that in the first region; the size of the second region is smaller than that of the first region along the thickness direction perpendicular to the substrate; the surface of the second region away from the substrate is rougher than the surface of the epitaxial layer away from the substrate and the surface of the first region away from the substrate; and

[0014] A metal layer is located on the side of the epitaxial layer away from the substrate, wherein the metal layer forms a Schottky contact with the epitaxial layer and an ohmic contact with the first region and the second region.

[0015] In the junction barrier Schottky diode of this application embodiment, on the one hand, the second region has a roughened surface, which increases the surface contact area between the metal layer and the semiconductor, effectively reducing the contact resistance between the metal and the semiconductor. On the other hand, the second region has a higher P-type ion doping concentration than the first region, which further reduces the contact resistance between the metal and the semiconductor. Furthermore, compared to a smooth metal-semiconductor interface, the roughened surface of the second region in contact with the metal layer improves the bonding performance between the metal layer and the second region with a higher P-type ion doping concentration, resulting in better metal layer adhesion and reduced detachment. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart illustrating a method for fabricating a junction barrier Schottky diode according to an embodiment of this application.

[0017] Figure 2 for Figure 1 A schematic cross-sectional view of the first region of P-type doping formed in the epitaxial layer in the method shown.

[0018] Figure 3 for Figure 1 The method shown is a cross-sectional schematic diagram of the formation of the second mask.

[0019] Figure 4 for Figure 1 The method shown is a schematic cross-sectional view of the second region formed by P-type heavy doping.

[0020] Figure 5 for Figure 1 The method shown is a cross-sectional view after the annealing activation step.

[0021] Figure 6 for Figure 1 The method shown is a schematic cross-sectional view of the formation of the Ni2Si alloy layer.

[0022] Figure 7 for Figure 1 The method shown is a cross-sectional schematic diagram of the metal stack.

[0023] Explanation of key component symbols:

[0024] 100 junction barrier Schottky diode

[0025] Substrate 10

[0026] Front 10a

[0027] Back 10b

[0028] Epitaxial layer 20

[0029] Zone 1, Section 31

[0030] Section 2, 32

[0031] First mask 40

[0032] First floor 41

[0033] Second floor 42

[0034] Second mask 50

[0035] Part 1, 51

[0036] Part 2, page 52

[0037] Side wall 53

[0038] Photoresist layer 60

[0039] Metal layer 70

[0040] Ni layer 71

[0041] Ni2Si alloy layer 72

[0042] Metal Stack 73

[0043] First opening H1

[0044] Second opening H2 Detailed Implementation

[0045] A junction barrier controlled Schottky diode (JBS) is a type of high-voltage, high-current composite power diode that combines the extremely short reverse recovery time of a Schottky barrier diode (SBD) with the high breakdown voltage and low leakage current of a PiN diode. When a forward bias is applied to a JBS diode, it is in the forward conducting state. Because the forward voltage drop is much smaller than the turn-on voltage of the PN junction, the PN junction is in the cutoff state, and only the Schottky region is conducting; the PN junction is formed by ion implantation of P+ and epitaxial drift region N-. When a reverse bias is applied to a JBS diode, it is in the reverse blocking state. The depletion regions of adjacent PN junctions overlap, generating a Schottky barrier shielding effect, thereby effectively reducing the reverse leakage current. Therefore, the breakdown voltage of the JBS diode is improved.

[0046] Ohmic contact resistance is a crucial component of the resistance of a junction barrier Schottky diode, and reducing this resistance is an effective way to decrease conduction losses. However, existing methods for fabricating junction barrier Schottky diodes suffer from high ohmic contact resistance and the tendency for metal to detach from the ohmic contact, affecting the reliability and yield of the diodes.

[0047] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0048] Figure 1 This is a schematic flowchart illustrating a method for fabricating a junction barrier Schottky diode according to an embodiment of this application. Figure 1 As shown, the preparation method includes steps S1 to S4. The following is in conjunction with... Figures 2 to 7 The structural diagram illustrates the preparation method in detail.

[0049] Step S1: Provide a substrate with an epitaxial layer on its surface.

[0050] In one embodiment, the substrate is N-type heavily doped silicon carbide (SiC), and the epitaxial layer is N-type lightly doped silicon carbide.

[0051] like Figure 2 As shown, the substrate 10 has a front side 10a and a back side 10b. An epitaxial layer 20 is formed on the front side 10a of the substrate 10.

[0052] Specifically, step S1 includes selecting a SiC epitaxial wafer and cleaning the SiC epitaxial wafer. The SiC epitaxial wafer can be a uniformly nitrogen-doped N-type SiC epitaxial wafer, wherein the doping concentration of the epitaxial layer 20 is 1E16cm⁻¹. -3 The epitaxial layer 20 has a thickness of 10 μm, and the total thickness of the substrate 10 and the epitaxial layer 20 in the epitaxial wafer is approximately 300 μm, but is not limited to this.

[0053] In addition, the cleaning steps for SiC epitaxial wafers can include RCA cleaning. Specifically, this may involve sequentially using an SC3 (H2SO4:H2O2:H2O = 1:1:10) (volume ratio) solution at a temperature of approximately 120℃ to 150℃ to remove organic matter and some metal contaminants from the surface of the SiC epitaxial wafer; then using a DHF (HF:H2O = 1:100) (volume ratio) solution at a temperature of approximately 20℃ to 25℃ to remove surface oxides and some metal contaminants from the SiC epitaxial wafer and reduce oxidation traps; finally, using an SC1 (NH4OH:H2O2:H2O = 1:1:5) (volume ratio) solution at a temperature of approximately 65℃ to 80℃ to remove surface particles and some metal contaminants from the SiC epitaxial wafer.

[0054] Step S2: Form a first region with a first doping concentration of P-type doped within the epitaxial layer.

[0055] like Figure 2 As shown, a first mask 40 is formed on the epitaxial layer 20. The first mask 40 includes a first layer 41 and a second layer 42 sequentially stacked on the epitaxial layer 20. The first layer 41 and the second layer 42 together define a plurality of first openings H1 that expose the surface of the epitaxial layer 20 (i.e., the first openings H1 penetrate both the first layer 41 and the second layer 42). The material of the first layer 41 is silicon dioxide (SiO2), and the material of the second layer 42 is photoresist.

[0056] Step S2 includes forming a first mask 40 and performing a first ion implantation using the first mask 40 to form a P-type doped first region 31 (hereinafter also referred to as the P+ region) within the epitaxial layer 20.

[0057] In one embodiment, the fabrication process of the first mask 40 specifically includes depositing a thickness of [missing information - likely a number] using plasma-enhanced chemical vapor deposition (PECVD). The SiO2 is then spin-coated with a 1.5μm thick photoresist, such as AZ5214, and then soft-baked in an oven at 90℃~110℃ for 30s. Next, the SiO2 above the P+ region of the epitaxial layer 20 is exposed through exposure, development, and thermal hardening processes. Then, the SiO2 above the P+ region is etched away by inductively coupled plasma (ICP) dry etching, thus obtaining the first mask 40.

[0058] Understandably, the SiO2 deposition method, SiO2 deposition thickness, photoresist thickness, softening temperature, and softening time are not limited to the ranges mentioned above.

[0059] Next, ion implantation forms the first region 31 (also known as the P+ region). This specifically involves multiple box-type ion implantations, implanting P-type ions (e.g., Al) at a temperature of 500°C, with the implantation energy and dose gradually decreasing, ultimately forming the P+ region. The concentration of P-type ions is approximately 1E15 cm⁻¹. -3 Understandably, the temperature and concentration of ion implantation are not limited to the ranges mentioned above.

[0060] Step S3: Form a second region with a second doping concentration of P-type heavy doping within the first region.

[0061] Specifically, step S3 includes forming a second mask and using the second mask to form a second region (hereinafter also referred to as the P++ region) with a higher P-type ion doping concentration (i.e., the second doping concentration) in the first region through a second ion implantation.

[0062] Please refer to the following: Figure 2 and Figure 3 The second mask 50 has a plurality of second openings H2, and the size of the second openings H2 is smaller than the size of the first opening H1.

[0063] Specifically, forming the second mask 50 includes removing the photoresist on the SiO2 in step S2 (i.e., removing the second layer 42 in the first mask 40) after forming the first region 31 by dry and wet photoresist removal methods, followed by continued deposition. Thick SiO2. A thick layer of SiO2 covers the first region 31 and the first layer 41 of the first mask 40 (i.e., the original SiO2 mask layer of the first mask 40).

[0064] Then, the material was etched away using a dry etching method. The thick SiO2 layer is located on the portion of the first region 31 and the top portion of the first layer 41, with the remaining portion attached to the sides of the first layer 41 forming sidewalls 53 to prepare for subsequent secondary ion implantation. Thus, the first layer 41 and the sidewalls 53 work together to form a second mask 50. The second mask 50 includes a first portion 51 and a second portion 52. The first portion 51 is formed by the first layer 41 of the first mask 40 and subsequent deposition... The second portion 52, obtained by etching SiO2, is a sidewall 53, or in other words, the sidewall 53 is formed on the sidewall of the first mask 40 defining the first opening H1. Due to the formation of the sidewall, the second opening H2 of the second mask 50 is smaller than the first opening H1 of the first mask 40. Understandably, the deposition thickness of SiO2 in the step of forming the second mask 50 is not limited to the range described above.

[0065] In other embodiments, the material of the first layer 41 of the first mask 40 and the material of the second mask 50 are not limited to SiO2. For example, the material of the first layer 41 of the first mask 40 and the material of the second mask 50 may also be silicon nitride. Alternatively, the materials of the first layer 41 of the first mask 40 and the materials of the second mask 50 may also be different. For example, the first layer 41 of the first mask 40 may be either SiO2 or silicon nitride, and the material of the second mask 50 may be either SiO2 or silicon nitride. In this case, the process of forming the second mask 50 includes, for example, completely removing the first mask 40 after forming the first region 31, and then forming the second mask 50 having the second opening H2. Figure 4 As shown, forming a second region 32 with a higher concentration of P-type ions specifically involves using a higher dose (e.g., 1E17–1E18 cm⁻¹) than the first ion implantation. -3 Lower energy (e.g., less than 40 keV) Al and B plasma implantation methods are used to form a second region 32 within the space constructed by the sidewall 53 (i.e., within the second opening H2), where the P-type ion doping concentration is greater than that in the first region 31.

[0066] Because the size of the second opening H2 is smaller than the size of the first opening H1, the size of the second region 32 formed along the thickness direction perpendicular to the substrate 10 is smaller than the size of the first region 31. Understandably, the ion implantation dose and ion implantation energy in the step of forming the second region 32 are not limited to the ranges described above.

[0067] Please refer to the following: Figure 4 and Figure 5The formation of the second region 32, which has a higher concentration of P-type ions, also includes removing the second mask 50 after the second ion implantation using a buffered oxide etch (BOE) solution (49% HF: 40% NHF4 = 1:6) (volume ratio). Subsequently, a photoresist layer 60 covering the first region 31 and the epitaxial layer 20 is formed through a mask photolithography process. That is, except for the second region 32, which has a higher concentration of P-type ions, the rest of the region is covered by the photoresist layer 60.

[0068] A high-temperature annealing process (e.g., 1700°C) is then performed to activate the doped ions in the first region 31 and the second region 32. Since the photoresist has a heat resistance of only 150°C, the photoresist layer 60 will first carbonize to form a carbon film during the high-temperature annealing process. Understandably, the high-temperature annealing process is not limited to the above-described steps in forming the second region 32, which has a higher concentration of P-type ion doping.

[0069] In this case, the surface of the N-type doped epitaxial layer 20 away from the substrate 10 is the part to be formed with a Schottky contact. Since the surface of the epitaxial layer 20 away from the substrate 10 is covered by the photoresist layer 60 during the high-temperature annealing activation step, the photoresist layer 60 has a protective effect on the part of the epitaxial layer 20 to be formed with a Schottky contact.

[0070] Furthermore, the surfaces of the first region 31 and the second region 32 that are away from the substrate 10 are the portions to be formed with ohmic contacts. Since the surface of the second region 32 is not covered by the photoresist layer 60 during the high-temperature annealing activation step, the surface of the second region 32 is roughened during the high-temperature annealing activation process.

[0071] In summary, during the high-temperature annealing activation process, the surface of the second region 32 away from the substrate 10 is roughened, while the surfaces of the first region 31 and the epitaxial layer 20 away from the substrate 10 are not roughened. The surface of the second region 32 away from the substrate 10 is rougher than the surfaces of the epitaxial layer 20 and the first region 31 away from the substrate 10.

[0072] Specifically, roughness is defined as the root mean square (rms) value (Rrms) of the height difference. In this fabrication method, the roughness of the surface of the second region 32 away from the substrate 10 is approximately 15 nm to 30 nm; while the surfaces of the first region 31 and the epitaxial layer 20 away from the substrate 10 are not roughened, and the roughness of the surfaces of the first region 31 and the epitaxial layer 20 away from the substrate 10 is approximately 1 nm.

[0073] It should be noted that the step of forming sidewall 53 is extremely necessary. On the one hand, sidewall 53 can prevent numerous defects at the implantation edge from affecting the Schottky barrier region during the second ion implantation, thereby affecting the device performance of the junction barrier Schottky diode. On the other hand, if boron is used for ion implantation to form the P++ region during the second ion implantation, due to the small atomic mass of boron and its strong diffusion ability, lateral diffusion will occur during the subsequent annealing activation of doped ions. Therefore, it is necessary to form sidewall 53 to reduce the size of the heavily p-doped base region (also known as the Pbase region) and prevent lateral diffusion during annealing activation from affecting the Schottky barrier region, thus impacting the device performance of the junction barrier Schottky diode.

[0074] Step S4: Form a metal layer on the side of the epitaxial layer away from the substrate.

[0075] Specifically, step S4 includes forming a Ni2Si alloy layer that is in direct contact with the second region and forming a Ti layer that is in direct contact with both the epitaxial layer and the first region.

[0076] Please see Figure 6 The formation of the Ni2Si alloy layer 72 specifically includes sputtering on the second region 32 and the photoresist layer 60 using a magnetron sputtering machine. A thick layer of Ni metal was then annealed at 500°C in an inert gas atmosphere (such as Ar) for 2 min to form a Ni2Si alloy with partial C precipitation. The alloy was then cleaned at 80°C for 10 min with a 5:1 SPM (98H2SO4:30% H2O2) solution to etch away the C precipitation, followed by annealing at 1050°C in an inert gas atmosphere (such as Ar) for 2 min.

[0077] Thus, as Figure 6 As shown, a Ni layer 71 is covered on the surface of the photoresist layer 60, and a Ni2Si alloy layer 72 is covered on the surface of the second region 32, which has a higher concentration of P-type ions, away from the substrate 10.

[0078] Understandably, in the steps of forming the Ni2Si alloy layer 72, the thickness of the Ni metal, the temperature and time involved in the annealing are not limited to the ranges mentioned above.

[0079] like Figure 6 and Figure 7 As shown, after forming the Ni2Si alloy layer 72, the photoresist layer 60 is removed using a dry stripping method. Subsequently, a metal stack 73 is formed on one side of the front side 10a of the substrate 10. The metal stack 73 covers the epitaxial layer 20, the first region 31, and the Ni2Si alloy layer 72, and is in direct contact with the surfaces of the epitaxial layer 20, the first region 31, and the Ni2Si alloy layer 72.

[0080] Specifically, the step of forming the metal stack 73 includes depositing a Ti layer on one side of the front side 10a of the substrate 10. The Ti layer covers the epitaxial layer 20, the first region 31 and the Ni2Si alloy layer 72, and is in direct contact with the surfaces of the epitaxial layer 20, the first region 31 and the Ni2Si alloy layer 72.

[0081] Furthermore, forming the metal layer 70 may also include sequentially forming a TiN layer and an AlCu layer on the side of the Ti layer away from the substrate 10. Understandably, the metal stack 73 is not limited to a Ti / TiN / AlCu stack, but may also be a stack of other metal films. Other metal films include, for example, Al, Mo, Au, etc. The metal layer 70 forms a Schottky contact with the epitaxial layer 20, and the metal layer 70 forms an ohmic contact with the first region 31 and the second region 32. Figure 7 The region I of a Schottky contact is indicated by a rectangular dashed box, and the region II of an Ohmic contact is indicated by an elliptical dashed box.

[0082] Specifically, the Ti layer in metal layer 70 directly contacts the epitaxial layer 20 to form a Ti / SiC-based Schottky contact. The Ti layer in metal layer 70 directly contacts the p-type doped first region 31 to form a Ti / SiC-based ohmic contact; the Ni2Si alloy layer 72 in metal layer 70 directly contacts the second region 32 with a higher p-type ion doping concentration to form a Ni2Si / SiC-based ohmic contact. Thus, a junction barrier Schottky diode 100 is obtained.

[0083] In summary, the above-described method for fabricating a junction barrier Schottky diode employs a method of shrinking the heavily p-type doped base region to prevent numerous edge defects from affecting the Schottky barrier region during the ion implantation step. Furthermore, it prevents lateral diffusion during the annealing activation process in the ion implantation step (at least when using beta implantation). This increases the effective carrier concentration at the metal-semiconductor (MS) interface, thereby enhancing device performance and reliability.

[0084] Moreover, in the above-mentioned method for fabricating a junction barrier Schottky diode, the P-type heavily doped base region is reduced by forming sidewalls, thereby achieving P++ heavy doping in a specified region, roughening of a specified region, and formation of Ni2Si alloy in a specified region. This effectively reduces the contact resistance between the metal and the semiconductor and improves the ohmic contact performance of the device.

[0085] Furthermore, in the aforementioned method for fabricating a junction barrier Schottky diode, the first mask is partially composed of SiO2. After the first region of P-type doping is fabricated using the first mask, SiO2 is deposited further, and the shielding layer is etched back to form sidewalls, thus reducing the first opening of the first mask to obtain the second mask. Since the fabrication process of the second mask utilizes a portion of the first mask, the fabrication process is simplified, resulting in high efficiency and low cost.

[0086] Furthermore, because the second ion implantation of P-type ions is activated by high-temperature annealing, the second region with a higher concentration of P-type ion doping lacks a carbon film for protection, resulting in surface roughening of the second region. This increases the surface contact area between the metal layer (the subsequently formed Ni2Si alloy layer) and the second region with a higher concentration of P-type ion doping, thus improving ohmic contact performance. Moreover, due to the roughened surface of the second region with a higher concentration of P-type ion doping, the metal layer exhibits better adhesion and is less prone to detachment compared to a smooth metal-semiconductor interface.

[0087] Furthermore, compared to the case where a second region with a higher concentration of P-type ions is not formed, and the metal layer only forms an ohmic contact with the heavily P-type doped base region, the above-described method for fabricating a junction barrier Schottky diode forms a second region with a higher concentration of P-type ions in the first P-type doped region. The metal layer forms an ohmic contact not only with the first P-type doped region but also with the second region with a higher concentration of P-type ions, thereby reducing the ohmic contact resistance of the device.

[0088] Furthermore, compared to forming ohmic contacts on the back side of the substrate, the above-mentioned method for fabricating a junction barrier Schottky diode forms ohmic contacts on the front side of the device. This overcomes the disadvantages of forming ohmic contacts on the back side of the device, such as requiring an additional photolithography step on the back side, which increases the fabrication difficulty; and the lack of overlay markings on the back side, making it difficult to accurately copy the pattern to the back side of each device.

[0089] This application also provides a junction barrier Schottky diode prepared using the above method.

[0090] like Figure 7As shown, the junction barrier Schottky diode 100 includes an N-type heavily doped substrate 10, an N-type lightly doped epitaxial layer 20 on the substrate 10, a P-type doped first region 31 within the epitaxial layer 20, a P-type heavily doped second region 32 within the first region 31, and a metal layer 70 located on the side of the epitaxial layer 20 away from the substrate 10. The doping concentration of P-type ions in the second region 32 is greater than that in the first region 31. Along the thickness direction perpendicular to the substrate 10, the size of the second region 32 is smaller than that of the first region 31. The surface of the second region 32 away from the substrate 10 is rougher than the surfaces of the epitaxial layer 20 and the first region 31 away from the substrate 10. The metal layer 70 forms a Schottky contact with the epitaxial layer 20, and an ohmic contact with the first region 31 and the second region 32.

[0091] Both the substrate 10 and the epitaxial layer 20 are made of silicon carbide. The metal layer 70 includes a Ni2Si alloy layer 72 in direct contact with the second region 32 and a Ti layer in direct contact with both the epitaxial layer 20 and the first region 31. The Ti layer also covers the Ni2Si alloy layer 72. The metal layer 70 also includes a TiN layer and an AlCu layer sequentially stacked on the side of the Ti layer away from the substrate 10. The surface roughness of the second region 32 away from the substrate 10 is approximately 15 nm to 30 nm.

[0092] In the junction barrier Schottky diode of this application embodiment, on the one hand, the second region has a roughened surface, which increases the surface contact area between the metal layer and the semiconductor, effectively reducing the contact resistance between the metal and the semiconductor. On the other hand, the second region has a higher P-type ion doping concentration than the first region, which further reduces the contact resistance between the metal and the semiconductor. Furthermore, compared to a smooth metal-semiconductor interface, the roughened surface of the second region in contact with the metal layer improves the bonding performance between the metal layer and the second region with a higher P-type ion doping concentration, resulting in better metal layer adhesion and reduced detachment.

[0093] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for fabricating a junction barrier Schottky diode, characterized in that, include: A substrate having an epitaxial layer on its surface is provided, wherein the substrate is heavily N-type doped and the epitaxial layer is lightly N-type doped; A first region with P-type doping is formed within the epitaxial layer; A second region heavily doped with P-type ions is formed within the first region, wherein the doping concentration of P-type ions in the second region is greater than that in the first region, and the size of the second region is smaller than that of the first region along the thickness direction perpendicular to the substrate. A photoresist layer is formed that completely covers the first region and the epitaxial layer but exposes the second region. Annealing activates the doped ions in the first and second regions. During the annealing activation process, the surface of the second region away from the substrate is roughened, the photoresist layer forms a carbon film, and the surfaces of the first region away from the substrate and the epitaxial layer away from the substrate are not roughened under the protection of the carbon film. This results in the surface of the second region away from the substrate being rougher than both the surface of the epitaxial layer and the surface of the first region away from the substrate. A metal layer is formed on the side of the epitaxial layer away from the substrate, wherein the metal layer forms a Schottky contact with the epitaxial layer and an ohmic contact with the first region and the second region.

2. The method for fabricating a junction barrier Schottky diode as described in claim 1, characterized in that, The first region is formed in the epitaxial layer by a first ion implantation using a first mask having a first opening; Using a second mask with a second opening, the second region is formed within the first region by a second ion implantation. The size of the second opening is smaller than the size of the first opening.

3. The method for fabricating a junction barrier Schottky diode as described in claim 2, characterized in that, After the first region is formed, a sidewall is formed on the sidewall of the first mask that defines the first opening, thereby obtaining the second mask.

4. The method for fabricating a junction barrier Schottky diode as described in claim 3, characterized in that, The formation of the second zone also includes: After the second ion implantation, the second mask is removed, and the photoresist layer is formed.

5. The method for fabricating a junction barrier Schottky diode as described in claim 4, characterized in that, Both the substrate and the epitaxial layer are made of silicon carbide. Forming the metal layer includes: Forming a Ni2Si alloy layer in direct contact with the second region; and A Ti layer is formed that is in direct contact with both the epitaxial layer and the first region.

6. The method for fabricating a junction barrier Schottky diode as described in claim 5, characterized in that, The Ti layer also covers the Ni2Si alloy layer, and the formation of the metal layer further includes forming a TiN layer and an AlCu layer sequentially stacked on the side of the Ti layer away from the substrate.

7. A junction barrier Schottky diode, characterized in that, include: N-type heavily doped substrate; An N-type lightly doped epitaxial layer is located on the substrate; The first region, which is p-type doped, is located within the epitaxial layer; A second region heavily doped with P-type ions is located within the first region, and the doping concentration of P-type ions in the second region is greater than that in the first region; the size of the second region is smaller than that of the first region along the thickness direction perpendicular to the substrate; neither the surface of the epitaxial layer away from the substrate nor the surface of the first region away from the substrate is roughened, and the surface of the second region away from the substrate is rougher than both the surface of the epitaxial layer away from the substrate and the surface of the first region away from the substrate; and A metal layer is located on the side of the epitaxial layer away from the substrate, wherein the metal layer forms a Schottky contact with the epitaxial layer and an ohmic contact with the first region and the second region.

8. The junction barrier Schottky diode as described in claim 7, characterized in that, The substrate and the epitaxial layer are both made of silicon carbide; the metal layer includes a Ni2Si alloy layer that is in direct contact with the second region and a Ti layer that is in direct contact with both the epitaxial layer and the first region.

9. The junction barrier Schottky diode as described in claim 8, characterized in that, The Ti layer also covers the Ni2Si alloy layer, and the metal layer further includes a TiN layer and an AlCu layer stacked sequentially on the side of the Ti layer away from the substrate.

10. The junction barrier Schottky diode as described in any one of claims 7 to 9, characterized in that, The surface roughness of the second region, away from the substrate, ranges from 15 nm to 30 nm.

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