Light-emitting diode and light-emitting device

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode, comprising a semiconductor stack, a first electrode, and a second electrode. The semiconductor stack has a mesa, a lower surface, and an upper surface that are opposite to each other. The semiconductor stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, wherein the light-emitting layer is located between the first and second semiconductor layers. The mesa refers to the surface of the first semiconductor layer not covered by the light-emitting layer. The first semiconductor layer has a through-portion at the mesa, which extends from the upper surface of the first semiconductor layer to the lower surface of the first semiconductor layer. The first electrode is disposed at least within the through-portion to electrically connect to the first semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer. Thus, the provision of the through-portion allows current injected through the first electrode to be injected from the sidewalls of the first semiconductor layer, thereby reducing the operating voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a light emitting diode and a light emitting device. Background Art

[0002] A light-emitting diode (LED) is a semiconductor light-emitting element typically made of semiconductors such as GaN, GaAs, GaP, and GaAsP. Its core is a PN junction, which is responsible for the light-emitting properties of the diode. LEDs offer advantages such as high luminous intensity, high efficiency, compact size, and long life, making them considered one of the most promising light sources. They are widely used in lighting, surveillance and control, high-definition broadcasting, high-end cinemas, office displays, interactive conferences, and virtual reality.

[0003] In the process of realizing the present invention, the inventors discovered that there are at least the following problems in the prior art: The emission wavelength of deep ultraviolet LEDs is mainly distributed in the range of 270nm to 283nm. The materials of their active layers are usually composed of AlxGaN and GaN materials with high Al content. Therefore, they are more susceptible to the design of the epitaxial growth machine, which affects the aluminum content of the active layer, thereby causing the light decay characteristics and emission wavelength of the deep ultraviolet light-emitting diode. In order to improve its light emission characteristics, deep ultraviolet LEDs mainly adopt a flip-chip structure. Therefore, in the last step of deep ultraviolet LED preparation, a pad with an AuSn layer is used. The thickness of the pad is at least 2μm to improve the heat dissipation characteristics of the component. However, due to the influence of the emission wavelength of deep ultraviolet LEDs, the photoelectric conversion efficiency of the chip is poor, the overall operating voltage is high, and heat is easily accumulated in the chip. When large current is injected, it is easy to cause poor heat dissipation, affecting the stability of the product.

[0004] It should be noted that the information disclosed in this background technology section is only intended to increase understanding of the overall background of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The present invention provides a light emitting diode, which includes a semiconductor stack, a first electrode and a second electrode.

[0006] The semiconductor stack has a mesa, an opposing lower surface, and an upper surface. The semiconductor stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The light-emitting layer is located between the first and second semiconductor layers. The mesa refers to the surface of the first semiconductor layer not covered by the light-emitting layer. The first semiconductor layer has a through-hole at the mesa. A first electrode is disposed at least within the through-hole to electrically connect to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer.

[0007] In some embodiments, the first electrode includes a first sublayer and a second sublayer, the first sublayer is disposed in the through-hole and on the mesa, the second sublayer is disposed on the back side of the mesa, and the first sublayer and the second sublayer are electrically connected through the through-hole.

[0008] In some embodiments, a size of the through portion at the mesa is larger than a size of the through portion at a surface of the first semiconductor layer away from the second semiconductor layer.

[0009] In some embodiments, the through portions are distributed continuously or discontinuously.

[0010] In some embodiments, when looking down at the semiconductor stack from above the light-emitting diode, the opening of the through portion is circular or elliptical.

[0011] In some embodiments, when looking down at the semiconductor stack from above the light-emitting diode, the area of ​​the through portion accounts for 1% to 10% of the area of ​​the mesa.

[0012] In some embodiments, the cross-section of the through portion is trapezoidal, and the inclination angle of the through portion is less than 90 degrees.

[0013] In some embodiments, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the order from the bottom surface of the semiconductor stack to the top surface of the semiconductor stack is the P-type semiconductor layer, the light emitting layer, and the N-type semiconductor layer.

[0014] In some embodiments, the first sublayer includes a first contact electrode and a first metal electrode, the first contact electrode is located in the through-hole and directly contacts the N-type semiconductor layer, the first metal electrode is connected to the first contact electrode, and the first metal electrode is located on the mesa.

[0015] In some embodiments, the first sub-layer further includes a first filling electrode, the first filling electrode is located in the through-hole and connected to the first contact electrode, and the first metal electrode connects the first filling electrode and the first contact electrode.

[0016] In some embodiments, the second electrode includes a third sublayer and a fourth sublayer, the third sublayer directly contacts the P-type semiconductor layer, and the fourth sublayer is connected to the third sublayer.

[0017] In some embodiments, the light-emitting diode further includes an insulating layer, a bonding metal layer and a substrate, the insulating layer covers the side walls and lower surface of the semiconductor stack, the insulating layer has a first opening exposing the third sublayer, the upper surface of the bonding metal layer is connected to the third sublayer through the first opening, the substrate is connected to the lower surface of the bonding metal layer, and the fourth sublayer is connected to the substrate.

[0018] In some embodiments, the third sublayer includes a second contact electrode and a second metal electrode, the second contact electrode directly contacts the P-type semiconductor layer, and the second metal electrode is connected to the second contact electrode.

[0019] In some embodiments, a substrate is disposed between the second sub-layer and the first semiconductor layer, the substrate has a second opening exposing the first sub-layer, and the second sub-layer is connected to the first sub-layer through the second opening.

[0020] In some embodiments, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the order from the bottom surface of the semiconductor stack to the top surface of the semiconductor stack is the N-type semiconductor layer, the light emitting layer, and the P-type semiconductor layer.

[0021] In some embodiments, the first sublayer includes a first contact electrode and a first metal electrode, the first contact electrode is located in the through-hole and directly contacts the N-type semiconductor layer, the first metal electrode is connected to the first contact electrode, and the first metal electrode is located on the mesa.

[0022] In some embodiments, the first sub-layer further includes a first filling electrode, the first filling electrode is located in the through-hole and connected to the first contact electrode, and the first metal electrode connects the first filling electrode and the first contact electrode.

[0023] In some embodiments, the second electrode includes a third sublayer and a fourth sublayer, the third sublayer directly contacts the P-type semiconductor layer, the fourth sublayer is connected to the third sublayer, the third sublayer includes a second contact electrode and a second metal electrode, the second contact electrode directly contacts the P-type semiconductor layer, and the second metal electrode is connected to the second contact electrode.

[0024] In some embodiments, the light-emitting diode further includes an insulating layer, a bonding metal layer and a substrate, the insulating layer covers the side walls and upper surface of the semiconductor stack, the insulating layer has a first opening exposing the second electrode, the upper surface of the bonding metal layer is connected to the first sublayer, the substrate is connected to the lower surface of the bonding metal layer, and the second sublayer is connected to the substrate.

[0025] In some embodiments, a substrate is disposed between the bonding metal layer and the first semiconductor layer, the substrate has a second opening exposing the first sub-layer, and the bonding metal layer is connected to the first sub-layer through the second opening.

[0026] In some embodiments, the bonding metal layer includes a buffer layer and at least one set of composite connection layers stacked in sequence.

[0027] In some embodiments, the buffer layer includes Ti, and the thickness of the buffer layer ranges from 1000 to 5000 angstroms. The composite connection layer includes a Ni layer and a Sn layer, and the thickness of the composite connection layer ranges from 1000 to 10000 angstroms.

[0028] In some embodiments, the thickness of the substrate is 5-50 μm.

[0029] In some embodiments, the light emitting layer has a light emission wavelength of 220 to 300 nm.

[0030] The present invention further provides a light-emitting device, which uses the light-emitting diode described in any of the above embodiments.

[0031] An embodiment of the present invention provides a light emitting diode and a light emitting device. By disposing a through portion, the current injected through the first electrode can be injected from the sidewall of the first semiconductor layer, thereby reducing the operating voltage and improving product stability.

[0032] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1A is a structural schematic diagram of a light emitting diode according to a first embodiment of the present invention;

[0035] Figure 1B is a schematic top view of a semiconductor stack;

[0036] Figures 2 to 11 is a schematic structural diagram of the light emitting diode of the first embodiment at various stages in the manufacturing process;

[0037] Figure 12 is a schematic structural diagram of a light emitting diode according to a second embodiment of the present invention;

[0038] Figures 13 to 23 is a schematic structural diagram of the light emitting diode of the second embodiment at various stages in the manufacturing process;

[0039] Figure 24 is a schematic top view of a semiconductor stack according to another embodiment of the present invention;

[0040] Figure 25 1 is a schematic top view of a semiconductor stack according to another embodiment of the present invention.

[0041] Reference numerals:

[0042] 10-substrate; 12-semiconductor stack; 121-table; 122-lower surface; 123-upper surface; 124-first semiconductor layer; 125-light-emitting layer; 126-second semiconductor layer; 14-through portion; 16-insulating layer; 18-bonding metal layer; 20-substrate; 21-first electrode; 211-first contact electrode; 212-first filling electrode; 213-first metal electrode; 22-second electrode; 221-second contact electrode; 222-second metal electrode; 41-first opening; 42-second opening; 44-temporary bonding glue; 46-temporary substrate; 71-first sublayer; 72-second sublayer; 73-third sublayer; 74-fourth sublayer. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0044] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof all mean "at least including".

[0045] See also Figure 1A , Figure 1A is a schematic structural diagram of a light emitting diode according to a first embodiment of the present invention. Figure 1Bis a schematic top view of a semiconductor stack. To achieve at least one of the aforementioned advantages or other advantages, a first embodiment of the present invention provides a light-emitting diode. As shown in the figure, the light-emitting diode may include a semiconductor stack 12, a first electrode 21, and a second electrode 22.

[0046] The semiconductor stack 12 is disposed on a substrate 10, which may be an insulating substrate. Preferably, the substrate 10 may be made of a transparent or translucent material. In the illustrated embodiment, the substrate 10 is a sapphire substrate. In some embodiments, the substrate 10 may be a patterned sapphire substrate, but the present invention is not limited thereto. The substrate 10 may also be made of a conductive material or a semiconductor material. For example, the substrate 10 material may include at least one of silicon carbide, silicon, magnesium aluminum oxide, magnesium oxide, lithium aluminum oxide, aluminum gallium oxide, and gallium nitride.

[0047] The semiconductor stack 12 has a mesa 121, an opposing lower surface 122, and an upper surface 123. The semiconductor stack 12 includes a first semiconductor layer 124, a light-emitting layer 125, and a second semiconductor layer 126. The light-emitting layer 125 is located between the first semiconductor layer 124 and the second semiconductor layer 126. The mesa 121 refers to the surface of the first semiconductor layer 124 that is not covered by the light-emitting layer 125 (this surface is the surface of the first semiconductor layer 124 on the side close to the light-emitting layer 125). The first semiconductor layer 124 has a through portion 14 at the mesa 121. The through portion 14 completely penetrates the first semiconductor layer 124, that is, the through portion 14 extends from the upper surface of the first semiconductor layer 124 to the lower surface of the first semiconductor layer 124.

[0048] The first semiconductor layer 124 may be an N-type semiconductor layer that can provide electrons to the light-emitting layer 125 under the action of a power source. In some embodiments, the first semiconductor layer 124 includes an N-type doped nitride layer. The N-type doped nitride layer may include one or more N-type impurities of Group IV elements. The N-type impurities may include one or a combination of Si, Ge, and Sn.

[0049] The light-emitting layer 125 may be a quantum well structure (Quantμm Well, abbreviated as QW). In some embodiments, the light-emitting layer 125 may also be a multiple quantum well structure (Multiple Quantμm Well, abbreviated as MQW), wherein the multiple quantum well structure includes multiple quantum well layers (Well) and multiple quantum barrier layers (Barrier) alternately arranged in a repeated manner, for example, it may be a multiple quantum well structure of GaN / AlGaN, InAlGaN / InAlGaN or InGaN / AlGaN. In addition, the composition and thickness of the well layer in the light-emitting layer 125 determine the wavelength of the generated light. In order to improve the luminous efficiency of the light-emitting layer 125, it can be achieved by changing the depth of the quantum well, the number of layers, thickness and / or other features of the paired quantum wells and quantum barriers in the light-emitting layer 125. In some embodiments, the light-emitting diode is an ultraviolet diode, and the emission wavelength of the light-emitting layer 125 may be 220 to 300 nm.

[0050] The second semiconductor layer 126 can be a P-type semiconductor layer, which can provide holes to the light-emitting layer 125 under the action of a power supply. In some embodiments, the second semiconductor layer 126 includes a P-type doped nitride layer. The P-type doped nitride layer may include one or more P-type impurities of Group II elements. The P-type impurities may include one or a combination of Mg, Zn, and Be. The second semiconductor layer 126 can be a single-layer structure or a multi-layer structure having different compositions. In addition, the configuration of the semiconductor stack 12 is not limited thereto, and other types of semiconductor stacks 12 can be selected based on actual needs.

[0051] The first electrode 21 is at least arranged in the through-hole 14 to electrically connect to the first semiconductor layer 124. Thereby, the first electrode 21 is in direct contact with the side wall of the first semiconductor layer 124, so that the current injected through the first electrode 21 can be injected from the side wall of the first semiconductor layer 124, thereby reducing the operating voltage and improving product stability. Preferably, the first electrode 21 can extend upward from the through-hole 14 to cover the surface of the first semiconductor layer 124 (the surface of the first semiconductor layer 124 on the side close to the light-emitting layer 125), further improving the overall structural connection strength and the electrical characteristics of the first electrode 21. The first electrode 21 can be a single-layer, double-layer or multi-layer structure, for example: a stacked structure of Ti / Al, Ti / Al / Ti / Au, Ti / Al / Ni / Au, V / Al / Pt / Au, etc.

[0052] The second electrode 22 is electrically connected to the second semiconductor layer 126. The second electrode 22 can be made of a transparent conductive material or a metal material, and can be adaptively selected according to the doping conditions of the surface layer of the second semiconductor layer 126 (such as the p-type GaN surface layer). In some embodiments, the second contact electrode 221 is made of a transparent conductive material, which may include indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium doped zinc oxide (GZO), tungsten doped indium oxide (IWO), or zinc oxide (ZnO), but the embodiments of the present disclosure are not limited thereto.

[0053] In some embodiments, taking into account the problem of reflected light and the current level of process manufacturing, the size of the through portion 14 at the table 121 is larger than the size of the through portion 14 at the surface of the first semiconductor layer 124 away from the second semiconductor layer 126, which can enhance the reflective effect and strengthen the light-emitting performance of the light-emitting diode. Preferably, the cross-sectional shape of the through portion 14 is trapezoidal, and the inclination angle of the through portion 14 is less than 90 degrees, preferably in the range of 30 to 60 degrees, to further enhance the light-emitting performance of the light-emitting diode. When plating the electrode layer (such as the first electrode 21), if the side wall of the through portion 14 is a vertical edge (the angle is 90 degrees), there will be a problem of uneven plating at the corners of the through portion 14.

[0054] In some embodiments, when looking down at the semiconductor stack 12 from above the light emitting diode, Figure 1B As shown, the opening of the through portion 14 is circular or elliptical, and a design close to a circular shape is more suitable to improve current transmission. The distribution of the through portions 14 is discontinuous, which reduces the number of mesas 121 and improves the light output effect of the LED.

[0055] In some embodiments, when looking down at the semiconductor stack 12 from above the light emitting diode, Figure 1B As shown ( Figure 1BThe shaded area in the figure represents the area of ​​the mesa 121. The area of ​​the through-portion 14 accounts for 1% to 10% of the area of ​​the mesa 121. That is, the area of ​​the through-portion 14 projected onto the upper surface of the substrate 10 accounts for 1% to 10% of the area of ​​the mesa 121 projected onto the upper surface of the substrate 10. This ensures current transmission. If the area of ​​the through-portion 14 is too large, it will lead to uneven current and uneven light output. Preferably, the area of ​​the through-portion 14 accounts for 1% to 5% of the area of ​​the mesa 121.

[0056] In this embodiment, the first semiconductor layer 124 is an N-type semiconductor layer, the second semiconductor layer 126 is a P-type semiconductor layer, and the P-type semiconductor layer, the light-emitting layer 125 and the N-type semiconductor layer are arranged in order from the lower surface 122 of the semiconductor stack 12 to the upper surface 123 of the semiconductor stack 12 .

[0057] The first electrode 21 includes a first sublayer 71 and a second sublayer 72. The first sublayer 71 is disposed within the through-hole 14 and on the mesa 121, and the second sublayer 72 is disposed on the back side of the mesa 121 (the back side of the mesa refers to the surface of the first semiconductor layer 124 away from the light-emitting layer 125). The first sublayer 71 and the second sublayer 72 are electrically connected through the through-hole 14. The second sublayer 72 is a pad electrode.

[0058] The first sublayer 71 includes a first contact electrode 211, a first filling electrode 212, and a first metal electrode 213. The first contact electrode 211 is located within the through-hole 14 and directly contacts the N-type semiconductor layer (the first semiconductor layer 124). The first filling electrode 212 is located within the through-hole 14 and connects to the first contact electrode 211. The first metal electrode 213 connects the first filling electrode 212 and the first contact electrode 211. The first metal electrode 213 is located on the mesa 121.

[0059] The second electrode 22 includes a third sublayer 73 and a fourth sublayer 74. The third sublayer 73 directly contacts the P-type semiconductor layer, and the fourth sublayer 74 is connected to the third sublayer 73 and serves as a pad electrode. The third sublayer 73 includes a second contact electrode 221 and a second metal electrode 222. The second contact electrode 221 directly contacts the P-type semiconductor layer, and the second metal electrode 222 is connected to the second contact electrode 221.

[0060] The light-emitting diode further includes an insulating layer 16, a bonding metal layer 18, and a substrate 20. The insulating layer 16 covers the sidewalls and lower surface 122 of the semiconductor stack 12 and has a first opening 41 exposing the second electrode 22. The upper surface of the bonding metal layer 18 is connected to the second electrode 22 through the first opening 41. The substrate 20 is connected to the lower surface of the bonding metal layer 18. The second sublayer 72 is connected to the first electrode 21. The fourth sublayer 74 is connected to the substrate 20.

[0061] The substrate 10 disposed between the second sub-layer 72 and the first semiconductor layer 124 has a second opening 42 exposing the first electrode 21 . The second sub-layer 72 is connected to the first sub-layer 71 through the second opening 42 .

[0062] The following discloses a method for making Figure 1A The LED method shown is shown in Figures 2 to 11 , Figures 2 to 11 1 is a schematic structural diagram of the light emitting diode of the first embodiment at various stages in the manufacturing process.

[0063] like Figure 2 As shown, a semiconductor stack 12 is first grown on a substrate 10, that is, a first semiconductor layer 124, a light emitting layer 125, and a second semiconductor layer 126 are sequentially grown on the substrate 10. Thereafter, the substrate 10 may be ground and polished to reduce warping of the sapphire substrate 10.

[0064] like Figure 3 As shown, the second semiconductor layer 126 and the light-emitting layer 125 are first etched away on the semiconductor stack 12 by means of a mask, dry etching, etc. to expose the first semiconductor layer 124 to form a mesa 123, and then a portion of the first semiconductor layer 124 at the mesa 121 is completely penetrated to form a through portion 14, and the outer portion of the semiconductor stack 12 is removed to expose the surface of the substrate 10, thereby isolating the single core particle.

[0065] like Figure 4 As shown, a first contact electrode 211 is deposited for the first semiconductor layer 124, followed by metal lift-off and subsequent fusion bonding, thereby forming an ohmic contact between the first contact electrode 211 and the first semiconductor layer 124. Furthermore, a second contact electrode 221 is deposited on the second semiconductor layer 126 using a negative photoresist and a yellow photolithography process, thereby forming an ohmic contact between the second contact electrode 221 and the second semiconductor layer 126. The second contact electrode 221 can be a transparent current spreading electrode made of 200 angstroms thick ITO. The ITO film is then stripped and fused to form an ohmic contact between the second semiconductor layer 126 and the ITO.

[0066] like Figure 5 As shown, in conjunction with the photolithography process, a first filling electrode 212 is deposited on the first contact electrode 211 to fill the holes formed by the first contact electrode 211, ensuring a flat surface and allowing for subsequent use with the first metal electrode 213. However, in some embodiments, the first filling electrode 212 may be omitted, that is, replaced by the first metal electrode 213. However, the lack of the first filling electrode 212 may cause the electrode at the through portion 14 to become concave, thereby increasing the void ratio.

[0067] like Figure 6 As shown, a negative photoresist is applied over the first contact electrode 211 and the first fill electrode 212, and a first metal electrode 213 is deposited using a yellow photolithography process. Furthermore, a negative photoresist is applied over the second contact electrode 221, and a second metal electrode 222 is deposited using a yellow photolithography process. The first metal electrode 213 and the second metal electrode 222 can have a multilayer structure of Cr / Al / Cr / Pt / Ti.

[0068] like Figure 7 As shown, PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to deposit an insulating material to form an insulating layer 16. Insulating layer 16 covers the sidewalls and lower surface 122 of semiconductor stack 12, and also covers the sidewalls of first metal electrode 213 and second metal electrode 222. Subsequently, a wet BOE etching or dry etching process is used to form a first opening 41 in insulating layer 16 to expose second metal electrode 222 (second electrode 22). Insulating layer 16 can include SiO2 and can be 10,000 angstroms thick.

[0069] like Figure 8 As shown, a bonding metal layer 18 for bonding is plated on the insulating layer 16 and the second metal electrode 222 to facilitate the subsequent bonding process. The bonding metal layer 18 includes a buffer layer and at least one group of composite connection layers stacked in sequence. The buffer layer mainly plays a buffering role and can be made of Ti metal; the composite connection layer mainly plays a bonding role and can be made of Ni / Sn bonding element pairs, with the number of Ni / Sn pairs preferably being 1 to 3 pairs. The thickness of the buffer layer ranges from 1000 to 5000 angstroms; the thickness of the composite connection layer ranges from 1000 to 10000 angstroms. For example, the bonding metal layer 18 can include a Ti layer, a first Ni layer, a first Sn layer, a second Ni layer, and a second Sn layer stacked in sequence, that is, the bonding metal layer 18 is a multilayer structure of Ti / Ni / Sn / Ni / Sn, and a group of Ni / Sn constitutes a group of composite connection layers. However, the present invention is not limited thereto, and the bonding metal layer 18 may also be formed of a bonding element pair of In / Au or Au / Au, which may also achieve a bonding effect. However, in comparison, the multilayer structure of Ti / Ni / Sn / Ni / Sn not only has a better bonding effect, but also has a relatively lower risk of damage in subsequent processes.

[0070] like Figure 9As shown, a substrate 20 is provided on the bonding metal layer 18. The substrate 20 serves as a permanent substrate 20 and plays the role of supporting the entire light-emitting diode. The substrate 20 can be a silicon substrate 20. By transferring the diode to the silicon substrate 20, a vertical structure is formed to improve heat dissipation, thereby increasing the ability of the light-emitting diode to inject large currents and thus improving brightness. Subsequently, the size of the required components is defined by using a yellow light process and a focusing method with dual lenses of different focal points, and hard baking is performed to obtain the required size of the light-emitting diode. Preferably, the substrate 10 that has completed the bonding process is ground to 5 to 50 μm, preferably 5 to 20 μm, to increase the heat dissipation capacity.

[0071] like Figure 10 As shown, the substrate 10 is etched by dry etching or the like to form a second opening 42 through the substrate 10 to expose the first contact electrode 211 located in the through portion 14 .

[0072] like Figure 11 As shown, a second sub-layer 72 is plated on the substrate 10, and the second sub-layer 72 is connected to the first contact electrode 211 through the second opening 42. In addition, a metal electrode is plated on the back of the substrate 20 to form a fourth sub-layer 74. In this way, a positive electrode pad and a negative electrode pad are formed.

[0073] The above is only a public one for making Figure 1A The method for producing a light emitting diode shown in the figure is not limited to the present invention and is merely used to illustrate a method for producing a light emitting diode.

[0074] See also Figure 12 , Figure 12 is a schematic structural diagram of the light emitting diode according to the second embodiment of the present invention. Figure 1A As for the light-emitting diode shown in the first embodiment, in this embodiment, the first semiconductor layer 124 is an N-type semiconductor layer, the second semiconductor layer 126 is a P-type semiconductor layer, and the direction from the lower surface 122 of the semiconductor stack 12 to the upper surface 123 of the semiconductor stack 12 is the N-type semiconductor layer, the light-emitting layer 125 and the P-type semiconductor layer in sequence.

[0075] The first sublayer 71 includes a first contact electrode 211, a first filling electrode 212, and a first metal electrode 213. The first contact electrode 211 is located within the through-hole 14 and directly contacts the N-type semiconductor layer. The first filling electrode 212 is located within the through-hole 14 and connects to the first contact electrode 211. The first metal electrode 213 connects the first filling electrode 212 and the first contact electrode 211. The first metal electrode 213 is located on the mesa 121.

[0076] The second electrode 22 includes a third sublayer 73 and a fourth sublayer 74. The third sublayer 73 directly contacts the P-type semiconductor layer, and the fourth sublayer 74 connects to the third sublayer 73. The third sublayer 73 includes a second contact electrode 221 and a second metal electrode 222.

[0077] The second contact electrode 221 directly contacts the P-type semiconductor layer, and the second metal electrode 222 is connected to the second contact electrode 221 .

[0078] The light-emitting diode further includes an insulating layer 16, a bonding metal layer 18, and a substrate 20. The insulating layer 16 covers the sidewalls and upper surface 123 of the semiconductor stack 12. The insulating layer 16 has a first opening 41 exposing the second electrode 22. The upper surface of the bonding metal layer 18 is connected to the first electrode 21. The substrate 20 is connected to the lower surface of the bonding metal layer 18. The second sublayer 72 is connected to the substrate 20. The substrate 10 disposed between the bonding metal layer 18 and the first semiconductor layer 124 has a second opening 42 exposing the first electrode 21. The bonding metal layer 18 is connected to the first electrode 21 through the second opening 42.

[0079] The following discloses a method for making Figure 12 The LED method shown is shown in Figures 13 to 23 , Figures 13 to 23 1 is a schematic structural diagram of the light emitting diode of the second embodiment at various stages in the manufacturing process.

[0080] like Figure 13 As shown, a semiconductor stack 12 is first grown on a substrate 10, that is, a first semiconductor layer 124, a light emitting layer 125, and a second semiconductor layer 126 are sequentially grown on the substrate 10. Thereafter, the substrate 10 may be ground and polished to reduce warping of the sapphire substrate 10.

[0081] like Figure 14 As shown, the second semiconductor layer 126 and the light-emitting layer 125 are first etched away on the semiconductor stack 12 by means of a mask, dry etching, etc. to expose the first semiconductor layer 124 to form a mesa 123, and then a portion of the first semiconductor layer 124 at the mesa 121 is completely penetrated to form a through portion 14, and the outer portion of the semiconductor stack 12 is removed to expose the surface of the substrate 10, thereby isolating the single core particle.

[0082] like Figure 15As shown, a first contact electrode 211 is deposited for the first semiconductor layer 124, followed by metal lift-off and subsequent fusion bonding, thereby forming an ohmic contact between the first contact electrode 211 and the first semiconductor layer 124. Furthermore, a second contact electrode 221 is deposited on the second semiconductor layer 126 using a negative photoresist and a yellow photolithography process, thereby forming an ohmic contact between the second contact electrode 221 and the second semiconductor layer 126. The second contact electrode 221 can be a transparent current spreading electrode made of 200 angstroms thick ITO. The ITO film is then stripped and fused to form an ohmic contact between the second semiconductor layer 126 and the ITO.

[0083] like Figure 16 As shown, in conjunction with the photolithography process, a first filling electrode 212 is deposited on the first contact electrode 211 to fill the hole formed by the first contact electrode 211 to ensure surface flatness and to be used in conjunction with the subsequent first metal electrode 213 .

[0084] like Figure 17 As shown, a negative photoresist is applied over the first contact electrode 211 and the first fill electrode 212, and a first metal electrode 213 is deposited using a yellow photolithography process. Furthermore, a negative photoresist is applied over the second contact electrode 221, and a second metal electrode 222 is deposited using a yellow photolithography process. The first metal electrode 213 and the second metal electrode 222 can have a multilayer structure of Cr / Al / Cr / Pt / Ti.

[0085] like Figure 18 As shown, PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to deposit an insulating material to form an insulating layer 16. Insulating layer 16 covers the sidewalls and lower surface 122 of semiconductor stack 12, and also covers the sidewalls of first metal electrode 213 and second metal electrode 222. Subsequently, a wet BOE etching or dry etching process is used to form a first opening 41 in insulating layer 16 to expose second metal electrode 222 (second electrode 22). Insulating layer 16 can include SiO2 and can be 10,000 angstroms thick.

[0086] like Figure 19 As shown, the temporary bonding adhesive 44 is evenly coated on the insulating layer 16 and the second metal electrode 222 by spin coating to perform a bonding process.

[0087] like Figure 20 As shown, a temporary substrate 46 is disposed on the temporary bonding adhesive 44 to facilitate subsequent processes.

[0088] like Figure 21As shown, the substrate 10 is etched by dry etching or the like to form a second opening 42 through the substrate 10 to expose the first contact electrode 211 located in the through portion 14 .

[0089] like Figure 22 As shown, a bonding metal layer 18 is plated on the substrate 10 for bonding. The bonding metal layer 18 connects to the first contact electrode 211 through the second opening 42 to facilitate subsequent processing. The bonding metal layer 18 includes a buffer layer and at least one set of composite connection layers stacked in sequence. The buffer layer primarily serves as a buffer and can be made of Ti metal; the composite connection layer primarily serves as a bonding layer and can be made of Ni / Sn bonding element pairs, with the number of Ni / Sn pairs preferably being 1 to 3. The buffer layer has a thickness ranging from 1000 to 5000 angstroms; the composite connection layer has a thickness ranging from 1000 to 10000 angstroms. For example, the bonding metal layer 18 can include a Ti layer, a first Ni layer, a first Sn layer, a second Ni layer, and a second Sn layer stacked in sequence, i.e., the bonding metal layer 18 has a multilayer structure of Ti / Ni / Sn / Ni / Sn, with a set of Ni / Sn layers constituting a set of composite connection layers. However, the present invention is not limited thereto, and the bonding metal layer 18 may also be formed of a bonding element pair of In / Au or Au / Au, which may also achieve a bonding effect. However, in comparison, the multilayer structure of Ti / Ni / Sn / Ni / Sn not only has a better bonding effect, but also has a relatively lower risk of damage in subsequent processes.

[0090] Next, a substrate 20 is set on the back side of the bonding metal layer 18. The substrate 20 serves as a permanent substrate 20 to support the entire light-emitting diode. The substrate 20 can be a silicon substrate 20. By transferring the diode to the silicon substrate 20, a vertical structure is formed to improve heat dissipation, thereby increasing the ability of the light-emitting diode to inject large currents and thus improving brightness. Subsequently, a yellow light process is used to define the size of the required components using a dual-lens focusing method with different focal points, and hard baking is performed to obtain the required size of the light-emitting diode. Preferably, the substrate 10 that has completed the bonding process is ground to 5 to 50 μm, preferably 5 to 20 μm, to increase heat dissipation capacity.

[0091] like Figure 23 As shown, the temporary substrate 46 and the temporary bonding adhesive 44 are removed, and a second sub-layer 72 is plated on the back of the substrate 20, and a fourth sub-layer 74 is plated on the second metal electrode 222. In this way, the positive electrode pad and the negative electrode pad are formed.

[0092] The above is only a public one for making Figure 12 The method for producing a light emitting diode shown in the figure is not limited to the present invention and is merely used to illustrate a method for producing a light emitting diode.

[0093] It should be noted that the production Figure 12 Method and method of making a light emitting diode Figure 1A Compared with the light emitting diode method, Figure 1A The light emitting diode only needs to be flipped once, and there is no need to set up a temporary substrate 46, so the process is relatively simple; Figure 12 The advantage of the light-emitting diode is that the prepared light-emitting diode has the same structure as a conventional LED, such as a P-type semiconductor layer on the top and an N-type semiconductor layer on the bottom (the substrate 20 can be used as a reference surface), and has high applicability.

[0094] It should be noted that in some embodiments, the substrate 10 may not be provided, but the entire substrate 10 may be directly removed. A buffer layer may be provided at the first semiconductor layer 124 to facilitate etching of the substrate 10 and avoid over-etching. However, retaining the substrate 10 can eliminate the need for laser lift-off. The thickness of the retained substrate 10 can be based on 5 μm, subject to the actual grinding machine, such as a grinding machine with an error of 1 μm. Because the substrate 10 is retained, there is no need for laser lift-off, so the semiconductor stack 12 will not cause erroneous epitaxial layer separation or cracking due to laser energy absorption problems.

[0095] The distribution form of the through-holes 14 can also be continuous distribution, such as Figure 24 and Figure 25 As shown, the through portion 14 is distributed in the form of two independent and continuously distributed through portions 14 . In addition, in some embodiments, the through portion 14 may also be a whole continuously distributed through portion 14 .

[0096] In some embodiments, the insulating layer 16 has different functions depending on the location involved. For example, when the insulating layer 16 covers the sidewalls of the semiconductor stack 12, it can be used to prevent the first semiconductor layer 124 and the second semiconductor layer 126 from being electrically connected due to leakage of conductive material, thereby reducing the short-circuit anomaly of the diode, but the embodiments of the present disclosure are not limited to this. The material of the insulating layer 16 includes a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. The inorganic material may include silica gel. The dielectric material includes an electrically insulating material such as aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating layer 16 may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof. The combination may be, for example, a Bragg reflector (DBR) formed by repeatedly stacking two materials with different refractive indices.

[0097] The present invention further provides a light-emitting device, which uses the light-emitting diode described in any of the above embodiments.

[0098] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention may be improved in only one or several aspects, without having to simultaneously solve all the technical problems listed in the prior art or background art. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as limiting the claim.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: A semiconductor stack having a mesa, an opposing lower surface, and an upper surface, the semiconductor stack including a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, the light-emitting layer being located between the first semiconductor layer and the second semiconductor layer, the mesa being a surface of the first semiconductor layer not covered by the light-emitting layer, wherein the first semiconductor layer has a through portion at the mesa, the through portion extending from the upper surface of the first semiconductor layer to the lower surface of the first semiconductor layer; a first electrode, disposed at least in the through-hole to electrically connect the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; The light-emitting diode further includes an insulating layer, a bonding metal layer and a substrate, wherein the insulating layer covers the side walls and lower surface of the semiconductor stack, the insulating layer has a first opening exposing the second electrode, the upper surface of the bonding metal layer is connected to the second electrode through the first opening, and the substrate is connected to the lower surface of the bonding metal layer.

2. The light emitting diode according to claim 1, wherein: The first electrode includes a first sublayer and a second sublayer. The first sublayer is disposed in the through-hole and on the mesa. The second sublayer is disposed on the back side of the mesa. The first sublayer and the second sublayer are electrically connected through the through-hole.

3. The light emitting diode according to claim 1, wherein: A size of the through portion at the mesa is larger than a size of the through portion at a surface of the first semiconductor layer away from the second semiconductor layer.

4. The light emitting diode according to claim 1, wherein: The through portions are distributed continuously or discontinuously.

5. The light emitting diode according to claim 1, wherein: When looking down at the semiconductor stack from above the light emitting diode, the opening of the through portion is circular or elliptical.

6. The light emitting diode according to claim 1, wherein: When looking down at the semiconductor stack from above the light-emitting diode, the area of ​​the through portion occupies 1% to 10% of the area of ​​the mesa.

7. The light emitting diode according to claim 1, wherein: The cross-section of the through portion is trapezoidal, and the inclination angle of the through portion is less than 90 degrees.

8. The light emitting diode according to claim 2, wherein: The first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the P-type semiconductor layer, the light emitting layer, and the N-type semiconductor layer are arranged in order from the lower surface of the semiconductor stack to the upper surface of the semiconductor stack.

9. The light emitting diode according to claim 8, characterized in that: The first sublayer includes a first contact electrode and a first metal electrode. The first contact electrode is located in the through-hole and directly contacts the N-type semiconductor layer. The first metal electrode is connected to the first contact electrode. The first metal electrode is located on the mesa.

10. The light emitting diode according to claim 9, characterized in that: The first sub-layer further includes a first filling electrode, which is located in the through-hole and connected to the first contact electrode. The first metal electrode connects the first filling electrode and the first contact electrode.

11. The light emitting diode according to claim 8, characterized in that: The second electrode includes a third sublayer and a fourth sublayer, the third sublayer directly contacts the P-type semiconductor layer, and the fourth sublayer is connected to the third sublayer.

12. The light emitting diode according to claim 11, characterized in that: The upper surface of the bonding metal layer is connected to the third sub-layer through the first opening, and the fourth sub-layer is connected to the substrate.

13. The light emitting diode according to claim 11, wherein: The third sub-layer includes a second contact electrode and a second metal electrode, the second contact electrode directly contacts the P-type semiconductor layer, and the second metal electrode is connected to the second contact electrode.

14. The light emitting diode according to claim 8, characterized in that: A substrate is provided between the second sub-layer and the first semiconductor layer. The substrate has a second opening exposing the first sub-layer. The second sub-layer is connected to the first sub-layer through the second opening.

15. A light emitting diode, characterized in that: The light emitting diode comprises: A semiconductor stack having a mesa, an opposing lower surface, and an upper surface, the semiconductor stack including a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, the light-emitting layer being located between the first semiconductor layer and the second semiconductor layer, the mesa being a surface of the first semiconductor layer not covered by the light-emitting layer, wherein the first semiconductor layer has a through portion at the mesa, the through portion extending from the upper surface of the first semiconductor layer to the lower surface of the first semiconductor layer; a first electrode, disposed at least in the through-hole to electrically connect the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; The light-emitting diode further includes an insulating layer, a bonding metal layer and a substrate, wherein the insulating layer covers the side walls and upper surface of the semiconductor stack, the insulating layer has a first opening exposing the second electrode, the upper surface of the bonding metal layer is connected to the first electrode, and the substrate is connected to the lower surface of the bonding metal layer.

16. The light emitting diode according to claim 15, characterized in that: The first electrode includes a first sublayer and a second sublayer, the first sublayer is arranged in the through-hole and on the table, the second sublayer is arranged on the back side of the table, the first sublayer and the second sublayer are electrically connected through the through-hole, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the direction from the lower surface of the semiconductor stack to the upper surface of the semiconductor stack are the N-type semiconductor layer, the light-emitting layer and the P-type semiconductor layer in order.

17. The light emitting diode according to claim 16, characterized in that: The first sublayer includes a first contact electrode and a first metal electrode. The first contact electrode is located in the through-hole and directly contacts the N-type semiconductor layer. The first metal electrode is connected to the first contact electrode. The first metal electrode is located on the mesa.

18. The light emitting diode according to claim 17, characterized in that: The first sub-layer further includes a first filling electrode, which is located in the through-hole and connected to the first contact electrode. The first metal electrode connects the first filling electrode and the first contact electrode.

19. The light emitting diode according to claim 16, wherein: The second electrode includes a third sublayer and a fourth sublayer, the third sublayer directly contacts the P-type semiconductor layer, the fourth sublayer is connected to the third sublayer, the third sublayer includes a second contact electrode and a second metal electrode, the second contact electrode directly contacts the P-type semiconductor layer, and the second metal electrode is connected to the second contact electrode.

20. The light emitting diode according to claim 16, wherein: The upper surface of the bonding metal layer is connected to the first sub-layer, and the second sub-layer is connected to the substrate.

21. The light emitting diode according to claim 16, wherein: A substrate is provided between the bonding metal layer and the first semiconductor layer. The substrate has a second opening exposing the first sub-layer. The bonding metal layer is connected to the first sub-layer through the second opening.

22. The light emitting diode according to claim 1 or 15, characterized in that: The bonding metal layer includes a buffer layer and at least one group of composite connection layers stacked in sequence.

23. The light emitting diode according to claim 22, characterized in that: The material of the buffer layer includes Ti, and the thickness of the buffer layer ranges from 1000 to 5000 angstroms. The composite connection layer includes a Ni layer and a Sn layer, and the thickness of the composite connection layer ranges from 1000 to 10000 angstroms.

24. The light emitting diode according to claim 14 or 21, characterized in that: The thickness of the substrate is 5 to 50 microns.

25. The light emitting diode according to claim 1 or 15, characterized in that: The light-emitting layer has a light-emitting wavelength of 220 to 300 nanometers.

26. A light emitting device, characterized in that: The light emitting device adopts the light emitting diode according to any one of claims 1 to 25.

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