High-sensitivity ultrasonic preamplifier for rock deformation experiments at high temperature and high pressure

Abstract

The invention discloses a high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments. The high-sensitivity ultrasonic preamplifier comprises an input-end signal amplitude limiting and current limiting protection circuit, a first-stage amplification circuit, a second-stage amplification circuit, a third-stage amplification circuit, and a power supply filter circuit. One end of the input-end signal amplitude limiting and current limiting protection circuit is connected to an external piezoelectric sensor, the other end of the input-end signal amplitude limiting and current limiting protection circuit is connected to one end of the first-stage amplification circuit, the other end of the first-stage amplification circuit is connected to one end of the third-stage amplification circuit via the second-stage amplification circuit, and the other end of the third-stage amplification circuit is connected to an output port. The power supply filter circuit is respectively connected to the first-stage amplification circuit, the second-stage amplification circuit, and the third-stage amplification circuit.

Description

Technical Field

[0001] The present invention relates to the field of geological research, and in particular to a high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments. Background Art

[0002] The composition, physical and chemical properties, structure, and changing patterns of the deep crust are both hot and challenging areas of geophysical research. Because researchers cannot directly observe deep Earth materials, they must rely on geophysical exploration methods, such as indicators like rock velocity, to infer information about the deep crust's materials and structures. Deep crustal rocks are often exposed to high temperatures (>=200°C) and high pressures (MPa to GPa). This necessitates the use of high-temperature and high-pressure vessels to pressurize and heat rock samples in the laboratory, mimicking the real-world deep crustal environment as closely as possible. Real-time rock velocity is often used to characterize the changing physical properties of rock samples during high-temperature and high-pressure deformation experiments. Acquiring this real-time velocity often requires an ultrasonic preamplifier to capture ultrasonic echo signals with a good signal-to-noise ratio. Therefore, the ultrasonic preamplifier is crucial to the success of high-temperature and high-pressure rock velocity experiments.

[0003] Due to limitations in the size of high-temperature and high-pressure vessels and experimental environmental conditions, researchers must meet the following experimental conditions to obtain the real-time wave velocity of rock samples during experiments:

[0004] (1) Rock samples are usually installed in high-temperature and high-pressure containers during experiments. Therefore, researchers must use high-pressure and high-temperature resistant piezoelectric materials as sensors to obtain ultrasonic information from rock samples. Usually, the acoustic impedance of high-pressure and high-temperature resistant piezoelectric materials is high, and the ultrasonic echo charge obtained by the sensor is very weak (μV to mV level). This requires an ultrasonic preamplifier with high amplification factor (amplification factor of more than 1000 times) and high sensitivity (input impedance MΩ level) to amplify the original weak ultrasonic signal to a voltage range that can be picked up by the collector, thereby obtaining clear ultrasonic echo arrival information and accurately locating the echo arrival position.

[0005] (2) In addition to installing rock samples, most small-sized high-temperature and high-pressure containers can only install one ultrasonic sensor. Therefore, in addition to picking up the original weak ultrasonic echo signal, the single ultrasonic sensor in the container also serves to transmit high-power and high-voltage (1A current and 100V voltage or above) ultrasonic excitation signals. This requires the ultrasonic preamplifier to have a transmit / receive switching function, which can be in a high-resistance state when the high-voltage and high-power excitation pulse is transmitted from the transmission channel of the external collector and loaded into the sensor in the container, thereby protecting the weak current analog circuit connected to the back end of the ultrasonic preamplifier from being damaged by the high-voltage and high-power pulse; and can switch to the receiving state in time when the high-voltage and high-power excitation pulse disappears, and receive the weak ultrasonic echo charge information returned by the sensor.

[0006] (3) The operating space of the high-temperature and high-pressure mechanical loading device matched with the high-temperature and high-pressure container is generally very limited. In order to save space and simplify operation, the ultrasonic preamplifier must also have the function of coaxial power supply, that is, the ability to transmit the amplified ultrasonic signal and the amplifier power supply on a coaxial cable at the same time, avoiding external power supply and simplifying the circuit.

[0007] Currently, the general ultrasonic preamplifiers sold on the market are not suitable for high-temperature and high-pressure rock deformation experiments. The main problems are:

[0008] (1) The amplification factor is not enough (up to 1000 times), resulting in low sensitivity of the amplifier, making it difficult to effectively obtain clear information about the arrival time of the ultrasonic echo of the piezoelectric sensor, resulting in misjudgment of the echo arrival time.

[0009] (2) It does not have the transmit / receive switching function and does not meet the requirements of the high-temperature and high-pressure rock deformation experiment where only one ultrasonic probe can be installed in the limited container space to simultaneously transmit high-voltage pulses and receive weak ultrasonic echo signals.

[0010] (3) Most ultrasonic preamplifiers do not have a coaxial power supply function and require an external power supply, which makes the entire instrument larger and more complicated to operate; or they have a built-in 220V power supply conversion circuit, but the entire amplifier is large and bulky, lacking in convenience.

[0011] In summary, it is necessary to study a high-sensitivity ultrasonic preamplifier that can be used for wave velocity measurement in high-temperature and high-pressure rock deformation experiments to meet the above experimental requirements. Summary of the Invention

[0012] The purpose of the present invention is to solve the above problems and provide a high-sensitivity ultrasonic preamplifier for rock high-temperature and high-pressure deformation experiments, which improves the ultrasonic echo signal pickup effect.

[0013] In order to achieve the above object, the technical solution of the present invention is:

[0014] A high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments includes an input signal limiting and current limiting protection circuit, a first-stage amplification circuit, a second-stage amplification circuit, a third-stage amplification circuit, and a power supply filter circuit; one end of the input signal limiting and current limiting protection circuit is connected to an external piezoelectric sensor, the other end of the input signal limiting and current limiting protection circuit is connected to one end of the first-stage amplification circuit, the other end of the first-stage amplification circuit is connected to one end of the third-stage amplification circuit via the second-stage amplification circuit, and the other end of the third-stage amplification circuit is connected to an output port; the power supply filter circuit is respectively connected to the first-stage amplification circuit, the second-stage amplification circuit, and the third-stage amplification circuit.

[0015] Furthermore, the input signal limiting and current limiting protection circuit includes an input port P2 (SMA socket), a resistor R8, a TVS bidirectional transient suppression diode D1, a resistor R11, a JFET junction field effect transistor Q5, a JFET junction field effect transistor Q11, a Schottky diode D3, a Schottky diode D4, a capacitor C17, and a resistor R23; one end of the input port P2 is connected to the piezoelectric sensor, and the other end of the input port P2 is connected to one end of the TVS bidirectional transient suppression diode D1 and one end of the resistor R11 after passing through the resistor R8, and the other end of the resistor R11 is connected to the piezoelectric sensor. The end is connected to the gate and source of the JFET junction field effect transistor Q5, the drain of the JFET junction field effect transistor Q5 is connected to the drain of the JFET junction field effect transistor Q11, the gate and source of the JFET junction field effect transistor Q11 are connected to the cathode of the Schottky diode D3, the anode of the Schottky diode D4 and one end of the capacitor C17, and the other end of the capacitor C17 is connected to the first-stage amplifier circuit through the resistor R23; the other end of the TVS bidirectional transient suppression diode D1, the anode of the Schottky diode D3, and the cathode of the Schottky diode D4 are all grounded.

[0016] Furthermore, the first-stage amplifier circuit includes a resistor R12, a resistor R33, a resistor R28, a resistor R14, a resistor R29, a resistor R39, a resistor R15, a resistor R27, a resistor R40, a capacitor C23, a capacitor C18, a capacitor C20, a capacitor C12, a capacitor C21, a JFET junction field-effect transistor Q10, and a PNP transistor Q9; one end of the resistor R12 and the resistor R33 is connected to the other end of the resistor R23 and the gate of the JFET junction field-effect transistor Q10 through the resistor R28, the source of the JFET junction field-effect transistor Q10 is respectively connected to one end of the capacitor C18, one end of the resistor R27, and one end of the resistor R29, and the drain of the JFET junction field-effect transistor Q10 is respectively connected to the base of the PNP transistor Q9, the resistor R1 4, the other end of the capacitor C18 and the other end of the resistor R27 are connected to the collector of the PNP transistor Q9, one end of the capacitor C21, and one end of the resistor R40 respectively through the capacitor C20, and the other end of the capacitor C21 is connected to the second-stage amplifier circuit; the emitter of the PNP transistor Q9 is connected to one end of the capacitor C12 and one end of the resistor R15 respectively, and the other end of the resistor R12, the other end of the resistor R14, the other end of the capacitor C12, and the other end of the resistor R15 are all connected to the power supply filter circuit; the other end of the resistor R29 is connected to one end of the resistor R39 and one end of the capacitor C23 respectively, and the other end of the resistor R33, the other end of the resistor R39, the other end of the capacitor C23, and the other end of the resistor R40 are all grounded.

[0017] Furthermore, the second-stage amplifier circuit includes a resistor R6, a resistor R32, a resistor R9, a resistor R34, a resistor R13, a resistor R35, a resistor R18, a resistor R25, a resistor R2, a resistor R19, a resistor R20, a resistor R36, a resistor R3, a resistor R37, a capacitor C13, a capacitor C19, a capacitor C10, a capacitor C12, a capacitor C21, an NPN transistor Q7, an NPN transistor Q12, and an NPN double triode pair Q4; one end of the resistor R6, one end of the resistor R32, and the other end of the capacitor C21 One end is connected to the base of NPN transistor Q7, the collector of NPN transistor Q7 is connected to one end of capacitor C13 and one end of resistor R9 respectively, the emitter of NPN transistor Q7 is connected to one end of capacitor C19 and one end of resistor R34 respectively; the other end of capacitor C13 is connected to one end of resistor R18 and the base of the left side of NPN double triode Q4 respectively, the other end of resistor R18 is connected to one end of resistor R25, one end of resistor R35 and one end of resistor R13 respectively, and the other end of resistor R25 is connected to one end of resistor R35 and one end of resistor R13 respectively. The collector of the NPN double triode Q4 is connected to one end of the capacitor C10, one end of the resistor R2 and the third-stage amplifier circuit respectively. The emitter of the NPN double triode Q4 is connected to one end of the resistor R19, the emitter of the NPN double triode Q4 is connected to one end of the resistor R20, the collector of the NPN transistor Q12 is connected to the other end of the resistor R19 and the other end of the resistor R20, and the NPN triode Q12 is connected to the other end of the resistor R19 and the other end of the resistor R20. The base of transistor Q12 is connected to one end of resistor R3 and one end of resistor R37 respectively, and the emitter of NPN transistor Q12 is grounded after passing through resistor R36; the other end of resistor R6, the other end of resistor R9, the other end of resistor R13, the other end of C10, the other end of R2, the collector on the right side of NPN dual triode pair Q4, and the other end of resistor R3 are all connected to the power supply filter circuit; the other end of resistor R32, the other end of resistor R34, the other end of resistor R35, and the other end of resistor R37 are all grounded.

[0018] Furthermore, the third-stage amplifier circuit includes resistor R4, resistor R7, resistor R22, resistor R10, resistor R31, resistor R26, resistor R30, resistor R21, resistor R5, resistor R38, resistor R16, resistor R24, resistor R17, capacitor C14, capacitor C24, capacitor C11, capacitor C15, capacitor C22, capacitor C16, PNP transistor Q3, PNP transistor Q8, PNP transistor Q13, NPN dual triode pair Q4, NPN transistor Q2, NPN transistor Q6, Schottky diode D2, Schottky diode D5, output port P3 (SMA socket); PNP transistor Q8 The base of the transistor is connected to one end of the capacitor C10, one end of the resistor R2, and the collector on the left side of the NPN double triode Q4 respectively. The emitter of the PNP transistor Q8 is connected to one end of the capacitor C14 and one end of the resistor R4 respectively. The other end of the capacitor C14 is connected to one end of the resistor R7, the base of the NPN transistor Q6, and one end of the resistor R22 respectively. The collector of the NPN transistor Q6 is connected to one end of the resistor R10, the base of the PNP transistor Q3, and one end of the capacitor C15 respectively. The emitter of the NPN transistor Q6 is connected to one end of the resistor R31 and one end of the resistor R26 respectively. The other end of the resistor R26 is connected to the resistor R30 after passing through the resistor R30. The emitter of the PNP transistor Q3 is connected to one end of the capacitor C11 and one end of the resistor R5, and the collector of the PNP transistor Q3 is connected to the anode of the Schottky diode D2, one end of the capacitor C22, and the base of the NPN transistor Q2. The cathode of the Schottky diode D2 is connected to one end of the resistor R38, the other end of the capacitor C22, and the base of the PNP transistor Q13 through the Schottky diode D5; the emitter of the NPN transistor Q2 is connected to one end of the resistor R17, one end of the resistor R24, and one end of the resistor R21 through the resistor R16, and the other end of the resistor R21 is connected to the capacitor C1. 5, the other end of the resistor R24 ​​is connected to the emitter of the PNP transistor Q13, and the other end of the resistor R17 is connected to one end of the output port P3 and the power supply filter circuit respectively through the capacitor C16; the other end of the resistor R4, the other end of the resistor R7, the other end of the resistor R10, the other end of the capacitor C11, the other end of the resistor R5, and the collector of the NPN transistor Q2 are all connected to the power supply filter circuit; the collector of the PNP transistor Q8, the other end of the resistor R22, the other end of the resistor R31, the other end of the capacitor C24, the other end of the resistor R38, and the collector of the PNP transistor Q13 are all grounded.

[0019] Furthermore, the power supply filter circuit includes an inductor L1, an inductor L2, an inductor L3, a magnetic bead FB1, a magnetic bead FB3, a magnetic bead FB4, a magnetic bead FB5, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R1, and an LDO three-terminal voltage regulator chip YW1; the OUT pins of the LDO three-terminal voltage regulator chip YW1 are respectively connected to one end of the capacitor C2, one end of the capacitor C8, the other end of the resistor R4, the other end of the resistor R7, the other end of the resistor R10, and the capacitor C The other end of 11, the other end of resistor R5, the collector of NPN transistor Q2, the other end of resistor R6, the other end of resistor R9, the other end of resistor R13, the other end of C10, the other end of R2, the collector on the right side of NPN dual triode Q4, the other end of resistor R3, the other end of resistor R12, the other end of resistor R14, the other end of capacitor C12, and the other end of resistor R15 are connected; the IN pin of LDO three-terminal voltage regulator chip YW1 is connected to one end of magnetic bead FB5 and one end of capacitor C1 respectively, and the IN pin of magnetic bead FB5 is connected to one end of magnetic bead FB5. The other end is connected to the emitter of transistor Q1 respectively, the base of transistor Q1 is connected to one end of capacitor C9 and one end of resistor R1 respectively, the other end of resistor R1 and the collector of transistor Q1 are connected to one end of magnetic bead FB4, the other end of magnetic bead FB4 is connected to one end of inductor L3 and one end of capacitor C7 respectively, the other end of inductor L3 is connected to one end of capacitor C6 and one end of magnetic bead FB3 respectively, the other end of magnetic bead FB3 is connected to one end of capacitor C5 and one end of inductor L2 respectively, the other end of inductor L2 is connected to capacitor One end of C4 is connected to one end of the magnetic bead FB1, the other end of the magnetic bead FB1 is respectively connected to one end of the inductor L1 and one end of the capacitor C3, the other end of the inductor L1 is respectively connected to one end of the capacitor C16 and one end of the output port P3; the GND pin of the LDO three-terminal voltage regulator chip YW1, the other end of the capacitor C8, the other end of the capacitor C2, the other end of the capacitor C1, the other end of the capacitor C9, the other end of the capacitor C7, the other end of the capacitor C6, the other end of the capacitor C5, the other end of the capacitor C4, and the other end of the capacitor C3 are all grounded.

[0020] Compared with the prior art, the present invention has the following advantages and positive effects:

[0021] 1. Aiming at the problem that the existing general ultrasonic preamplifier has a small amplification factor (up to 1000 times), resulting in low sensitivity of the amplifier and the inability to clearly and accurately locate the arrival position of the ultrasonic echo in the high-temperature and high-pressure deformation experiment of the rock, the present invention adopts the following methods to make improvements: (1) a three-stage amplification structure, which can achieve a maximum amplification of about 5000 times of weak signals; (2) the amplifier input stage adopts a MOS tube and transistor discrete amplification architecture to ensure that the input impedance of the entire amplifier is above the MΩ level, which can maximize the pickup of the ultrasonic echo charge information detected by the ultrasonic sensor; (3) the coaxial power supply part of the amplifier adopts an LC filter and LDO (three-terminal voltage regulator chip) step-down filter combination structure, which can minimize electromagnetic interference while ensuring a maximum amplification of about 5000 times, thereby improving the signal-to-noise ratio of the amplified ultrasonic signal.

[0022] 2. In order to address the problem that existing general ultrasonic preamplifiers cannot realize the transmit / receive switching function and are therefore unsuitable for high-temperature and high-pressure rock experimental environments, the present invention improves its structure so that it can be applied to the switching of the overvoltage and current limiting protection function of transmitting high voltage and the weak current signal receiving function. That is, when an ultrasonic probe is used in the high-temperature and high-pressure rock experiment and a high-voltage and high-power transmit pulse is loaded on the ultrasonic probe, the input end of the ultrasonic preamplifier connected to the ultrasonic probe is in a high-resistance, current-limiting and voltage-limiting state, thereby protecting the subsequent analog conditioning circuit from being damaged by the high-voltage pulse; after the high-voltage pulse disappears, the ultrasonic preamplifier is in a normal receiving state to receive the weak ultrasonic echo signal. The ultrasonic preamplifier in the present invention first uses a series resistor (above 1kΩ) and a TVS diode (transient voltage suppressor diode) structure at the input end to limit the high-voltage pulse to the overvoltage protection range of the TVS diode (transient voltage suppressor diode) (usually tens of V). The suppressed voltage pulse is then input into a bidirectional current limiting circuit composed of a JFET tube (junction field effect transistor), which further limits the voltage pulse to the saturation conduction voltage drop (about 2V) and saturation conduction current (tens of mA) of the JFET tube, thereby realizing the ultrasonic preamplifier's transmitting high-voltage overvoltage current limiting protection; when the high-voltage pulse disappears, the subsequent weak ultrasonic echo signal (μV to mV level) will not cause the TVS tube to turn on after entering the input end of the ultrasonic preamplifier, nor will it trigger the current limiting and amplitude limiting functions of the JFET tube, that is, the weak ultrasonic echo signal can normally pass through the protection circuit and enter the next-stage amplification circuit of the amplifier to realize normal weak signal amplification.

[0023] 3. In response to the problem that existing preamplifiers do not have a coaxial power supply function, the present invention adopts a phantom power supply solution, which can realize the coaxial transmission function of the amplified AC signal and DC power supply. That is, the amplifier and the collector are connected using only one coaxial cable, which can not only transmit the amplified AC ultrasonic information, but also power the amplifier through this cable. No additional external power supply is required, which saves instrument space, simplifies operation, and is compact.

[0024] 4. The entire amplifier main circuit in the present invention is built using discrete components, and the components used in the circuit are all domestic devices with independent intellectual property rights, and the technology is completely independent and controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 Schematic diagram of the circuit structure of the present invention;

[0027] Figure 2 Schematic diagram of the circuit function of the present invention. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts, any modifications, equivalent replacements, improvements, etc., shall be included in the scope of protection of the present invention.

[0029] like Figure 1 、 Figure 2 As shown, this embodiment discloses a high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments, the high-sensitivity ultrasonic preamplifier includes an input signal limiting and current limiting protection circuit, a first-stage amplification circuit, a second-stage amplification circuit, a third-stage amplification circuit, and a power supply filter circuit; one end of the input signal limiting and current limiting protection circuit is connected to an external piezoelectric sensor, the other end of the input signal limiting and current limiting protection circuit is connected to one end of the first-stage amplification circuit, the other end of the first-stage amplification circuit is connected to one end of the third-stage amplification circuit via the second-stage amplification circuit, and the other end of the third-stage amplification circuit is connected to the output port; the power supply filter circuit is respectively connected to the first-stage amplification circuit, the second-stage amplification circuit, and the third-stage amplification circuit.

[0030] The following describes the structure and function of each circuit in detail. Figure 1 As shown:

[0031] (1) Input signal limiting and current limiting protection circuit, which includes input port P2 (SMA socket), resistor R8, TVS bidirectional transient suppression diode, resistor R11, JFET junction field effect transistors Q5, Q11, Schottky diodes D3, D4, capacitor C17 and resistor R23;

[0032] The input port P2 is connected to an external piezoelectric sensor, which serves as the input port for the weak ultrasonic echo signal returned by the sensor, and at the same time receives the high-voltage and high-power pulse signal loaded onto the piezoelectric sensor by the external power amplifier. Port 1 of P2 is connected to end 1 of resistor R8, and end 2 of R8 is connected to the bidirectional TVS tube SMAJ5.0A (transient suppression diode) to ground. When the high-voltage and high-power pulse signal on the piezoelectric sensor is input through port P2, the bidirectional TVS transient suppression diode SMAJ5.0A limits the high-voltage and high-power pulse to its breakdown voltage of about 6.4V through the resistor R8 (1KΩ). At this time, D1 is turned on to the ground, which is equivalent to the input port 1 of P2 being connected to the ground through end 2 of R8, that is, the impedance of the input port 1 of P2 to the ground is 1KΩ. The role of R8 is to ensure that D1 is After being turned on, the input 1 port of P2 will not be directly connected to the ground (impedance is approximately 0), thereby ensuring that the high-voltage and high-power pulse signal on the piezoelectric sensor connected to the input port P2 will not be directly loaded onto the ground, thereby causing an overload of the external power amplifier (if there is no R8, the high-voltage and high-power pulse output by the external power amplifier loaded onto the piezoelectric sensor is equivalent to returning directly through the ground, that is, the load impedance connected to the external power amplifier at this time is approximately 0, and the output current of the external power amplifier is infinite, which will cause the external power amplifier to overload and damage the external power amplifier.). After being clipped to 6.4V by diode D1, the high-voltage, high-power pulse signal (marked as S1) passes through the bidirectional overvoltage and current-limiting protection circuit composed of JFET transistors (junction field-effect transistors) Q5 and Q11-3DG7G (Q5's gate and source are shorted and connected to terminal 1 of 1kΩ resistor R11. Terminal 2 of R11 is connected to R8 and D1; Q5's drain is connected to Q11's drain, and Q11's gate and source are shorted and connected to the cathode of diode D3 and the anode of D4. Resistor R11 is a current-limiting resistor, protecting Q5 and Q11 while limiting the current flowing through D3 and D4). This circuit further clips the high-voltage, high-power pulse signal S1, which has been clipped to 6.4V, to its pinch-off voltage of approximately 4V. The signal current flowing out of Q11's source is also limited to its saturation current IDSS level, with a maximum of approximately 11mA. This signal is marked as S2. The S2 signal is further limited to -0.6V to 0.6V by a bidirectional ground-limiting circuit formed by diodes D3 and D4 (B0520LW). This signal is labeled S3. The cathode of diode D3 and the anode of D4 are shorted together and connected to the source of Q11, which is also connected to terminal 1 of C17. The anode of diode D3 and the cathode of D4 are shorted together and grounded. The S3 signal is AC-coupled through 1nF capacitor C17 to terminal 1 of 1kΩ resistor R23.

[0033] (2) a first-stage amplifier circuit, comprising resistors R12, R33, R28, R14, R29, R39, R15, R27, and R40, capacitors C23, C18, C20, C12, and C21, a JFET junction field-effect transistor Q10, and a PNP transistor Q9;

[0034] The 187kΩ resistor R12 end 2 is connected to the 100kΩ resistor R33 end 1, and is also connected to the R23 end 2 and the 1MΩ resistor R28 end 2. The R12 end 1 is connected to the OUT output terminal of the LDO chip (three-terminal voltage regulator chip) XL317 (the OUT output terminal of the XL317 is marked as power supply V1, and the output voltage is 24V). The R33 end 2 is grounded. The resistor R23 end 2 and the R28 end 2 are commonly connected to the gate of the JFET (junction field effect transistor) Q10-3DJ7H. The voltage-divider network formed by resistors R12 and R33 sets Q10's quiescent operating point to approximately 100 / (100+187)*24=8.3623V. This means that Q10's gate voltage is approximately 8.36V during quiescent operation. Resistor R28, connected in series with the gate, increases Q10's input impedance to 10MΩ, preventing the voltage-divider network of R12 and R13 from lowering Q10's input impedance. Resistor R23 acts as a current-limiting resistor for input signal S3, further protecting Q10's gate. During static operation, the source voltage of Q10 is approximately 8.36 + 0.25 = 8.61 V. Therefore, the static current flowing through the source of Q10 is approximately 8.61 / (49.9 + 6040) = 0.0014 A. Terminal 1 of 49.9Ω resistor R29 is connected to the source of Q10, while terminal 2 is connected to terminal 1 of 6.04kΩ resistor R39 and terminal 1 of 22μf capacitor C23. Terminal 2 of resistor R39 and terminal 2 of capacitor C23 are both grounded. R39 and C23 form a high-pass filter circuit that filters out low-frequency noise in input signal S3. The high-pass cutoff frequency is 1000 / (6.28*6040*0.000022) = 1.2 Hz. Terminal 2 of 4.99kΩ resistor R14 is connected to the drain of Q10, and terminal 1 is connected to power supply V1. When Q10 is in a static state, the drain current is approximately equal to the source current. Therefore, the voltage drop across R14 is 0.0014*4990=6.986V. That is, the voltage drop across Q10's drain and source in a static state is 24-6.986-8.61=8.404V, and Q10 operates in the amplification region. The emitter of PNP transistor Q9 (2N3906) is connected to terminal 2 of 1kΩ resistor R15 and terminal 2 of 100μf / 16V capacitor C12. Terminal 1 of resistor R15 and terminal 1 of capacitor C12 are both connected to power supply V1. The base of Q9 is short-circuited with the drain of Q10. Therefore, the voltage drop across R15 is 6.986 + 0.6V = 7.586V (0.6V is the PN junction voltage drop between the emitter and base of Q9). This means that the voltage across Q9's emitter to ground is 7.586V, and the static emitter current is 7.586 / 1000 = 7.586mA. C12 and R15 form a high-pass filter to remove low-frequency noise from the amplified signal in the first-stage amplifier circuit. The high-pass cutoff frequency is 1 / (6.28*0.0001*1000) = 1.59Hz.The collector of Q9 is connected to terminal 1 of 22μf capacitor C20, 5.6nf capacitor C21 and terminal 1 of 1kΩ resistor R40. The voltage drop on R40 is 0.007586*1000=7.586V (the current flowing through the collector and emitter of Q9 is the same when static), that is, the collector potential of Q9 is 7.586V, then the collector-emitter voltage drop of Q9 is 24-2*7.586=8.828V, and Q9 operates in the amplification area. Terminal 2 of C20 is connected to terminal 1 of a 1pf capacitor C18 and terminal 1 of a 2.49kΩ resistor R27. Terminal 2 of capacitor C18 and terminal 2 of resistor R27 are connected together to the source of Q10 and to terminal 1 of R29. Therefore, C20, C18, R27, and R29 together form the AC negative feedback network of the first-stage amplifier circuit. C20 blocks the DC component of the Q9 output signal, allowing only the AC component of the amplified signal to pass, preventing circuit saturation. The AC amplification factor of the first-stage amplifier is 1+R27 / R29=1+2490 / 49.9=50.9 (During AC amplification, R39 does not participate due to the presence of C23). C18 and R27, in parallel, form a low-pass filter circuit in the first-stage amplifier circuit, filtering out high-frequency noise from the Q9 output signal (this signal is labeled S4). The low-pass cutoff frequency is 1000000000 / (6.28*1*2.49)=63.95MHz. The S4 signal is AC-coupled to the second-stage amplifier circuit through terminal 1 of the 5.6nF capacitor C21.

[0035] (3) a second-stage amplifier circuit, which includes resistors R6, R32, R9, R34, R13, R35, R18, R25, R2, R19, R20, R36, R3, and R37; capacitors C13, C19, C10, C12, and C21; NPN transistors Q7 and Q12; and an NPN dual-triode pair Q4;

[0036] End 2 of the 100kΩ resistor R6 is connected to capacitor segment 2 of C21, and is also connected to end 1 of a 41.2kΩ resistor R32, end 1 of a 5.6nF capacitor C13, and the base of a 2N3904 transistor Q7. End 1 of R6 is connected to power supply V1, and end 2 of resistor R32 is grounded. R6 and R32 form a resistor divider network that sets the quiescent voltage at the base of Q7 to 24*41.2 / (100+41.2)=7V. The collector of Q7 is connected to end 2 of a 499Ω resistor R9, which is connected to power supply V1. End 1 of R9 is connected to the emitter of Q7, to end 1 of a 499Ω resistor R34, and to end 1 of a 5.6nF capacitor C19. The voltage drop across R34 is 7 + 0.6 = 7.6V (0.6V is the base-emitter PN junction voltage drop of transistor Q7). Therefore, the quiescent current flowing through Q7's emitter is 7.6 / 499 = 0.01523A. Since the collector and emitter currents flowing through Q7 are the same during quiescent conditions, the voltage drop across R9 is 0.01523 * 499 = 7.6V, meaning that the collector-emitter voltage drop across Q7 is 24 - 2 * 7.6 = 8.8V, placing Q7 in its amplification region. As an emitter-follower differential circuit, Q7 increases the load capacity of Q9's collector output. After the S4 signal is AC-coupled to Q7's emitter-follower differential circuit via C21, it is split into two differential signals of equal voltage amplitude, each AC-coupled via C13 and C19 to the NPN dual-triode transistor Q4 amplifier circuit for differential amplification, eliminating differential-mode noise in the amplified signal. Terminal 2 of 144kΩ resistor R13 is connected to terminal 1 of 96kΩ resistor, terminal 2 of 10kΩ resistor R18, and terminal 1 of 10kΩ resistor R25; terminal 1 of R18 is connected to the base of the left side of NPN dual triode pair Q4 (i.e., the transistor on the left side of NPN dual triode pair Q4) and is also connected to terminal 2 of C13; terminal 2 of R25 is connected to the base of the right side of NPN dual triode pair Q4 (i.e., the transistor on the right side of NPN dual triode pair Q4) and is also connected to terminal 2 of C19; the voltage divider network formed by R13 and R35 sets the quiescent operating point base voltage of the dual triodes in Q4 to 24*96 / (144+96)=9.6V. Terminal 2 of 215kΩ resistor R3 is connected to terminal 1 of 26.1kΩ resistor R37 and the base of 2N3904 transistor Q12. The voltage divider network formed by R3 and R37 sets the base voltage of Q12 at its quiescent operating point to 24*26.1 / (26.1+215)=2.598V. The emitter of Q12 is connected to terminal 1 of 1kΩ resistor R36, and terminal 2 of resistor R36 is grounded. Therefore, the emitter current flowing through Q12 at quiescent state is (2.598-0.6) / 1000=0.001998A (0.6V is the base-emitter PN junction voltage drop of transistor Q12).The collector of Q12 is connected to terminal 2 of the 499 ohm resistor R19 and terminal 2 of the 499 ohm resistor R20. Terminal 1 of R19 is connected to the emitter on the left side of the NPN dual triode Q4. Terminal 1 of R20 is connected to the emitter on the left side of the NPN dual triode Q4. The collector on the left side of the NPN dual triode Q4 is connected to terminal 2 of the 1pf capacitor C10 and terminal 2 of the 4.02k ohm resistor R2. Terminal 1 of C10 and terminal 1 of R2 are both connected to the power supply V1. The collector on the right side of the NPN dual triode Q4 is directly connected to the power supply V1. Since the collector and emitter currents of Q12 are the same in static mode, the voltage drops across R19 and R20 are both 0.001998*499=0.997V. Therefore, the collector-emitter voltage drop of Q12 is 9.6-0.6-1.998-0.997=6.005V (0.6V is the base-emitter PN junction voltage drop on the left side of the NPN dual triode pair Q4), indicating that Q12 operates in the amplification region. In static mode, the collector current of Q4 is the same as the emitter current of the series-connected transistor Q12. Therefore, the voltage drop across R2 is 0.001998*4020=8.03196V. Therefore, the collector-emitter voltage drop of Q4 is 24-8.03196-9=6.97V, indicating that Q4 operates in the amplification region. C10 and R2, connected in parallel, form a low-pass filter in the second-stage amplifier circuit, filtering out high-frequency noise from the amplified signal. Its cutoff frequency is 100,000,000 / (6.28*1*4.02) = 39.61 MHz. C10 also stabilizes the amplification pole of the second-stage amplifier circuit, preventing oscillation. The junction between R2's terminal 2 and the left collector of the NPN dual triode pair Q4 serves as the output port of the second-stage amplifier circuit, connected to the base of the PNP transistor Q8. Its output signal is denoted as S5. The AC gain of the entire second-stage amplifier circuit is R2 / (2*R19) = 4020 / (2*499) = 4.

[0037] (4) The third-stage amplifier circuit includes resistors R4, R7, R22, R10, R31, R26, R30, R21, R5, R38, R16, R24, and R17; capacitors C14, C24, C11, C15, C22, and C16; PNP transistors Q3, Q8, Q13, and Q12; NPN dual triode pairs Q4, Q2, and Q6; Schottky diodes D2 and D5; and an output port P3 (SMA socket);

[0038] The base quiescent voltage of transistor Q8 is equal to the collector potential of Q4 (24 - 0.001998 * 4020 = 15.96804V). The emitter of Q8 is connected to terminal 2 of a 499Ω resistor R4 and terminal 1 of a 15nF capacitor. Q8 and R4 form an emitter-follower circuit, enhancing the output load capability of Q4's collector. The S5 signal is AC-coupled to the input of the third-stage amplifier circuit via terminal 2 of capacitor C14. Terminal 2 of a 100kΩ resistor R7 is connected to terminal 1 of a 41.2kΩ resistor R22, which is then connected to the base of an NPN transistor Q6-2N3904. Terminal 1 of R7 is connected to power supply V1, and terminal 2 of R22 is grounded. The collector of Q6 is connected to terminal 2 of 1.62kΩ resistor R10, terminal 1 of R10 is connected to power supply V1, the emitter of Q6 is connected to terminal 1 of 1.47kΩ resistor R31 and terminal 1 of 100Ω resistor R26, terminal 2 of R31 is grounded, terminal 2 of R26 is connected to terminal 1 of 1kΩ variable resistor R30, the variable terminal and terminal 2 of R30 are short-circuited and connected to terminal 1 of 10μf capacitor C24, and terminal 2 of C24 is grounded. The voltage divider network composed of R7 and R22 sets the base voltage of Q6's static operating point at 24*41.2 / (100+41.2)=7V, so the emitter static current flowing through Q6 is (7-0.6) / 1470=0.004356A (0.6V is the base-emitter PN junction voltage drop of Q6 transistor). Since the collector static current and emitter current flowing through Q6 are the same in static state, that is, the voltage drop across R10 is 0.004356*1620=7.056V, the collector-emitter voltage drop of Q6 is 24-7.056-7+0.6=10.5348V, and Q6 operates in the amplification area. The base of PNP transistor Q3 (2N3906) is connected to terminal 2 of R10 and the collector of Q6, and to terminal 1 of 22μf capacitor C15. Q3's emitter is connected to terminal 2 of 499Ω resistor R5 and terminal 2 of 1pf capacitor C11. Terminals 1 of R5 and 1pf of C11 are both connected to power supply V1. Q3's collector is connected to the anode of Schottky diode D2 (B0520LW), terminal 1 of 10nf capacitor C22, and the base of NPN transistor Q2 (2N3904). C11 and R5 form the low-pass filter circuit of the third-stage amplifier circuit to filter out high-frequency noise from the amplified signal. Its cutoff frequency is 10000000000000 / (6.28*1*499)=319.1MHz. C11 also stabilizes the operating point of the third-stage amplifier circuit, preventing oscillation. In static state, the emitter potential of Q3 is 7.056+0.6=7.656V, so the emitter static current flowing through Q3 is 7.656 / 499=0.0153A.The anode of Schottky diode D5-B0520LW is connected to the cathode of D2. The cathode of D5 is connected to terminal 1 of 499Ω resistor R38, terminal 2 of 10nf capacitor C22, and the base of PNP transistor Q13-2N3906. Terminal 2 of R38 is grounded. In static state, since the collector of Q3 is connected in series with D2, D5, and R38, the static current flowing through R38 is equal to the collector static current of Q3. The voltage drop across R38 is 0.0153*499=7.6347V. Q3 The emitter-collector voltage drop is 24-7.656-0.3-0.3-7.6347=8.1093V (0.3V is the PN junction voltage drop of the Schottky diode), and Q3 operates in the amplification region; the collector of Q2 is connected to the power supply V1, the emitter of Q2 is connected to the 10Ω resistor R16 terminal 1, the R16 terminal 2 is connected to the R24 terminal 1, and the 2.49kΩ resistor R21 terminal 2 is connected, and the R21 terminal 1 is connected to the C15 terminal 2. R21 and C15 form a negative feedback network of the third-stage amplifier circuit. Terminal 2 of R24 is connected to the emitter of a PNP transistor Q13 (2N3906), while the collector of Q13 is grounded. D2, D5, C22, Q2, Q13, R16, and R24 form the complementary power amplifier output section of the third-stage amplifier circuit, improving the overall output capability of the amplifier circuit under load. C22 eliminates AC crossover distortion in the third-stage amplifier circuit. Terminal 1 of a 49.9Ω resistor R17 is connected to terminal 2 of R16 and terminal 1 of R24, setting the output impedance of the entire amplifier circuit to approximately 50 ohms. Terminal 2 of R17 is connected to terminal 1 of a 10μf / 16V capacitor C16, and terminal 2 of C16 is connected to the P3 output port (SMA). C16 couples the amplified signal to the output port and filters out the DC level of the amplified signal. The AC gain of the third-stage amplifier circuit is R21 / (R26+R30), with a maximum of 1+2490 / (100+0)=25.9.

[0039] The total AC amplification factor of the entire amplifier circuit is the product of the respective AC amplification factors of the three amplifier circuits, that is, the maximum total AC amplification factor is 50.9*4*25.9=5273.24 times.

[0040] (5) Power supply filter circuit, which includes inductors L1, L2, L3, magnetic beads FB1, FB3, FB4, FB5, capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, resistor R1 and LDO three-terminal voltage regulator chip XL317;

[0041] The P3 port not only outputs the entire amplifier circuit's AC amplified signal, but also accepts an external power supply via P3 port pin 1. C16 pin 2 is connected to P3 output pin 1 and 100mH high-capacity magnetic toroidal inductor L1 pin 1. L1 pin 2 is connected to 1000μf / 35V aluminum electrolytic capacitor C3 pin 1, and C3 pin 2 is grounded. Due to the inductor's ability to isolate AC from DC, the AC amplified signal output from C16 pin 2 will not flow through inductor L1 into the subsequent low-pass filter circuit. Furthermore, due to the capacitor's ability to isolate DC from AC, the external DC power input from P3 pin 1 will not flow through C16 into the amplifier circuit, but will flow through L1 into the subsequent power supply filter circuit. Thus, C16, P3, L1, and C3 form the phantom power supply for the entire preamplifier, enabling the simultaneous transmission of external power and AC amplified signals over a single coaxial cable. FB1, FB3, and FB4 in the filter circuit are CBG201209U600T. Their function is to attenuate spike noise in the external power supply. FB1 terminal 1 is connected to L2 terminal 2, FB1 terminal 2 is connected to 100μf / 35V filter capacitor C4 terminal 1 and 100μH / 1A solid-state inductor L2 terminal 1, L2 terminal 2 is connected to 100μf / 35V filter capacitor C5 terminal 1 and FB3 terminal 1, FB3 terminal 2 is connected to 100μH / 1A solid-state inductor L3 terminal 1 and 100μf / 35V filter capacitor C6 terminal 1, L3 terminal 2 is connected to 100μf / 35V filter capacitor C7 terminal 1 and FB4 terminal 1. Terminals C4, C5, C6, and C7 are all grounded. L2 and C5 form an LC filter circuit to filter out ripple noise in the external power supply. C6, L3, and C7 form a CLC filter circuit to further attenuate the ripple voltage level in the external power supply. The collector of NPN transistor Q1-2SC1766 is connected to terminal 2 of FB4 and terminal 1 of 10Ω resistor R1. Terminal 2 of R1 is connected to the base of Q1 and terminal 1 of 100μf / 35V filter capacitor C9. Terminal 2 of C9 is grounded. The emitter of Q1 is connected to terminal 1 of FB5. Q1, R1, and C9 form an electronic filter, which can increase the capacitance of C9 by β times (β is the amplification factor of Q1 transistor, generally above 100). This can reduce the size of the filter capacitor and improve the filtering capability. After electronic filtering, the ripple voltage noise in the external power supply is very low (1mV-10mV). Connect FB5's terminal 2 to the 100μf / 35V filter capacitor C1's terminal 1 and the IN port of the YW1-XL317 LDO three-terminal voltage regulator. Connect C1's terminal 2 to ground, and YW1's GND terminal to ground. YW1's OUT port is connected to the 0.1μf capacitor C2's terminal 1 and the 100μf / 35V filter capacitor C8's terminal 1. Both C2's terminal 2 and C8's terminal 2 are grounded. The LDO chip (three-terminal voltage regulator) further suppresses the ripple voltage of the external power supply, reducing it to around μV, which is ultimately supplied to the entire amplifier circuit.

[0042] All components used in the ultrasonic preamplifier circuit are domestically produced. The inductors, capacitors, and resistors are all domestically produced. Ferrite beads FB1, FB3, FB4, and FB5 are CBG201209U600T Fenghua High-Tech chip beads. The bidirectional transient suppression diodes (TVSs) are SMAJ5.0A from Hecotech Electronics. Schottky diodes D2, D3, D4, and D5 are B0520LW from Hecotech Electronics. The NPN transistor 2N3904 is a domestically produced model from Blue Arrow Electronics, as are the PNP transistors 2N3906 and 2N3906. The NPN transistor 2SC1766 is a domestically produced model from Hecotech Electronics. The dual NPN transistor pair is the MMDT3904 from Canyu Technology. The LDO three-terminal voltage regulator chip is the XL317 from Xinluda Semiconductor.

[0043] The present invention has the following beneficial effects:

[0044] 1. The ultrasonic preamplifier described in detail in the present invention has high sensitivity (input impedance of about 10MΩ) and high amplification factor (up to about 5273 times), which can obtain clear ultrasonic echo arrival information with good signal-to-noise ratio, effectively preventing misjudgment of echo arrival time.

[0045] 2. The ultrasonic preamplifier described in detail in the present invention has a transmit / receive switching function, which can meet the requirements of simultaneously transmitting high-voltage pulses and receiving weak ultrasonic echo signals in the case of a limited container space for high-temperature and high-pressure rock deformation experiments where only one ultrasonic probe can be installed.

[0046] 3. The ultrasonic preamplifier described in detail in the present invention has a coaxial power supply function and does not require an external power supply. This can effectively reduce the size of the external instrument connected to the ultrasonic preamplifier, simplify the operation, and is efficient and convenient.

[0047] 4. The components used in the ultrasonic preamplifier detailed in the present invention are all domestic electronic components. The technology is completely independent and controllable, which can effectively avoid the bottleneck phenomenon.

Claims

1. High-sensitivity ultrasonic preamplifier for rock high-temperature and high-pressure deformation experiments, characterized by: The high-sensitivity ultrasonic preamplifier includes an input-end signal limiting and current limiting protection circuit, a first-stage amplifying circuit, a second-stage amplifying circuit, a third-stage amplifying circuit, and a power supply filter circuit; one end of the input-end signal limiting and current limiting protection circuit is connected to an external piezoelectric sensor, the other end of the input-end signal limiting and current limiting protection circuit is connected to one end of the first-stage amplifying circuit, the other end of the first-stage amplifying circuit is connected to one end of the third-stage amplifying circuit via the second-stage amplifying circuit, and the other end of the third-stage amplifying circuit is connected to the output port; the power supply filter circuit is respectively connected to the first-stage amplifying circuit, the second-stage amplifying circuit, and the third-stage amplifying circuit; the amplifier input stage adopts a discrete amplification architecture of MOS tubes and transistors; The input end signal limiting and current limiting protection circuit includes an input port P2, a resistor R8, a TVS bidirectional transient suppression diode D1, a resistor R11, a JFET junction field effect transistor Q5, a JFET junction field effect transistor Q11, a Schottky diode D3, a Schottky diode D4, a capacitor C17, and a resistor R23; one end of the input port P2 is connected to the piezoelectric sensor, and the other end of the input port P2 is connected to one end of the TVS bidirectional transient suppression diode D1 and one end of the resistor R11 after passing through the resistor R8, and the other end of the resistor R11 is connected to the JFET The gate and source of the junction field effect transistor Q5 are connected, the drain of the JFET junction field effect transistor Q5 is connected to the drain of the JFET junction field effect transistor Q11, the gate and source of the JFET junction field effect transistor Q11 are connected to the cathode of the Schottky diode D3, the anode of the Schottky diode D4 and one end of the capacitor C17, and the other end of the capacitor C17 is connected to the first-stage amplifier circuit through the resistor R23; the other end of the TVS bidirectional transient suppression diode D1, the anode of the Schottky diode D3, and the cathode of the Schottky diode D4 are all grounded.

2. The high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments according to claim 1, characterized in that: The first-stage amplifier circuit includes a resistor R12, a resistor R33, a resistor R28, a resistor R14, a resistor R29, a resistor R39, a resistor R15, a resistor R27, a resistor R40, a capacitor C23, a capacitor C18, a capacitor C20, a capacitor C12, a capacitor C21, a JFET junction field effect transistor Q10 and a PNP transistor Q9; one end of the resistor R12 and the resistor R33 is connected to the other end of the resistor R23 and the gate of the JFET junction field effect transistor Q10 through the resistor R28, the source of the JFET junction field effect transistor Q10 is respectively connected to one end of the capacitor C18, one end of the resistor R27 and one end of the resistor R29, the drain of the JFET junction field effect transistor Q10 is respectively connected to the base of the PNP transistor Q9 and one end of the resistor R14. The other end of the capacitor C18 and the other end of the resistor R27 are connected to the collector of the PNP transistor Q9, one end of the capacitor C21, and one end of the resistor R40 respectively through the capacitor C20, and the other end of the capacitor C21 is connected to the second-stage amplifier circuit; the emitter of the PNP transistor Q9 is connected to one end of the capacitor C12 and one end of the resistor R15 respectively, and the other end of the resistor R12, the other end of the resistor R14, the other end of the capacitor C12, and the other end of the resistor R15 are all connected to the power supply filter circuit; the other end of the resistor R29 is connected to one end of the resistor R39 and one end of the capacitor C23 respectively, and the other end of the resistor R33, the other end of the resistor R39, the other end of the capacitor C23, and the other end of the resistor R40 are all grounded.

3. The high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments according to claim 2, characterized in that: The second-stage amplifier circuit includes a resistor R6, a resistor R32, a resistor R9, a resistor R34, a resistor R13, a resistor R35, a resistor R18, a resistor R25, a resistor R2, a resistor R19, a resistor R20, a resistor R36, a resistor R3, a resistor R37, a capacitor C13, a capacitor C19, a capacitor C10, a capacitor C12, a capacitor C21, an NPN transistor Q7, an NPN transistor Q12 and an NPN double triode pair Q4; one end of the resistor R6, one end of the resistor R32 and the other end of the capacitor C21 are all connected to The base of the NPN transistor Q7 is connected, the collector of the NPN transistor Q7 is connected to one end of the capacitor C13 and one end of the resistor R9 respectively, and the emitter of the NPN transistor Q7 is connected to one end of the capacitor C19 and one end of the resistor R34 respectively; the other end of the capacitor C13 is connected to one end of the resistor R18 and the base of the left side of the NPN double triode Q4 respectively, the other end of the resistor R18 is connected to one end of the resistor R25, one end of the resistor R35, and one end of the resistor R13 respectively, and the other end of the resistor R25 is connected to The other end of the capacitor C19 is connected to the base on the right side of the NPN dual triode Q4; the collector on the left side of the NPN dual triode Q4 is respectively connected to one end of the capacitor C10, one end of the resistor R2 and the third-stage amplifier circuit, the emitter on the left side of the NPN dual triode Q4 is connected to one end of the resistor R19, the emitter on the right side of the NPN dual triode Q4 is connected to one end of the resistor R20, the collector of the NPN transistor Q12 is connected to the other end of the resistor R19 and the other end of the resistor R20, and the NPN transistor The base of Q12 is connected to one end of the resistor R3 and one end of the resistor R37 respectively, and the emitter of the NPN transistor Q12 is grounded after passing through the resistor R36; the other end of the resistor R6, the other end of the resistor R9, the other end of the resistor R13, the other end of C10, the other end of R2, the collector on the right side of the NPN dual triode Q4, and the other end of the resistor R3 are all connected to the power supply filter circuit; the other end of the resistor R32, the other end of the resistor R34, the other end of the resistor R35, and the other end of the resistor R37 are all grounded.

4. The high-sensitivity ultrasonic preamplifier for high-temperature and high-pressure rock deformation experiments according to claim 3, characterized in that: The third stage amplifier circuit includes resistor R4, resistor R7, resistor R22, resistor R10, resistor R31, resistor R26, resistor R30, resistor R21, resistor R5, resistor R38, resistor R16, resistor R24, resistor R17, capacitor C14, capacitor C24, capacitor C11, capacitor C15, capacitor C22, capacitor C16, PNP transistor Q3, PNP transistor Q8, PNP transistor Q13, NPN double triode pair Q4, NPN transistor Q2, NPN transistor Q6, Schottky diode D2, Schottky diode D5, and output port P3; the base of PNP transistor Q8 is connected to capacitor C14, C24, C11, C15, C22, C16, PNP transistor Q3, PNP transistor Q8, PNP transistor Q13, NPN double triode pair Q4, NPN transistor Q2, NPN transistor Q6, Schottky diode D2, Schottky diode D5, and output port P3; the base of PNP transistor Q8 is connected to capacitor C14, C24, C11, C15, C22, C16, PNP transistor Q3, PNP transistor Q8, PNP transistor Q13, NPN double triode pair Q4, NPN transistor Q2, NPN transistor Q6, Schottky diode D2, Schottky diode D5, and output port P3; The emitter of the PNP transistor Q8 is connected to one end of the capacitor C14 and one end of the resistor R4 respectively. The other end of the capacitor C14 is connected to one end of the resistor R7, the base of the NPN transistor Q6 and one end of the resistor R22 respectively. The collector of the NPN transistor Q6 is connected to one end of the resistor R10, the base of the PNP transistor Q3 and one end of the capacitor C15 respectively. The emitter of the NPN transistor Q6 is connected to one end of the resistor R31 and one end of the resistor R26 respectively. The other end of the resistor R26 is connected to one end of the capacitor C24 after passing through the resistor R30. The emitter of the PNP transistor Q3 is respectively connected to one end of the capacitor C11 and one end of the resistor R5, the collector of the PNP transistor Q3 is respectively connected to the anode of the Schottky diode D2, one end of the capacitor C22, and the base of the NPN transistor Q2, and the cathode of the Schottky diode D2 is respectively connected to one end of the resistor R38, the other end of the capacitor C22, and the base of the PNP transistor Q13 after passing through the Schottky diode D5; the emitter of the NPN transistor Q2 is respectively connected to one end of the resistor R17, one end of the resistor R24, and one end of the resistor R21 after passing through the resistor R16, and the other end of the resistor R21 is connected to the other end of the capacitor C15 One end of the resistor R24 ​​is connected to the emitter of the PNP transistor Q13, and the other end of the resistor R17 is connected to one end of the output port P3 and the power supply filter circuit respectively through the capacitor C16; the other end of the resistor R4, the other end of the resistor R7, the other end of the resistor R10, the other end of the capacitor C11, the other end of the resistor R5, and the collector of the NPN transistor Q2 are all connected to the power supply filter circuit; the collector of the PNP transistor Q8, the other end of the resistor R22, the other end of the resistor R31, the other end of the capacitor C24, the other end of the resistor R38, and the collector of the PNP transistor Q13 are all grounded.

5. The high-sensitivity ultrasonic preamplifier for rock high-temperature and high-pressure deformation experiments according to claim 4, characterized in that: The power supply filter circuit includes an inductor L1, an inductor L2, an inductor L3, a magnetic bead FB1, a magnetic bead FB3, a magnetic bead FB4, a magnetic bead FB5, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R1, and an LDO three-terminal voltage regulator chip YW1; the OUT pins of the LDO three-terminal voltage regulator chip YW1 are respectively connected to one end of the capacitor C2, one end of the capacitor C8, the other end of the resistor R4, the other end of the resistor R7, the other end of the resistor R10, and the capacitor C11. The other end of resistor R5, the collector of NPN transistor Q2, the other end of resistor R6, the other end of resistor R9, the other end of resistor R13, the other end of C10, the other end of R2, the collector on the right side of NPN dual triode Q4, the other end of resistor R3, the other end of resistor R12, the other end of resistor R14, the other end of capacitor C12, and the other end of resistor R15 are connected; the IN pin of LDO three-terminal voltage regulator chip YW1 is connected to one end of magnetic bead FB5 and one end of capacitor C1 respectively, and the other end of magnetic bead FB5 is connected to the other end of The ends are connected to the emitter of the transistor Q1 respectively, the base of the transistor Q1 is connected to one end of the capacitor C9 and one end of the resistor R1 respectively, the other end of the resistor R1 and the collector of the transistor Q1 are connected to one end of the magnetic bead FB4, the other end of the magnetic bead FB4 is connected to one end of the inductor L3 and one end of the capacitor C7 respectively, the other end of the inductor L3 is connected to one end of the capacitor C6 and one end of the magnetic bead FB3 respectively, the other end of the magnetic bead FB3 is connected to one end of the capacitor C5 and one end of the inductor L2 respectively, the other end of the inductor L2 is connected to the capacitor C 4 and one end of the magnetic bead FB1, the other end of the magnetic bead FB1 is respectively connected to one end of the inductor L1 and one end of the capacitor C3, the other end of the inductor L1 is respectively connected to one end of the capacitor C16 and one end of the output port P3; the GND pin of the LDO three-terminal voltage regulator chip YW1, the other end of the capacitor C8, the other end of the capacitor C2, the other end of the capacitor C1, the other end of the capacitor C9, the other end of the capacitor C7, the other end of the capacitor C6, the other end of the capacitor C5, the other end of the capacitor C4, and the other end of the capacitor C3 are all grounded.

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