A layout structure and related chip

By employing a sequential arrangement and consistent routing of resistor array units, voltage selection switch array units, and digital logic circuit units in a resistor-string digital-to-analog converter, the problem of increased chip area and cost in the resistor-string digital-to-analog converter is solved, achieving effective isolation between analog and digital signals and improving layout design efficiency.

CN115802599BActive Publication Date: 2025-10-24SHENZHEN INJOINIC TECH
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Patent Information

Application Number
CN202111402904.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-09-09
Publication Date
2025-10-24
Estimated Expiration
2041-09-09

AI Technical Summary

Technical Problem

As the accuracy of resistor-to-analog converters (DACs) increases, the number of switches and resistors required in the circuit increases dramatically, leading to larger chip area, higher costs, and increased crosstalk and interference between analog and digital signals.

Method used

The resistor array unit, voltage selection switch array unit, and digital logic circuit unit are arranged sequentially. The first metal layer and the second metal layer are used for wiring to ensure that the analog signal lines and digital signal lines are in the same direction and avoid crossing. Multiple voltage selection switch array units and digital logic circuit units are connected through wiring units.

Benefits of technology

It achieves a compact and aesthetically pleasing layout structure, reduces chip development costs, avoids crosstalk between analog and digital signals, and improves layout design efficiency.

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Abstract

The embodiment of the application provides a layout structure and a chip based on a resistance string digital-to-analog converter, at least one resistance array unit, at least one voltage selection switch array unit and a digital logic circuit unit are sequentially arranged in the layout structure based on the resistance string digital-to-analog converter, a first metal layer is used for wiring of a first analog signal line of the at least one resistance array unit, a second metal layer is used for wiring of a second analog signal line of the at least one resistance array unit and the at least one voltage selection switch array unit, and wiring of a first digital signal line of the at least one voltage selection switch array unit and the digital logic circuit unit, and the wiring directions of the second analog signal line and the first digital signal line are consistent. It can be seen that the wiring of such a layout structure is simple and clear, can meet the requirements of RDAC on device matching, can be flexibly used, improves the efficiency of layout design, and saves the chip development cost.
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Citation Information

Patent Citations

  • Digital-to-analog converter with linear amplification rate

    US20030112167A1