MOS transistor switching loss calculation method and device, equipment and storage medium

Abstract

The application discloses a MOS tube switching loss calculation method, device and equipment and a storage medium. By constructing a first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time, the first function and the second function are associated with key parameters of the MOS tube, a loss model is constructed based on the first function and the second function, a fitting function of the key parameters is constructed based on test data, known parameters and the fitting function are input into the loss model for processing, and switching loss is obtained. By constructing the loss model, the switching loss of the MOS tube can be calculated in advance through the known parameters in the circuit design stage, and the actual circuit detection is not needed, so that a guidance direction is provided for circuit design, the problem that the switching loss of the MOS tube in the designed circuit cannot meet actual application and repeated modification are avoided, and production cost is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of MOS switch loss, and particularly relate to a MOS switch loss calculation method, device, equipment and storage medium. BACKGROUND

[0002] In recent years, high-frequency switching power supply applications are more and more widely used. For high-frequency switching power supply, the commonly used switching tube is MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), which is referred to as MOS tube. The fast switching action speed and low switching loss of MOS tube make it can be widely used in high-frequency switching power supply.

[0003] The switching loss of MOS tube is due to the fact that the voltage and current changes are not instantaneous during the MOS tube opening or closing process, but need a period of time. During this period of time, there is an overlapping area of the current and voltage of the MOS tube, thereby generating loss. The existing calculation method of MOS tube switching loss usually detects the parameters (such as drain-source current, drain-source voltage and time, etc.) of MOS tube in the actual circuit, and then calculates the switching loss of MOS tube based on the detected parameters. However, this method depends on the existing circuit, and the switching loss of MOS tube cannot be calculated in advance in the circuit design stage. This results in the fact that the switching loss of MOS tube in the designed circuit cannot meet the actual application, which leads to repeated redesign and increases the production cost. SUMMARY

[0004] The present application provides a MOS switch loss calculation method, device, equipment and storage medium, which can calculate the switching loss of MOS tube in advance in the circuit design stage, thereby reducing the production cost.

[0005] In a first aspect, the embodiments of the present application provide a MOS switch loss calculation method, comprising:

[0006] A first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time are constructed, and the first function and the second function are associated with key parameters of the MOS tube;

[0007] A loss model is constructed based on the first function and the second function;

[0008] A fitting function of the key parameters is constructed based on test data;

[0009] The known parameters and the fitting function are input into the loss model for processing to obtain the switching loss.

[0010] In a second aspect, the embodiments of the present application further provide a MOS switch loss calculation device, comprising:

[0011] a function constructing module, configured to construct a first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time, the first function and the second function being associated with a key parameter of the MOS tube;

[0012] a model constructing module, configured to construct a loss model based on the first function and the second function;

[0013] a fitting function constructing module, configured to construct a fitting function of the key parameter based on test data;

[0014] a switch loss calculating module, configured to input the known parameter and the fitting function into the loss model for processing to obtain the switch loss.

[0015] In a third aspect, an embodiment of the present application further provides a computer device, comprising:

[0016] one or more processors;

[0017] a storage device configured to store one or more programs;

[0018] when the one or more programs are executed by the one or more processors, the one or more processors implement the MOS tube switch loss calculation method provided in the first aspect of the present application.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the MOS tube switch loss calculation method provided in the first aspect of the present application.

[0020] The MOS tube switch loss calculation method provided by the embodiment of the present application, by constructing a first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time, the first function and the second function being associated with a key parameter of the MOS tube, constructing a loss model based on the first function and the second function, constructing a fitting function of the key parameter based on test data, inputting the known parameter and the fitting function into the loss model for processing to obtain the switch loss. By constructing the loss model, the switch loss of the MOS tube can be calculated in advance through the known parameter in the circuit design stage, without relying on the detection of the actual circuit, providing a guidance direction for the circuit design, avoiding the problem that the switch loss of the MOS tube in the designed circuit cannot meet the actual application, leading to repeated modification, and reducing the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 Fig. 1 is a structural schematic diagram of a MOS tube switch circuit;

[0022] Figure 2 Fig. 3 is a waveform diagram of current and voltage in the process of the MOS tube switch.

[0023] Figure 3 Waveform diagram of current and voltage during MOS tube off process;

[0024] Figure 4 Flow chart of a MOS tube switching loss calculation method provided by the embodiment one of the present application;

[0025] Figure 5 Curve of output junction capacitance Coss changing with drain-source voltage Vds;

[0026] Figure 6 Curve of charge amount Qoss of output junction capacitance and drain-source voltage Vds;

[0027] Figure 7 Curve of charge amount Qgd of gate-drain junction capacitance Cgd changing with drain-source voltage Vds;

[0028] Figure 8 Curve of charge amount changing with drain-source voltage Vds when the drain-source voltage is discharged from Vds1 to Vfd;

[0029] Figure 9 Curve of capacitance Cgs and drain-source voltage Vds;

[0030] Figure 10 Fitting curve of Vgs(Ids);

[0031] Figure 11 Fitting curve of Vgs-Vth / Ids;

[0032] Figure 12 Fitting curve of Qgs1(Ids);

[0033] Figure 13 Vml(Ids) curve tested and fitted at 50 degrees;

[0034] Figure 14 Vml(Ids) curve tested and fitted at 80 degrees;

[0035] Figure 15 Vml(Ids) curve tested and fitted at 100 degrees;

[0036] Figure 16 Vml(Ids) curve tested and fitted at 120 degrees;

[0037] Figure 17 Temperature coefficient curve;

[0038] Figure 18 Qgs1(Ids) curve tested and fitted at 50 degrees;

[0039] Figure 19 Qgs1(Ids) curve tested and fitted at 80 degrees;

[0040] Figure 20 Qgs1(Ids) curve tested and fitted at 100 degrees;

[0041] Figure 21 Qgs1(Ids) curve tested and fitted at 120 degrees;

[0042] Figure 22 Temperature coefficient curve;

[0043] Figure 23 A turn-on model schematic diagram of a MOS tube of a flyback topology provided by the embodiment of the present application;

[0044] Figure 24 A voltage and current waveform diagram in the turn-on process of the MOS tube of the flyback topology provided by the embodiment of the present application;

[0045] Figure 25 A turn-off model schematic diagram of a MOS tube of a flyback topology provided by the embodiment of the present application;

[0046] Figure 26 A voltage and current waveform diagram in the turn-off process of the MOS tube of the flyback topology provided by the embodiment of the present application;

[0047] Figure 27 Another voltage and current waveform diagram in the turn-off process of the MOS tube of the flyback topology provided by the embodiment of the present application;

[0048] Figure 28 Eoss / Vds relationship curve;

[0049] Figure 29 A structure schematic diagram of a MOS tube switching loss calculation device provided by the embodiment of the present application;

[0050] Figure 30 A structure schematic diagram of a computer device provided by the fourth embodiment of the present application. DETAILED DESCRIPTION

[0051] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0052] Figure 1 A structure schematic diagram of a MOS tube switching circuit, Figure 2 A waveform diagram of current and voltage in the MOS tube turn-on process,Figure 3 The waveforms of current and voltage during the turn-off process of the MOSFET are shown below. Figure 1 and Figure 2 As shown, during the turn-on process of the MOSFET, at time t12, the drive voltage charges the gate-source capacitance Cgs through resistor Rgate, and the gate-source voltage Vgs rises exponentially to the turn-on threshold voltage Vth. At time t23, the MOSFET enters the amplification region, and the channel current Ids rises until it reaches the load current. At time t35, the drain-source current Ids remains constant, and the drain-source voltage Vds begins to decrease, dropping to Vfd at time t4. After that, due to the sudden increase in the output junction capacitance Coss, the decrease in drain-source voltage Vds slows down. During this period, the gate-source capacitance Cgs no longer consumes charge, and the gate-source voltage Vgs remains constant at Vmp. After time t5, the drain-source voltage Vds has dropped to 0, and the drive voltage continues to charge the gate-source capacitance Cgs. The gate-source and drain-source terminals operate independently, and the gate-source voltage Vgs rises exponentially to the drive voltage. The drain-source current Ids and drain-source voltage Vds cross over during time t25. The expression for the turn-on loss of the MOSFET is:

[0053]

[0054] Where fs is the switching frequency of the MOSFET.

[0055] like Figure 1 and Figure 3 As shown, during the MOSFET turn-off process, in time t01, the gate-source capacitance Cgs discharges through resistor Rgate, and the gate-source voltage Vgs slowly decreases to Vmp. In time t12, the MOSFET operates in the saturation region, and the drain-source voltage Vds slowly rises to the sudden voltage Vfd of the output junction capacitance Coss, approximately 30V. In time t23, the MOSFET operates in the amplification region, the drain-source current Ids remains constant, and the drain-source voltage Vds begins to rise significantly. During time t13, Cgs stops discharging, and the gate-source voltage Vgs remains constant at Vmp. In time t34, the drain-source voltage Vds has risen to its maximum voltage Vo. At this time, the MOSFET operates in the linear region, the gate-source capacitance Cgs continues to discharge through Rgate, and the gate-source voltage Vgs drops from Vmp to Vth, while Ids drops from its maximum value to 0. The drain-source voltage Vds and drain-source current Ids cross over during time t14, and the expression for the turn-off loss is:

[0056]

[0057] The switching loss of the MOS tube is the sum of the turn-on loss and the turn-off loss. From the above calculation process, it can be seen that the above calculation method needs to detect the actual circuit in the case where the actual circuit already exists, detect the changes of the drain-source voltage and the drain-source current in each time period, and the time length of each time period. However, this cannot be achieved in the circuit design stage.

[0058] Embodiment one

[0059] To solve the above problems, the embodiment of the present application provides a MOS tube switching loss calculation method, which can calculate the switching loss of the MOS tube in the design stage in advance by constructing a loss model and a fitting function of key parameters in the case where part of the parameters of the MOS tube are known. Figure 4 A flowchart of a MOS tube switching loss calculation method provided by the embodiment one of the present application, the embodiment can be applicable to pre-calculate the switching loss of the MOS tube in the circuit design stage, the method can be executed by a MOS tube switching loss calculation device provided by the embodiment of the present application, the device can be realized by software and / or hardware, and is usually configured in a computer device, such as Figure 4 The method specifically includes the following steps:

[0060] S101, a first function of the drain-source current with respect to time and a second function of the drain-source voltage with respect to time are constructed, and the first function and the second function are associated with key parameters of the MOS tube.

[0061] In the embodiment of the present application, the drain-source current is also called the channel current Ids, the first function of the drain-source current with respect to time Ids(t) is the change relationship of the drain-source current with time, and the second function of the drain-source voltage with respect to time Vds(t) is the change relationship of the drain-source voltage with time. In the embodiment of the present application, since the time is an unknown quantity, the first function and the second function can only be indirectly represented by the key parameters of the MOS tube. The key parameters include the Miller voltage of the MOS tube, the charge amount of the output junction capacitance, the charge amount of the gate-drain junction capacitance, and the charge amount of the gate-source junction capacitance. These key parameters are changing parameters in the MOS tube breaking process, and therefore, a large amount of test data is needed to construct the fitting function of the key parameters subsequently.

[0062] S102, a loss model is constructed based on the first function and the second function.

[0063] As described above, the switching loss of the MOS tube is generated due to the crossing of the drain-source current and the drain-source voltage. Therefore, to calculate the switching loss of the MOS tube is to calculate the integral of the product of the drain-source current and the drain-source voltage with respect to time, that is, to calculate the integral of the product of the first function and the second function with respect to time, and the loss model is expressed as:

[0064]

[0065] Wherein, T is the switching period of the MOS tube.

[0066] S103, constructing a fitting function of the key parameter based on the test data.

[0067] In the embodiment of the application, a large number of existing switching circuits are detected to obtain test data, and then a fitting function of the key parameter is constructed based on the test data.

[0068] The fitting function of the key parameter includes: a first fitting function of the Miller voltage with respect to the drain-source current and the temperature, a second fitting function of the charge quantity of the output junction capacitor with respect to the drain-source voltage, a third fitting function of the charge quantity of the gate-drain junction capacitor with respect to the drain-source voltage, and a fourth fitting function of the charge quantity of the gate-source junction capacitor with respect to the drain-source current. Specifically, a large number of data pairs of the key parameter and the corresponding variable are found from a large number of test data, and a fitting function of the key parameter and the corresponding variable is fitted based on the large number of data pairs of the key parameter and the corresponding variable.

[0069] S104, inputting the known parameter and the fitting function into the loss model for processing to obtain the switching loss.

[0070] In the embodiment of the application, the known parameter and the fitting function are input into the loss model for processing to obtain the switching loss. Specifically, the known parameter is a parameter known in the circuit design stage, for example, the switching frequency of the MOS tube, the driving voltage, the resistance value of the driving resistor, the turn-on voltage of the MOS tube, etc. The known parameter is substituted into the fitting function of the key parameter to determine the key parameter, and then the first function and the second function, and the time of each stage of the drain-source current and the drain-source voltage can be determined, and the product of the first function and the second function with respect to time can be calculated to obtain the switching loss of the MOS tube.

[0071] The calculation method of the MOS tube switching loss provided in the embodiment of the application constructs a first function of the drain-source current with respect to time and a second function of the drain-source voltage with respect to time, the first function and the second function are associated with the key parameter of the MOS tube, a loss model is constructed based on the first function and the second function, a fitting function of the key parameter is constructed based on the test data, the known parameter and the fitting function are input into the loss model for processing to obtain the switching loss. By constructing the loss model, the switching loss of the MOS tube can be calculated in advance in the circuit design stage through the known parameter, without relying on the detection of the actual circuit, which provides a guidance direction for the circuit design, avoids the problem that the switching loss of the MOS tube in the designed circuit cannot meet the actual application, and leads to repeated modification, and reduces the production cost.

[0072] Embodiment two

[0073] In order for those skilled in the art to more clearly understand the technical solutions of the present application, the technical solutions of the present application are described below in conjunction with specific examples.

[0074] The embodiment of the present application takes a flyback topology as an example, and the parameters of the flyback circuit are known as follows:

[0075] The input power of the flyback circuit: P in = 75W, the inductance of the transformer: L m = 370uH; the leakage inductance of the transformer: L r = 6uH; the switching frequency: f s = 65kHz; the turns ratio of the transformer: N ps = 7.667; the large electrolytic capacitance: C b = 100uF. The MOS platform voltage in CCM mode (continuous mode): V pCCM = V in + nV o = 213.9V; the MOS platform voltage in DCM mode (discontinuous mode):

[0076] The parameters of the drive circuit are known as follows:

[0077] The external drive resistance of the MOS: R gon = 68ohm; the VCC drive voltage: Vcc = 15V; the MOS off discharge resistance: R goff = 20ohm; the voltage for testing and reading the Coss mutation:

[0078] The basic parameters of the MOS are known as follows:

[0079] The threshold voltage for testing and reading the MOS turn-on at the working temperature: V th = 2V; the external capacitance of the MOS: C ds1 = 100pF; the capacitance parameter of the equivalent primary side of the secondary side: C eq = 40pF. The working temperature of the MOS is set to Temp = 100 degrees.

[0080] According to the above analysis, there are many variables in the system, and the final loss cannot be obtained by simply theoretical model calculation, so it is necessary to perform function fitting on the key parameters through testing and function fitting method, so as to calculate the final loss. In this paper, a specific MOS is taken as an example to illustrate the key parameters that need to be fitted:

[0081] (1) Qoss(Vds) curve: the charge amount Qoss of the output junction capacitance Coss, which varies with the drain-source voltage Vds.

[0082] Since the output junction capacitance Coss of MOSFET is a variable that changes with the drain-source voltage Vds, the loss caused thereby cannot be directly calculated. The curve of the output junction capacitance Coss changing with the drain-source voltage Vds can be obtained through testing as shown in Figure 5 .

[0083] According to the curve shown in Figure 5 , the integral of the output junction capacitance Coss can obtain Qoss:

[0084]

[0085] The Qoss in the above formula corresponds to the area surrounded by Vds and Coss in Figure 5 . In order to obtain the Qoss / Vds curve, Vds is divided into n equal parts, and the incremental interval is used, for example, 0.1V, 0.2V, 0.3V, and so on. The corresponding Coss(n) capacitance value can be obtained under each part of ΔVds(n) voltage. Then the change amount of the nth part of Vds is calculated as follows:

[0086] ΔV ds (n)=V ds (n+1)-V ds (n)

[0087] The increased charge amount is:

[0088]

[0089] Thus, the charge amount corresponding to Vds(n+1) is:

[0090] Q oss (n+1)=ΔQ oss (n)+Q oss (n)

[0091] Thus, the incremental charge amount ΔQoss(n) is continuously added to Qoss(n) to obtain the relationship curve of the output junction capacitance charge amount Qoss and the drain-source voltage Vds as shown in Figure 6 .

[0092] Through fitting, the function of Qoss about Vds can be obtained, wherein the first part of the curve before the turning point is the fitting curve when Vds≦30V, and the second part of the curve after the turning point is the fitting curve when Vds>30V. In actual application, the Vds voltage is generally greater than 30V, so the Q oss (V ds ) fitting curve formula is:

[0093] Q oss (V ds> 30V) = -1.1830 · 10 -10 · V ds 4 + 1.7736 · 10 -7 · V ds 3

[0094] - 9.4709 · 10 -5 · V ds 2 + 3.1730 · 10 -2 · V ds + 8.4419 · 10 1

[0095] (2) Qgd(Vds) curve: the curve of the charge amount Qgd of the gate-drain junction capacitance Cgd varying with Vds voltage.

[0096] From the foregoing, the gate-drain junction capacitance Cgd is a function of Vds, so the charge amount on the Cgd capacitor is also a function of Vds. By measurement, we can easily obtain the Cgd(Vds) curve, and by integrating Cgd, we can obtain Qgd:

[0097]

[0098] Actual test comparison found that due to the limitation of equipment, when measuring the Cgd(Vds) curve, the Cgd has dropped to several pico farads when Vds> 30V, and the equipment cannot measure accurately, resulting in large test error. At present, this paper adopts the method of point measurement, by reading the value of Qgd under different voltages, directly obtains the Qgd(Vds) curve. The obtained Qgd(Vds) curve is shown in Figure 7

[0099] When the MOS tube is turned off, we only need the charge amount required for the drain-source voltage to charge from voltage Vfd to voltage Vds1; when turned off, only the charge amount required for the drain-source voltage to discharge from Vds1 to Vfd. The charge amount is also related to Vds, and the charge amount is defined as Qgd1. Therefore, we need to obtain the Qgd1(Vds) curve, that is, the (Qgd(Vds)-Qgd(Vfd)) / Vds curve. The curve is shown in Figure 8

[0100] Q gd1 (V ds ) = 7.154 · 10 -7 · V ds 2 + 7.4714 · 10 -3 · V ds ​​-2.146-10 -1

[0101] (3) Vml(Ids) curve: the curve of the Miller voltage Vml versus the channel current Ids (note that Vth varies with temperature, so it is necessary to test at 100°C).

[0102] The gate-source voltage Vgs is a function of the channel current Ids. In fact, we cannot directly measure the Vml / Ids curve, but we can calculate it.

[0103] In fact, we can directly measure the fitting curve of Cgs(Vds), which is shown in Figure 9 It can be seen that Cgs does not vary with Vds, so we can consider that Cgs is a constant value, and we can take the average of the Cgs values obtained as follows.

[0104] In addition, we can directly measure the fitting curve of Vgs(Ids) (note that the measurement is performed at 100°C for the MOSFET), as shown in Figure 10

[0105] From the curve in Figure 10 we can easily obtain the Vth value, which is the Vgs value when the Ids current is greater than 0 A. Here, we can obtain Vth = 3 V. From this information, we can obtain the fitting curve of the Miller voltage Vml(Ids), which is the fitting curve of Vgs-Vth / Ids, as shown in Figure 11

[0106] It is worth noting that, to fit this parameter, the data used is in the range of 0.5 A to 7 A of channel current, which is because our applications are basically in this range, and in order to ensure the accuracy of the fitting, we only use this part of the data for fitting. This curve should be fitted using a power function, and the fitting function of Vml(Ids) obtained is:

[0107] (V gs -V th ) = V ml = 0.7198- I ds 0.4

[0108] (4) Qgs(Ids) curve: the curve of the charge amount Qgs of the gate-source junction capacitance Cgs versus the channel current Ids.

[0109] Figure 9 ​​It has been explained that the gate-source junction capacitance Cgs is a constant value and does not change with Vds, and Qgs1 is the amount of charge required by the gate-source junction capacitance Cgs when the gate-source voltage Vgs rises from Vth to Vml, which changes with Ids, and Qgs1 can be calculated by the following formula:

[0110] Q gs1 = Q gs -Q gsth = V ml ·C gs

[0111] According to the above formula, the fitting curve of Qgs1(Ids) can be obtained as shown in Figure 12 Similarly, the fitting function uses the channel current in the range of 0.5A-7A, and the curve is fitted using a power function, and the fitting function is obtained as:

[0112] Q gs1 (I in ) = 4.1291*10 -1 ·I ds 0.4

[0113] In addition, it is worth noting that Vml(Ids) and Qgs1(Ids) are functions of temperature, and if the MOS tube works at different temperatures, or the MOS tube itself heats up and changes its temperature, the temperature needs to be introduced into the actual calculation as a variable. Therefore, the temperature coefficient calculation method of Vml(Ids) and Qgs1(Ids) is introduced in the present application. The specific method is as follows:

[0114] Figures 13-16 The Vml(Ids) curves tested and fitted at different temperatures (50 degrees, 80 degrees, 100 degrees, and 120 degrees, respectively) are given, and according to the fitted curve, we can get the Vml value at any current Ids at four temperatures, as shown in the following table.

[0115] Tc 2A 3A 4A 5A 50 4.1151E-01 5.3199E-01 6.3831E-01 7.3520E-01 80 4.8445E-01 6.2629E-01 7.5146E-01 8.6553E-01 100 5.8106E-01 7.1773E-01 8.3379E-01 9.3658E-01 120 7.5660E-01 8.9624E-01 1.0107E+00 1.1094E+00

[0116] Take 50 degrees as the reference, divide the Vml voltage at each current at other temperatures by the Vml voltage at 50 degrees, and finally average the coefficients at each temperature to get the data shown in the following table.

[0117] Tc 5A 10A 15A 20A AVG 50 1 1 1 1 1 80 1.17726374 1.17726374 1.17726374 1.17726374 1.17726374 100 1.412019849 1.349147599 1.306244223 1.273907597 1.335329817 120 1.838614811 1.684689809 1.583358412 1.508976205 1.653909809

[0118] Finally, the curve is fitted with Tc as the abscissa and AVG as the ordinate, and the temperature coefficient curve can be obtained as shown in Figure 17 The fitting function of the temperature coefficient is:

[0119] Kvml (temp) = 1.0207 - 10 -4 ·temp 2 - 8.2041 - 10 -3 ·temp + 1.1597

[0120] Through the above analysis, the Vml(Ids) curve function of the MOS tube at 50 degrees is:

[0121] V ml (I in ) = 2.6529 - 10 -1 ·I ds 7.22·10-1

[0122] After introducing the temperature coefficient, the Vml(Ids) relationship of the MOS tube is:

[0123]

[0124] Temp is the working temperature of the MOS tube. Through the above calculation method, we can obtain the Vml-Ids relationship curve and the specific value of the MOS tube at different temperatures.

[0125] Similarly, we can use the same method to obtain the Qgs1-Ids curve at different temperatures, and thus obtain its temperature coefficient.

[0126] Figures 18-21 The Qgs1(Ids) curves at different temperatures (50 degrees, 80 degrees, 100 degrees, and 120 degrees, respectively) are given. According to the fitted curve, we can obtain the Qgs1 value at any current Ids at four temperatures, as shown in the following table.

[0127] Tc 2A 3A 4A 5A 50 2.3606E-01 3.1634E-01 3.8937E-01 4.5743E-01 80 2.6133E-01 3.3785E-01 4.0537E-01 4.6690E-01 100 3.1345E-01 3.8717E-01 4.4978E-01 5.0523E-01 120 4.0814E-01 4.8347E-01 5.4520E-01 5.9846E-01

[0128] Take 50 degrees as the reference, divide Qgs1 at each current at other temperatures by Qgs1 at 50 degrees, and then average the coefficients at each temperature to obtain the data shown in the following table.

[0129] Tc 5A 10A 15A 20A AVG 50 1 1 1 1 1 80 1.107089462 1.067995574 1.041098129 1.020702237 1.05922135 100 1.327852241 1.22392597 1.155160369 1.104493658 1.202858059 120 1.729018752 1.528324707 1.400222757 1.308301052 1.491466817

[0130] Finally, taking Tc as the abscissa and AVG as the ordinate to fit the curve, the temperature coefficient curve can be obtained, as shown in Figure 22 The function of the temperature coefficient fitting is:

[0131] K Qgs1 (temp) = 1.3396 - 10 -4 ·temp 2 - 1.5846 - 10-2 • temp + 1.4596

[0132] Through the above analysis, the Qgs1 (Ids) curve function of the MOS tube at 50 degrees is:

[0133]

[0134] After introducing the temperature coefficient, the Vml (Ids) relationship of the MOS tube is:

[0135]

[0136] In the above formula, Temp is the working temperature of the MOS tube. Through the above calculation method, we can obtain the relationship curve and specific numerical value of Qgs1 and Ids of the MOS tube at different temperatures.

[0137] The switching loss of the MOS tube includes turn-on loss, turn-off loss and capacitive loss caused by the output junction capacitor and the external parallel capacitor of the MOS tube. The calculation process of the turn-on loss, the turn-off loss and the capacitive loss caused by the output junction capacitor and the external parallel capacitor of the MOS tube is described below.

[0138] Figure 23 A turn-on model schematic diagram of the MOS tube of the flyback topology provided for the embodiment of the present application, Figure 24 The voltage and current waveform diagram in the turn-on process of the MOS tube of the flyback topology provided for the embodiment of the present application is as shown in Figure 23 and Figure 24 As shown in the figures, in the T01 time period, the driving current Igate (or driving voltage VCC) charges the gate-source junction capacitor Cgs of the MOS tube through the driving resistor Rg, the gate-source voltage Vgs rises exponentially, at T1 moment, the gate-source Vgs reaches the turn-on threshold voltage Vth. In the whole T01 time period, the drain-source voltage Vds and the drain-source current Ids remain unchanged, and the drain-source current Ids is 0, that is, in the whole T01 time period, the turn-on loss is 0.

[0139] In the T12 time period, the drive current Igate continues to charge the gate-source junction capacitance Cgs through the external resistance Rg, the channel of the MOS tube begins to conduct, the drain-source current Ids begins to rise, the current Idiode drops, and Im remains unchanged. Due to the change of the drain-source current Ids, the voltage on the drain inductance Lr rises. The drain-source voltage Vds of the MOS tube begins to drop, and the current Igate begins to branch, a part of which charges the gate-source junction capacitance Cgs, and a part of which charges the gate-drain junction capacitance Cgd. At the T2 moment, the drain-source voltage Vds drops to the sudden change voltage Vfd, the drain-source current rises to Ids1, and the gate-source voltage Vgs of the MOS tube rises to the Miller voltage Vml. Due to the existence of the drain inductance Lr, the drain-source voltage Vds changes simultaneously with the drain-source current Ids, that is, as long as the change of the drain-source current occurs, the change of the drain-source voltage will also occur.

[0140] The current balance equation for the gate point G of the MOS tube is:

[0141]

[0142] That is, the current flowing through the G point is equal to the current flowing through Rg. The current of Rg is equal to the voltage across Rg divided by its resistance. The voltage across Rg is equal to In the formula, since Ids is a changing curve, Vml will also change accordingly, so the function needs to be averaged.

[0143] The charge balance equation for the gate point G of the MOS tube is:

[0144]

[0145] That is, the charge amount passing through the G point is equal to the charge change amount of Cgd plus the charge change amount of Cgs. The number of charges required for the gate-source voltage Vgs of the MOS tube to rise from the opening threshold voltage Vth to the Miller voltage Vml is Q. gd1 (V p ) is the number of charges required for the drain-source voltage Vds of the MOS tube to drop from Vp to the sudden change voltage Vfd.

[0146] The equation of the voltage and current on the drain inductance Lr is as follows:

[0147]

[0148] Wherein, Id is the drain inductance current, is the drain inductance voltage.

[0149] The charge balance equation for the node D (i.e. the drain of the MOS tube) is:

[0150] I ds1 ·T 12= Q oss (V in +nV o )- Q oss (V fd )+ I d · T 12 +C ds1 · (V in +nV o -Vf d )

[0151] That is, the channel current Ids flowing through the MOS rises from 0 to Ids1 in T12 time, so the charge increment flowing through the channel is I ds1 · T 12 . This charge amount is equal to the charge increment I d · T 12 of the drain inductance current, the charge variation Q oss (V in +nV o )- Q oss (V fd ) of the output junction capacitor Coss, and the charge variation C ds1 · (V in +nV o -V fd ) of the MOS external parallel capacitor, wherein (Coss = Cds + Cgd).

[0152] In the equation set composed of the above gate G point current balance equation, the gate G point charge balance equation, the drain D point charge balance equation, and the drain inductance voltage equation, there are four unknown quantities, which are the gate current Igd + Igs, the channel current Ids1 at T2 time, the drain inductance Id, and the first stage time T12.

[0153] According to the fitting function of the above known parameters and key parameters, the above four unknown quantities can be solved.

[0154]

[0155] After all unknown quantities are solved, in fact, for the convenience of calculation, when calculating the turn-on loss, the channel current of the MOS is not used here, but the drain inductance current is used, and the loss caused by the output junction capacitor Coss and the MOS external parallel capacitor Cds1 will be calculated separately in subsequent embodiments.

[0156] Linearizing Vds(t) and Ids(t) waveforms in T12 time can be obtained as follows:

[0157]

[0158] Then the turn-on loss of the MOS in T12 time is:

[0159]

[0160] In the T23 period, the drain-source voltage Vds is reduced from Vfd to 0, and the channel current Ids continues to rise until it reaches the maximum current. Since dv / dt is very small, the change in Ids is also very small, and the gate-source voltage Vgs is approximately maintained at Vml unchanged.

[0161] The current equation of the gate-drain junction capacitance is established:

[0162]

[0163] That is, in the T23 time, Vgs does not change substantially, so Igs does not change, and therefore the current flowing through the drive resistor Rgon will only flow into Cgd.

[0164] The charge balance equation of the gate-drain junction capacitance is established:

[0165] I gd ·T 23 =Q gd (V fd )

[0166] That is, in the T23 time, the charge amount of the Cgd junction capacitance will continue to decrease until it decreases to 0, and the change amount of the charge amount of Cgd is Q gd (V fd ).

[0167] There are two unknown quantities in the current equation of the gate-drain junction capacitance and the charge balance equation of the gate-drain junction capacitance, which are T23 and Igd.

[0168] According to the fitting function of the above known parameters and key parameters, the above two unknown quantities can be solved.

[0169]

[0170] Linearizing the Vds(t) and Ids(t) waveforms in the T23 time can be expressed as follows: (Similarly, the current expression here does not use the channel current of MOS, but uses the drain inductance current, and the loss caused by the output junction capacitance Coss and the MOS external parallel capacitance Cds1 will be calculated separately in subsequent embodiments).

[0171]

[0172] Then the turn-on loss of the MOS tube in the T23 time is:

[0173]

[0174] Then the total turn-on loss is:

[0175]

[0176] Figure 25 A turn-off model schematic diagram of a MOS tube of a flyback topology provided for an embodiment of the present application, Figure 26 A voltage and current waveform diagram during the MOS tube turn-off process of the flyback topology provided for an embodiment of the present application, as shown in Figure 25 and Figure 26 In T01 time: the MOS tube gate-source junction capacitance Cgs discharges through the drive resistor Rg, the discharge current is Igs, the gate-source voltage Vgs decreases exponentially, at T1 moment, Vgs reaches the Miller voltage Vml. In the entire T01 time period, Vds and Ids remain unchanged. Vds is 0, i.e. in the entire T01 time period, the turn-off loss is 0.

[0177] In T12 time: the MOS tube gate-source junction capacitance Cgs stops discharging to the drive resistor Rg, the discharge current Igate is all used to maintain Cgs discharge, the MOS tube channel starts to close, Vds starts to rise, because in the low-voltage state, the MOS tube drain-source junction capacitance Cds is very large, Vds changes is not obvious, the channel current Ids can be approximately considered to remain unchanged, at T2 moment, the voltage Vds rises to Vfd, the MOS tube gate-source voltage Vgs approximately maintains the Miller voltage Vml unchanged.

[0178] The current equation of the gate-drain junction capacitance is established:

[0179]

[0180] That is, in T12 time, Vgs voltage is constant Vml voltage unchanged, so no current flows through Cgs, and the drive current will all flow through Cgd.

[0181] The charge balance equation of the gate-drain junction capacitance is established:

[0182] I gd ·T 12 =I gata ·T 12 =Q gd (V fd )

[0183] That is, in T12 time, according to the law of conservation of charge, the charge amount of Cgd will increase from 0 to Qgd(Vfd).

[0184] There are two unknown quantities in the above current equation of the gate-drain junction capacitance and the charge balance equation of the gate-drain junction capacitance, which are Igd and T12.

[0185] According to the fitting function of the above known parameters and key parameters, the above two unknown quantities can be solved.

[0186] According to the following known parameters:

[0187] R goff = 20 ohm;

[0188] Q gd (V fd ) = 3.1575 nC;

[0189]

[0190] And the fitting function of the key parameters:

[0191] V ml (I ds ) = 0.7198 · I ds 0.4

[0192] The two unknown quantities in CCM mode and DCM mode can be solved:

[0193]

[0194]

[0195] Linearizing the Vds(t) and Ids(t) waveform in T12 time can be expressed as follows:

[0196]

[0197] In the formula, Ioff is the current value when off.

[0198] Finally, the loss generated in T12 time in CCM mode and DCM mode is:

[0199]

[0200] In T23 time, due to the sudden decrease of junction capacitance Coss, dVds / dt increases rapidly, Vds rises rapidly, at this time the current Ioff begins to flow to each capacitor, the current on the capacitor is C*dv / dt, MOS tube channel current Ids begins to decrease, causing Vgs also begins to decrease, Cgs discharges through Rg. Vgs drops to Vml1. This state can be discussed in two cases.

[0201] Case 1: as Figure 26As shown, before Vds rises to Vp, Ids has already dropped to 0, in this case, there is no turn-off loss in T34 period, before T34 starts, the MOS channel has already closed, i.e. Vgs has dropped to Vth, all the current is used to charge the capacitors. The MOS is in linear region, which is a typical voltage-controlled current source,

[0202] Establish the current balance equation of the gate:

[0203]

[0204] That is, in T23 time, the current flowing through the gate G point is equal to the current flowing through Rgoff. The current of Rgoff is equal to the voltage across Rgoff divided by its resistance. The voltage across Rgoff is equal to Vml(Ids), and unlike the turn-on, at this time VCC is no longer driven, so the voltage across Rgoff is Vml(Ids).

[0205] Establish the charge balance equation of the gate:

[0206] (I gs +I gd )·T 23_1 =Q gd1 (V in1 )+Q gs1 (I ds , Temp)

[0207] That is, in T23 time, according to the conservation of charge, the amount of charge passing through G point is equal to the change in charge of Cgd plus the change in charge of Cgs.

[0208] Establish the charge balance equation of the drain:

[0209] I off ·T 23_1 =Q oss (V in1 )-Q oss (V fd )+(C ds1 +C eq )·(V in1 -V fd )

[0210] That is, the channel current Ids flowing through the MOS drops from Ioff to 0 in T23 time, and the drain-source voltage of the MOS rises from Vfd to Vin1. Therefore, the increase in charge flowing through the channel is I off ·T 23_1 . The change in charge of the Coss junction capacitor is Q oss (V in1 )-Q oss (V fd), the outer and the capacitance variation is: (C ds1 + C eq ) · (V in1 - V fd ).

[0211] It should be noted that the difference between the current when the switch is off and when it is on is that when it is on, the channel current flows to the drain inductance, the junction capacitance Coss and the outer and junction capacitance; when it is off, the drain inductance current flows to the channel, the junction capacitance Coss and the outer and capacitance Cds1 and the equivalent capacitance Ceq equivalent to the secondary side to the primary side.

[0212] The above equation set composed of the current balance equation of the gate, the charge balance equation of the gate and the charge balance equation of the drain has three unknowns, which are Igate, Vin1 and T23_1.

[0213] The known parameters are as follows:

[0214] R goff = 20 ohm; C ds1 = 100 pF; C eq = 40 pF

[0215] V fd = V ds_cut = 30 V; Q oss (V fd ) = 85.06 nC;

[0216] In combination with the fitting function of the aforementioned key parameters, the above three unknowns can be solved, and the solutions of the three unknowns in CCM mode and DCM mode can be obtained as follows:

[0217]

[0218]

[0219] After all the unknowns are solved, the Vds(t) and Ids(t) waveform in T23_1 time can be linearized to obtain the following expression:

[0220]

[0221] Therefore, the total off losses in CCM mode and DCM mode in case 1 can be obtained as follows:

[0222]

[0223] Therefore, the total off losses in CCM mode and DCM mode in case 1 can be obtained as follows:

[0224]

[0225] Case 2: Figure 27 Another voltage and current waveform diagram in the MOS tube off process of the flyback topology provided by the embodiment of the application, due to the reduction of Coss mutation, dVds / dt rapidly increases, Vds rapidly rises, at this time the current Ioff starts to flow to each capacitor, the current on the capacitor is C*dv / dt, the MOS tube channel current Ids starts to decrease, causing Vgs also starts to decrease, Cgs discharges through Rg. Vgs drops to Vmp1. When Vds rises to Vp, Ids has not decreased to 0, in this case, due to the effect of the drain inductance Lr, Vds continues to rise. The channel current Ids continues to decrease, Vgs starts to decrease from Vmp1 to Vth, but due to the resonance of the drain inductance and the Cds, Cgd, etc. Capacitors, will greatly delay the decrease of Ids. This part is divided into two time periods in this state, namely T23 time period and T34 time period.

[0226] In T23 time, MOSFET is in linear region, which is a typical voltage-controlled current source. The voltage Vds has risen to Vin+nVo (i.e. Vp), but the channel current has not decreased to 0, so the channel current at T23 time is required to establish the gate current equation as follows:

[0227]

[0228] The gate charge balance equation is as follows:

[0229] (I gs +I gd )·T 23_2 =Q gd1 (V in +nV o )+Q gs1 (I off )-Q gs1 (I mos )

[0230] That is, in T23 time, the channel current Ids flowing through the MOS tube decreases from Ioff to Imos, and the MOS drain-source voltage rises from Vfd to Vp (i.e. V in +nV o ). According to the charge conservation, the charge amount through the G point is equal to the charge change amount of Cgd plus the charge change amount of Cgs.

[0231] The charge balance equation of the drain is as follows:

[0232] (I off -I mos )·T 23_2 =Q oss (V p )-Q oss (Vfd )+(C ds1 +C eq )·(V p -V fd )

[0233] That is, the channel current Ids flowing through the MOS tube decreases from Ioff to Imos in the time T23, and the MOS drain-source voltage increases from Vfd to Vp. Therefore, the charge increment flowing through the channel is (I off -I mos )·T 23_2 . The charge variation of the output junction capacitor Coss is Q oss (V p )-Q oss (V fd ), and the charge variation of the outer capacitor is (C ds1 +C eq )·(V p -V fd ).

[0234] The equation group composed of the above-mentioned current balance equation of the gate, the charge balance equation of the gate, and the charge balance equation of the drain includes three unknown quantities, which are Igate, Imos, and T23_2, respectively.

[0235] The known parameters are as follows:

[0236] R goff = 20 ohm; V fd = V ds_cut = 30 V; Q oss (V fd ) = 85.06 nC;

[0237] C ds1 = 100 pF; C eq = 40 pF;

[0238]

[0239] In combination with the fitting function of the aforementioned key parameters, the above-mentioned three unknown quantities can be solved, and the solutions of the three unknown quantities in the CCM mode and the DCM mode are as follows:

[0240]

[0241]

[0242] It can be seen that the Imos calculated in this example is negative, and there is no real solution for T23 time, so it can be explained that the MOS tube parameters will not appear the off current of case 2 under this application condition, so the calculation method of case 1 needs to be used when finally calculating the loss.

[0243] If the calculated Imos is positive and less than the Ioff value, then the linearization of Ids(t) and Vds(t) can be obtained as follows.

[0244]

[0245] The loss in T23 time in case 2 is in CCM mode and DCM mode respectively:

[0246]

[0247] For case 2, there will also be a loss in T34 time, when Vds rises to Vp, Ids has not fallen to 0, due to the effect of leakage inductance Lr, Vds continues to rise. The channel current Ids continues to drop, Vgs starts to drop from Vmp1 to Vth, but due to the resonance of leakage inductance and Cds, Cgd and other capacitors, it will greatly delay the drop of Ids. To simplify the calculation, we regard 1 / 4 period of the resonance of leakage inductance and Cds, Cgd and other capacitors as T34 time, so we have:

[0248]

[0249] The resonance frequency is:

[0250]

[0251] Since Coss(Vds) is a variable, in the T34 time period of the off stage, Vds>Vin+nVo>200V, the change of Coss after 200V will not be too large, for the sake of simplifying the calculation, we define the junction capacitance value when Vds voltage is 300V for calculating the resonance frequency and T34 time. Therefore, the following known conditions are obtained:

[0252] C ds1 =100pF; C oss (300V)=10.9pF

[0253] The calculation results are as follows:

[0254]

[0255] The linearization of Ids(t) and Vds(t) in T34 time can be obtained as follows:

[0256]

[0257] The loss in T34 in case 2 is as follows in CCM mode and DCM mode respectively:

[0258]

[0259] Therefore, the total turn-off loss in CCM mode and DCM mode for case 2 is as follows:

[0260]

[0261] So far, the MOS turn-off loss has been calculated completely. Since there are two cases in T23, it can be determined whether the MOS is working in case 1 or case 2 according to whether the calculated value Imos is positive or negative.

[0262] In the foregoing, we mentioned that the output junction capacitance Coss and the MOS external capacitance Cds1 will generate loss when the MOS is turned on and turned off. In order to facilitate understanding and calculation, the loss in this part is calculated separately.

[0263] The loss generated by the output junction capacitance Coss can use the curve of Eoss, and the calculation formula of Eoss is as follows:

[0264]

[0265] Among them, Substituting it into the above formula, the calculation formula of Eoss is as follows:

[0266]

[0267] It can be seen that to obtain Eoss loss, Qoss needs to be divided into n equal parts, each charge increment is ΔQoss, and the nth charge increment is ΔQoss(n), and the calculation formula is as follows:

[0268] ΔQ oss (n)=Q oss (n+1)-Q oss (n)

[0269] Then the increased energy calculation formula is as follows:

[0270]

[0271] Similarly, each part of the increased energy ΔEoss(n) is continuously added to Eoss(n) to obtain the curve of Eoss / Vds as shown in Figure 28 .

[0272] From Figure 28It can be known that there is an inflection point when Vds≈30V, in order to make the fitting more accurate, Eoss / Vds is segmented and fitted from the inflection point, (the inflection point is generally taken as Vds=30V).

[0273] Wherein, the curve part before the inflection point is the fitting curve when Vds≦30V, and the curve part after the inflection point is the fitting curve when Vds>30V. In actual application, generally we will have Vds voltage greater than 30V, so the fitting curve formula that needs to be used is:

[0274] E oss (V ds >30V)=4.303·10 -6 ·V ds 2 +6.8222·10 -4 ·V ds +8.6009·10 -1

[0275] Therefore, the total loss generated by the output junction capacitance Coss junction capacitance can be obtained as:

[0276] P oss =E oss (V in +nV o )·f s

[0277] The known conditions in CCM mode and DCM mode are as follows:

[0278]

[0279] The output junction capacitance Coss junction capacitance loss in CCM mode and DCM mode is calculated respectively as:

[0280]

[0281] The loss caused by the external parallel capacitance Cds1 can be directly obtained using the following formula:

[0282]

[0283] The loss of the external parallel junction capacitance Cds1 in CCM mode and DCM mode is calculated respectively as:

[0284]

[0285] The MOS switch loss calculation method provided by the embodiment of the present application can calculate the switch loss of the MOS tube in advance by constructing a loss model and inputting known parameters in the circuit design stage, without relying on detection of the actual circuit, thereby providing a guidance direction for circuit design, avoiding the problem that the switch loss of the MOS tube in the designed circuit cannot meet the actual application, and reducing the production cost. In addition, not only the electrical characteristics of the MOS tube are considered, but also the temperature characteristics of the MOS tube are considered, and the concept of temperature coefficient is introduced. Therefore, in actual work, the loss of the MOS tube is affected by temperature, and therefore the temperature is also considered in actual calculation, so that more accurate and effective loss can be obtained. In addition, the loss caused by the inductive load and the loss caused by the capacitive load are calculated respectively, thereby improving the calculation accuracy of the switch loss. The MOS switch loss calculation method can be used to build a database of MOS tubes, that is, for the same MOS tube, its electrical characteristics and temperature characteristic parameters are relatively fixed, and the fitting method of the present application can be used to dataize these parameters and then perform parameterized modeling. Finally, it becomes a digital system, and the data can be directly called for subsequent derivation and analysis, thereby improving the calculation efficiency.

[0286] Embodiment three

[0287] Figure 29 The structure diagram of the MOS switch loss calculation device provided by the embodiment of the present application is shown in Figure 29 The device comprises:

[0288] The function construction module 301 is configured to construct a first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time, and the first function and the second function are associated with key parameters of the MOS tube.

[0289] The model construction module 302 is configured to construct a loss model based on the first function and the second function.

[0290] The fitting function construction module 303 is configured to construct a fitting function of the key parameters based on test data.

[0291] The switch loss calculation module 304 is configured to input the known parameters and the fitting function into the loss model for processing, so as to obtain the switch loss.

[0292] In some embodiments of the present application, the switch loss comprises turn-on loss and turn-off loss.

[0293] The turn-on loss comprises first turn-on loss in a first stage and second turn-on loss in a second stage, and the gate-source voltage rises from the threshold voltage to the Miller voltage in the first stage, and the drain-source voltage drops from the abrupt voltage to zero in the second stage.

[0294] The turn-off loss includes a first turn-off loss of a third stage and a second turn-off loss of a fourth stage, the drain-source voltage rises from zero to the mutation voltage in the third stage, and the gate-source voltage drops from the Miller voltage to the threshold voltage in the fourth stage.

[0295] The fitting function of the key parameters includes a first fitting function of the Miller voltage with respect to the drain-source current and temperature, a second fitting function of the charge amount of the output junction capacitance with respect to the drain-source voltage, a third fitting function of the charge amount of the gate-drain junction capacitance with respect to the drain-source voltage, and a fourth fitting function of the charge amount of the gate-source junction capacitance with respect to the drain-source current.

[0296] In some embodiments of the present application, the switch loss calculation module 304 includes a first calculation submodule for calculating a first turn-on loss, and the calculation process of the first turn-on loss is as follows:

[0297] An equation set composed of a current balance equation of the gate, a charge balance equation of the gate, a charge balance equation of the drain, and a drain inductance voltage equation is constructed;

[0298] The duration of the first stage and the drain inductance current are calculated based on the known parameters of the MOS tube, the fitting function of the key parameters, and the equation set;

[0299] The duration of the first stage and the drain inductance current are substituted into the loss model for processing to obtain the first turn-on loss.

[0300] In some embodiments of the present application, the switch loss calculation module 304 includes a second calculation submodule for calculating a second turn-on loss, and the calculation process of the second turn-on loss is as follows:

[0301] An equation set composed of a charge balance equation of the gate-drain junction capacitance and a current equation of the gate-drain junction capacitance is constructed;

[0302] The duration of the second stage and the drain inductance current are calculated based on the known parameters of the MOS tube, the fitting function of the key parameters, and the equation set;

[0303] The duration of the second stage and the drain inductance current are substituted into the loss model for processing to obtain the second turn-on loss.

[0304] In some embodiments of the present application, the switch loss calculation module 304 includes a third calculation submodule for calculating a first turn-off loss, and the calculation process of the first turn-off loss is as follows:

[0305] An equation set composed of a charge balance equation of the gate-drain junction capacitance and a current equation of the gate-drain junction capacitance is constructed;

[0306] calculating the duration of the third phase and the drain inductance current based on the known parameters of the MOS tube, the fitting function of the key parameters and the equation set;

[0307] processing the duration of the third phase and the drain inductance current in the loss model to obtain the first turn-off loss.

[0308] In some embodiments of the present application, the switch loss calculation module 304 comprises a fourth calculation submodule for calculating a second turn-off loss, and the calculation process of the second turn-off loss is as follows:

[0309] constructing an equation set composed of the current balance equation of the gate, the charge balance equation of the gate and the charge balance equation of the drain;

[0310] calculating the duration of the fourth phase, the gate current and the drain-source voltage based on the known parameters of the MOS tube, the fitting function of the key parameters and the equation set;

[0311] processing the duration of the fourth phase, the gate current and the drain-source voltage in the loss model to obtain the second turn-off loss.

[0312] In some embodiments of the present application, the switch loss further comprises a capacitive loss caused by the output junction capacitance and the external parallel capacitance of the MOS tube.

[0313] In some embodiments of the present application, the switch loss calculation module 304 comprises a fifth calculation submodule for calculating the capacitive loss, and the calculation process of the capacitive loss is as follows:

[0314] calculating the loss caused by the output junction capacitance based on the energy stored by the output junction capacitance and the switching frequency of the MOS tube;

[0315] calculating the loss caused by the external parallel capacitance based on the external parallel capacitance and the switching frequency of the MOS tube;

[0316] calculating the sum of the loss caused by the output junction capacitance and the loss caused by the external parallel capacitance as the capacitive loss.

[0317] The MOS tube switch loss calculation device described above can perform the MOS tube switch loss calculation method provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of performing the MOS tube switch loss calculation method.

[0318] Embodiment four

[0319] Embodiment four of the present application provides a computer device, Figure 30 As shown in the structural schematic diagram of the computer device provided in embodiment four of the present application, Figure 30 The computer device comprises:

[0320] The processor 401, the memory 402, the communication module 403, the input device 404 and the output device 405; the number of processors 401 in the mobile terminal can be one or more, Figure 30 The processor 401 in the mobile terminal is taken as an example; the processor 401, the memory 402, the communication module 403, the input device 404 and the output device 405 in the mobile terminal can be connected through a bus or other means, Figure 30 The processor 401, the memory 402, the communication module 403, the input device 404 and the output device 405 can be integrated on the computer equipment.

[0321] The memory 402 as a kind of computer readable storage medium, it can be used to store software program, computer executable program and module, such as the module corresponding to MOS tube switching loss calculation method in the above embodiment. The processor 401 is by running the software program, instruction and module stored in the memory 402, thereby executing the various function applications and data processing of computer equipment, that is, realizing the MOS tube switching loss calculation method described above.

[0322] The memory 402 can mainly include storage program area and storage data area, wherein the storage program area can store operating system, at least one application required by function; storage data area can store data created according to microcomputer use and the like. In addition, the memory 402 can include high-speed random access memory, and can also include nonvolatile memory, for example, at least one magnetic disk storage device, flash memory device or other nonvolatile solid-state memory device. In some examples, the memory 402 can further include a memory disposed remotely with respect to the processor 401, which can be connected to the electronic device through a network. Examples of the above network include but are not limited to the Internet, intranet, local area network, mobile communication network and combination thereof.

[0323] The communication module 403 is used to establish connection with external device (for example, intelligent terminal) and realize data interaction with external device. The input device 404 can be used to receive input digital or character information, and generate key signal input related to user settings and function control of computer equipment.

[0324] The computer equipment provided in the embodiment can execute the MOS tube switching loss calculation method provided in any of the above embodiments of the application, and has corresponding functions and beneficial effects.

[0325] Embodiment five

[0326] The embodiment five of the present application provides a storage medium comprising computer executable instructions, and a computer program is stored on the storage medium, and the computer program is executed by a processor to realize the MOS switch loss calculation method provided by any of the above embodiments of the present application, and the method comprises the following steps of:

[0327] constructing a first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time, the first function and the second function being associated with a key parameter of the MOS tube;

[0328] constructing a loss model based on the first function and the second function;

[0329] constructing a fitting function of the key parameter based on test data;

[0330] inputting the known parameter and the fitting function into the loss model for processing to obtain the switch loss.

[0331] It should be noted that, for the device, the apparatus and the storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts refer to the part of the method embodiments.

[0332] Through the above description of the embodiments, those skilled in the art can clearly understand that the present application can be realized by means of software and necessary general hardware, and of course can be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product can be stored in a computer readable storage medium, such as a floppy disk, a read-only memory (ROM), a random access memory (RAM), a FLASH, a hard disk or an optical disk, etc., and includes a plurality of instructions for causing a computer device (which can be a robot, a personal computer, a server or a network device, etc.) to execute the MOS switch loss calculation method described in any embodiment of the present application.

[0333] It should be noted that, in the above device, each module and sub-module included is only divided according to the function logic, but is not limited to the above division, as long as the corresponding function can be realized; in addition, the specific name of each functional module is only for easy distinction, and does not limit the protection scope of the present application.

[0334] It should be understood that aspects of the application can be implemented in hardware, software, firmware or a combination thereof. In the above embodiments, various steps or methods can be implemented in software or firmware which is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, and in another embodiment, any of the following technologies, known in the art, can be used: discrete logic circuitry having logic gates for implementing logic functions upon an application of data signals; application specific integrated circuits having appropriate combinational logic gates; programmable gate arrays (PGA), field programmable gate arrays (FPGA), and so forth.

[0335] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples.

[0336] Note that the above only describes the preferred embodiments of the present application and the principles of the technology applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A MOSFET switching loss calculation method, characterized by, The application is applied to a circuit design stage, comprising: constructing a first function of drain-source current with respect to time and a second function of drain-source voltage with respect to time, the first function and the second function being associated with key parameters of a MOS tube; constructing a loss model based on the first function and the second function; constructing a fitting function of the key parameters based on test data; inputting the known parameters and the fitting function into the loss model for processing to obtain switching loss; inputting the known parameters and the fitting function into the loss model for processing to obtain switching loss, comprising: substituting the known parameters into the fitting function of the key parameters to determine the key parameters; determining the first function and the second function from the key parameters; calculating the integral of the product of the first function and the second function with respect to time to obtain the switching loss of the MOS tube.

2. The MOSFET switching loss calculation method of claim 1, wherein, The switching loss comprises turn-on loss and turn-off loss; The turn-on loss comprises first turn-on loss in a first stage and second turn-on loss in a second stage, the gate-source voltage rising from a threshold voltage to a Miller voltage in the first stage, and the drain-source voltage falling from a sudden change voltage to zero in the second stage; The turn-off loss comprises first turn-off loss in a third stage and second turn-off loss in a fourth stage, the drain-source voltage rising from zero to the sudden change voltage in the third stage, and the gate-source voltage falling from the Miller voltage to the threshold voltage in the fourth stage; The fitting function of the key parameters comprises: a first fitting function of the Miller voltage with respect to drain-source current and temperature, a second fitting function of the charge amount of an output junction capacitor with respect to drain-source voltage, a third fitting function of the charge amount of a gate-drain junction capacitor with respect to drain-source voltage, and a fourth fitting function of the charge amount of a gate-source junction capacitor with respect to drain-source current.

3. The MOSFET switching loss calculation method of claim 2, wherein, The calculation process of the first turn-on loss is: constructing an equation set composed of a current balance equation of a gate electrode, a charge balance equation of the gate electrode, a charge balance equation of a drain electrode, and a drain inductance voltage equation; calculating the time length of the first stage and the drain inductance current based on the known parameters of the MOS tube, the fitting function of the key parameters, and the equation set; substituting the time length of the first stage and the drain inductance current into the loss model for processing to obtain the first turn-on loss.

4. The MOSFET switching loss calculation method of claim 2, wherein, The calculation process of the second turn-on loss is: constructing an equation set composed of a charge balance equation of a gate-drain junction capacitor and a current equation of the gate-drain junction capacitor; calculating the time length of the second stage and the drain inductance current based on the known parameters of the MOS tube, the fitting function of the key parameters, and the equation set; substituting the time length of the second stage and the drain inductance current into the loss model for processing to obtain the second turn-on loss.

5. The MOSFET switching loss calculation method of claim 2, wherein, The calculation process of the first turn-off loss is: constructing an equation set composed of a charge balance equation of a gate-drain junction capacitor and a current equation of the gate-drain junction capacitor; calculating the time length of the third stage and the drain inductance current based on the known parameters of the MOS tube, the fitting function of the key parameters, and the equation set; substituting the time length of the third stage and the drain inductance current into the loss model for processing to obtain the first turn-off loss.

6. The MOSFET switching loss calculation method of claim 2, wherein, The calculation process of the second turn-off loss is: constructing an equation set composed of a current balance equation of the gate, a charge balance equation of the gate and a charge balance equation of the drain; calculating the duration of the fourth phase, the gate current and the drain-source voltage based on the known parameters of the MOS transistor, the fitting function of the key parameter and the equation set; processing the duration of the fourth phase, the gate current and the drain-source voltage in the loss model to obtain the second turn-off loss.

7. The MOSFET switching loss calculation method of any one of claims 1-6, wherein, The switching loss further includes a capacitive loss caused by an output junction capacitance and an external parallel capacitance of the MOS transistor.

8. The MOSFET switching loss calculation method of claim 7, wherein, The calculation process of the capacitive loss is: calculating the loss caused by the output junction capacitance based on the energy stored by the output junction capacitance and the switching frequency of the MOS transistor; calculating the loss caused by the external parallel capacitance based on the external parallel capacitance and the switching frequency of the MOS transistor; calculating the sum of the loss caused by the output junction capacitance and the loss caused by the external parallel capacitance as the capacitive loss.

9. A MOSFET switching loss calculation device, comprising: application in the circuit design stage, comprising: a function construction module configured to construct a first function of the drain-source current with respect to time and a second function of the drain-source voltage with respect to time, the first function and the second function being associated with a key parameter of the MOS transistor; a model construction module configured to construct a loss model based on the first function and the second function; a fitting function construction module configured to construct a fitting function of the key parameter based on test data; a switching loss calculation module configured to input the known parameters and the fitting function into the loss model for processing to obtain a switching loss; the switching loss calculation module is configured to substitute the known parameters into the fitting function of the key parameter to determine the key parameter, determine the first function and the second function based on the key parameter, and calculate the integral of the product of the first function and the second function with respect to time to obtain the switching loss of the MOS transistor.

10. A computer device, comprising: comprise: one or more processors; a storage device configured to store one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the MOS transistor switching loss calculation method according to any one of claims 1-8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the MOS transistor switching loss calculation method according to any one of claims 1-8.

Images