Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a device region and a spacer region, the substrate comprising a substrate and a fin separated from the substrate in the device region and the spacer region, a gate structure being formed on top of the substrate across the fin, the gate structure covering part of the top and part of the sidewall of the fin; in the spacer region, etching to remove the gate structure and the fin, forming a groove exposing the top surface of the substrate and extending in the same direction as the fin; and forming a spacer structure in the groove. The probability of the fin in the device region being bent is reduced, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Moreover, FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a device region and a partition region; a fin protruding from the substrate in the device region; a gate structure located in the device region, the gate structure covering a portion of the top and a portion of the sidewalls of the fin; and a partition structure located in the partition region, the partition structure penetrating the gate structure and extending downward to the top of the substrate, the partition structure being aligned with the extending direction of the fin, and the partition structure dividing the corresponding gate structure in the extending direction of the gate structure.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a device region and a partition region, the substrate including a substrate and fins disposed on the substrate of the device region and the partition region, a gate structure spanning the fins being formed on the top of the substrate of the device region and the partition region, the gate structure covering a portion of the top and a portion of the sidewalls of the fins; etching away the gate structure and the fins in the partition region to form a groove exposing the top surface of the substrate and consistent with the extension direction of the fins; and forming a partition structure in the groove.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. After forming a gate structure spanning the fin on top of the substrate in the device region and the isolation region, the gate structure and the fin in the isolation region are then etched away. Compared to existing methods that remove the fin in the isolation region before forming the gate structure, this invention removes the gate structure and the fin in the isolation region after forming the gate structure. During the removal of the gate structure and the fin in the isolation region, the gate structure located in the device region can support the fin, reducing the probability of the fin in the device region bending, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 4 to 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 7 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one semiconductor structure formation method as an example.

[0013] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a device region 10A and a partition region 10B, and a fin 11 protruding on the substrate 10.

[0015] refer to Figure 2Remove the fin 11 in the partition area 10B.

[0016] refer to Figure 3 After removing the fin 11 in the partition region 10B, an isolation layer 12 is formed on the substrate 10 in the device region 10A and the partition region 10B, the isolation layer 12 covering the sidewall of the fin 11.

[0017] Research has revealed that during the formation of the isolation layer 12, an annealing process is used. The material of the isolation layer 12 located in the isolation region 10B is prone to generating significant stress on the fins 11 on both sides of the isolation region 10B during the annealing process, which increases the probability of the fins 11 on both sides of the isolation region 10B bending, thereby affecting the performance of the semiconductor structure.

[0018] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a device region and a partition region, the substrate including a substrate and fins disposed on the substrate of the device region and the partition region, a gate structure spanning the fins being formed on the top of the substrate of the device region and the partition region, the gate structure covering a portion of the top and a portion of the sidewalls of the fins; etching away the gate structure and the fins in the partition region to form a groove exposing the top surface of the substrate and consistent with the extension direction of the fins; and forming a partition structure in the groove.

[0019] In the scheme disclosed in the embodiments of the present invention, after forming a gate structure spanning the fin on the top of the substrate in the device region and the isolation region, the gate structure and the fin in the isolation region are then etched away. Compared with the existing scheme of removing the fin in the isolation region before forming the gate structure, the present invention removes the gate structure and the fin in the isolation region after forming the gate structure. During the removal of the gate structure and the fin in the isolation region, the gate structure located in the device region can support the fin, reducing the probability of the fin in the device region bending, thereby improving the performance of the semiconductor structure.

[0020] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figures 4 to 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 4 It is a top view. Figure 5 yes Figure 4 A cross-sectional view along the ab direction. Figure 6 yes Figure 4 A cross-sectional view along the cd direction.

[0022] The semiconductor structure includes: a substrate 200, the substrate 200 including a device region 200A and a partition region 200B; a fin 201, protruding from the substrate 200 in the device region 200A; a gate structure 203, located in the device region 200A, the gate structure 203 covering part of the top and part of the sidewalls of the fin 201; and a partition structure 212, located in the partition region 200B, the partition structure 212 penetrating the gate structure 203 and extending downward to the top of the substrate 200, the partition structure 212 being aligned with the extending direction of the fin 201, the fins 201 adjacent to the device region 200A being isolated by the partition structure 212, and the partition structure 212 dividing the corresponding gate structure 203 in the extending direction of the gate structure 203.

[0023] In this embodiment, during the semiconductor structure formation process, after forming a gate structure 203 spanning the fin 201 on the top of the substrate in the device region 200A and the isolation region 200B, the gate structure 203 and the fin 201 in the isolation region 200B are then etched away. During the removal of the gate structure 203 and the fin 201 in the isolation region 200B, the gate structure 203 located in the device region 200A can support the fin 201, reducing the probability of the fin 201 in the device region 200A bending, thereby improving the performance of the semiconductor structure.

[0024] The substrate 200 provides a process platform for the fabrication process.

[0025] The substrate 200 includes a device region 200A and an isolation region 200B. The device region 200A is the working area of ​​the semiconductor device, and the isolation region 200B is used to isolate adjacent semiconductor devices.

[0026] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0027] In this embodiment, the fin 201 is disposed on the substrate 200, and the fin 201 and the substrate 200 are an integral structure. The material of the fin 201 is the same as that of the substrate 200, which is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, or a group III-V semiconductor material.

[0028] In this embodiment, the semiconductor structure further includes an isolation layer 202 located on the substrate 200 exposed by the fin 201, the isolation layer 202 covering part of the sidewall of the fin 201.

[0029] The isolation layer 202 is used to isolate adjacent devices. The material of the isolation layer 202 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0030] In this embodiment, the gate structure 203 includes a metal gate structure.

[0031] Specifically, after forming the metal gate structure, the metal gate structure in the isolation region 200B is removed. This is different from the approach of forming the dummy gate structure, removing the dummy gate structure in the isolation region 200B, forming the isolation structure 212 in the isolation region 200B, and then forming the metal gate structure. This embodiment can increase the process window for forming the metal gate structure and reduce the process difficulty of forming the metal gate structure.

[0032] Meanwhile, when the device is in operation, the gate structure 209 is used to control the opening or closing of the conductive channel.

[0033] In this embodiment, the gate structure 209 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0034] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0035] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0036] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 207 located on the substrate 200 on the side of the gate structure 203 and the isolation structure 212, and the interlayer dielectric layer 204 covers the sidewalls of the gate structure 203 and the isolation structure 212.

[0037] The interlayer dielectric layer 207 is used to isolate adjacent devices. The material of the interlayer dielectric layer 207 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 207 is silicon oxide.

[0038] In this embodiment, the semiconductor structure further includes a sidewall 206 located between the gate structure 203 and the interlayer dielectric layer 207, and the sidewall 206 covers the sidewall of the gate structure 203 exposed by the partition structure 212.

[0039] The sidewall 206 is used to protect the sidewalls of the gate structure 203. The sidewall 206 can be a single-layer structure or a multilayer structure, and the material of the sidewall 206 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 206 is a single-layer structure, and the material of the sidewall 206 is silicon nitride.

[0040] The partition structure 212 is used to isolate adjacent device areas 200A.

[0041] In this embodiment, the partition structure 212 also penetrates the isolation layer 202 located in the partition area 200B.

[0042] Specifically, since the isolation layer 202 covers part of the sidewall of the fin 201, in order to completely remove the fin 201 in the partition area 200B, the partition structure 212 also penetrates the isolation layer 202 located in the partition area 200B.

[0043] It should be noted that the partition structure 212 also penetrates a portion of the substrate 200 of the partition region 200B, that is, the partition structure 212 is embedded in the substrate 200 of the partition region 200B.

[0044] Specifically, the partition structure 212 penetrates a portion of the substrate 200 in the partition region 200B, increasing the bottom depth of the partition structure 212 and thereby improving the isolation effect of the partition structure 212.

[0045] In other embodiments, the bottom of the partition structure may also be flush with the top of the substrate.

[0046] It should also be noted that the length and width of the partition structure 212 are specifically set according to the layout of the device region 200A and the partition region 200B. As an example, the partition structure 212 is shown to extend through both gate structures 203.

[0047] In this embodiment, the material of the partition structure 212 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide.

[0048] Specifically, silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide are all insulating materials with good electrical isolation properties.

[0049] Figures 7 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0050] refer to Figures 7 to 11 , Figure 7 It is a top view. Figure 8 yes Figure 7 A sectional view along the AB direction. Figure 9 It is a top view. Figure 10 yes Figure 9 A sectional view along the AB direction. Figure 11 yes Figure 9 A cross-sectional view along the CD direction provides a substrate including a device region 100A and a partition region 100B. The substrate includes a substrate 100 and fins 101 disposed on the substrate 100 of the device region 100A and the partition region 100B. A gate structure 103 is formed on the top of the substrate of the device region 100A and the partition region 100B, spanning the fins 101. The gate structure 103 covers a portion of the top and a portion of the sidewalls of the fins 101.

[0051] The substrate provides a process platform for subsequent process manufacturing.

[0052] The substrate includes a device region 100A and an isolation region 100B. The device region 100A is the working area of ​​the semiconductor device, and the isolation region 100B is used to isolate adjacent semiconductor devices.

[0053] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0054] In this embodiment, the fin 101 is disposed on the substrate 100, and the material of the fin 101 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, or a group III-V semiconductor material.

[0055] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 101, forming an isolation layer 102 on the substrate exposed by the fin 101, the isolation layer 102 covering a portion of the sidewall of the fin 101.

[0056] The isolation layer 102 is used to isolate adjacent devices. The material of the isolation layer 102 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.

[0057] In this embodiment, the process for forming the isolation layer 102 includes flowable chemical vapor deposition (FCVD).

[0058] It should be noted that at this time, fins 101 are also formed on the substrate 100 of the isolation region 100B. Since the fins 101 are evenly distributed on the substrate 100, the stress generated by the isolation layer 102 between adjacent fins 101 is relatively uniform during the formation of the isolation layer 102, thereby reducing the probability of the fins 101 in the device region 100A bending.

[0059] Reference Figure 9 and Figure 11 A gate structure 103 spanning the fin 101 is formed on the top of the substrate of the device region 100A and the isolation region 100B.

[0060] In this embodiment, the gate structure 103 includes a metal gate structure.

[0061] Specifically, after forming the metal gate structure, the metal gate structure in the isolation region 100B is removed. Compared to the scheme of forming the dummy gate structure, removing the dummy gate structure in the isolation region 100B, forming the isolation structure in the isolation region 100B, and then forming the metal gate structure, this embodiment can increase the process window for forming the metal gate structure and reduce the process difficulty of forming the metal gate structure.

[0062] Meanwhile, when the device is in operation, the gate structure 109 is used to control the opening or closing of the conductive channel.

[0063] In this embodiment, the gate structure 109 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0064] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0065] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0066] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0067] In other embodiments, the gate structure may also be a pseudo-gate structure.

[0068] In this embodiment, during the step of providing the substrate, an interlayer dielectric layer 107 is also formed on the substrate on the side of the gate structure 103, and the interlayer dielectric layer 107 covers the sidewall of the gate structure 103.

[0069] The interlayer dielectric layer 107 is used to isolate adjacent devices.

[0070] In this embodiment, the metal gate structure is formed using a back-gate process, and the interlayer dielectric layer 107 is also used to provide spatial location for the formation of the metal gate structure.

[0071] Furthermore, when the gate structure 103 and the fin 101 are subsequently etched away in the isolation region 100B to form a groove exposing the top surface of the substrate 100 and aligned with the extending direction of the fin 101, the interlayer dielectric layer 107 can also protect the fin 101 in the device region 100A. The material of the interlayer dielectric layer 107 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 107 is silicon oxide.

[0072] It should be noted that the sidewall of the gate structure 103 is also formed with a sidewall 106, and the interlayer dielectric layer 107 covers the sidewall of the sidewall 106 accordingly.

[0073] The sidewall 106 is used to protect the sidewalls of the gate structure 103. The sidewall 106 can be a single-layer structure or a multilayer structure, and the material of the sidewall 106 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 106 is a single-layer structure, and the material of the sidewall 106 is silicon nitride.

[0074] refer to Figures 12 to 17 , Figure 12 It is a top view. Figure 13 yes Figure 12 A sectional view along the AB direction. Figure 14 yes Figure 12 A sectional view along the CD direction. Figure 15 It is a top view. Figure 16 yes Figure 15 A sectional view along the AB direction. Figure 17yes Figure 15 In a cross-sectional view along the CD direction, the gate structure 103 and the fin 101 are etched away in the isolation region 100B to form a groove 110 that exposes the top surface of the substrate 100 and is aligned with the extending direction of the fin 101.

[0075] It should be noted that after the gate structure 103 is formed, the gate structure 103 and fin 101 in the isolation region 100B are removed. During the removal of the gate structure 103 and fin 101 in the isolation region 100B, the gate structure 103 located in the device region 100A can support the fin 101, reducing the probability of the fin 101 in the device region 100A bending, thereby improving the performance of the semiconductor structure.

[0076] It should also be noted that the groove 110 located in the partition area 100B provides space for the subsequent formation of the partition structure.

[0077] In this embodiment, in the isolation region 100B, the gate structure 103 and the fin 101 are sequentially etched away in the same step.

[0078] Specifically, the gate structure 103 and the fin 101 are removed in the same step. This embodiment can use a single photomask, thereby reducing the number of photomasks and photolithography steps, and reducing process costs while reducing process steps.

[0079] In this embodiment, the step of etching away the gate structure 103 and the fin 101 in the isolation region 100B includes: as follows Figures 12 to 14 As shown, a mask layer 108 with a mask opening 109 is formed on top of the gate structure 103. The extending direction of the mask opening 109 is consistent with the extending direction of the fin 101, and the mask opening 109 is located on top of the gate structure 103 and the fin 101 in the isolation region 100B; Figures 15 to 17 As shown, using the mask layer 108 as a mask, the gate structure 103 and fin 101 in the isolation region 100B are etched along the mask opening 109.

[0080] It should be noted that, since the isolation layer 102 covers part of the sidewall of the fin 101, in order to completely remove the fin 101 in the isolation region 100B, the isolation layer 102 is also etched away during the step of etching away the gate structure 103 and the fin 101.

[0081] In this embodiment, the process of etching away the gate structure 103 and the fin 101 in the isolation region 100B includes a dry etching process.

[0082] Specifically, the dry etching process includes anisotropic dry etching, which has the characteristic of anisotropic etching, with a longitudinal etching rate much greater than the lateral etching rate. This allows for highly accurate pattern transformation and reduces damage to the sidewalls of the gate structure 103 in the device region 100A during the etching removal of the gate structure 103 and the fin 101, thus ensuring the morphological quality of the sidewalls of the recess 110. Damage to the sidewalls of the nitride layer 120 and the oxide layer 114 is also minimized.

[0083] It should be noted that an interlayer dielectric layer 107 is formed on the substrate. During the formation of the groove 110, the interlayer dielectric layer 107 of the isolation region 100B is also etched accordingly, so that the substrate, the isolation layer 102, the gate structure 103 and the interlayer dielectric layer 107 together form the groove 110.

[0084] It should also be noted that, in the step of etching away the gate structure 103 and the fin 101, a portion of the substrate 100 is also etched away.

[0085] Specifically, etching removes a portion of the substrate 100, thereby increasing the depth of the groove 110 and improving the isolation effect of the partition structure subsequently formed in the groove 110.

[0086] In other embodiments, depending on process requirements, only the gate structure, fins, and isolation layer may be etched away, with the bottom of the groove flush with the top of the substrate.

[0087] In this embodiment, the mask layer 108 serves as an etching mask for removing the gate structure 103 and fin 101 of the isolation region 100B.

[0088] Specifically, the mask layer 108 includes an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

[0089] The organic material layer provides a flat surface for the formation of the photoresist layer, thereby improving the exposure effect during the formation of the photoresist layer. The organic material layer is made of organic materials. In this embodiment, the organic material layer is spin-on carbon (SOC). In other embodiments, the organic material layer may also be made of other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0090] The anti-reflective coating material includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.

[0091] In this embodiment, before removing the gate structure 103 and fin 101 of the blocking region 100B, the method further includes: using the photoresist layer as a mask, sequentially etching the anti-reflection coating and the organic material layer.

[0092] It should be noted that in other embodiments, the photoresist layer is consumed during the etching process of the anti-reflective coating and the organic material layer, and the first mask layer may accordingly consist only of the organic material layer and the anti-reflective coating located on the organic material layer.

[0093] It should also be noted that after forming the groove 110, the process also includes removing the mask layer 108.

[0094] Specifically, the process of removing the mask layer 108 includes an ashing process.

[0095] refer to Figures 18 to 22 , Figure 20 It is a top view. Figure 21 yes Figure 20 A sectional view along the AB direction. Figure 22 yes Figure 20 A cross-sectional view along the CD direction shows that a partition structure 112 is formed in the groove 110.

[0096] The partition structure 112 is used to isolate adjacent device areas 100A.

[0097] In this embodiment, the step of forming the partition structure 112 in the groove 110 includes: as follows Figures 18 to 19As shown, an insulating material layer 111 is formed on the top of the gate structure 103 and in the recess 110; as Figures 20 to 22 As shown, with the top of the gate structure 103 as the stop position, the isolation material layer 111 above the top of the gate structure 103 is planarized, and the remaining isolation material layer 111 in the groove 110 serves as the partition structure 112.

[0098] In this embodiment, a high aspect ratio (HARP) chemical vapor deposition process is used to form the isolation material layer 111. The HARP process can meet the filling requirements of openings with high aspect ratios; therefore, by employing the HARP process, the gap-filling effect of the isolation material layer 111 can be improved.

[0099] In this embodiment, in the step of forming the partition structure 112 in the groove 110, the material of the partition structure 112 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

[0100] Specifically, silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide are all insulating materials with good electrical isolation properties.

[0101] It should be noted that the length and width of the partition structure 112 are specifically set according to the layout of the device region 100A and the partition region 100B. As an example, the partition structure 112 is shown to extend through two gate structures 103.

[0102] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate including a device region and a partition region; Fins protrude from the substrate of the device region; A gate structure is located in the device region, and the gate structure covers a portion of the top and a portion of the sidewalls of the fin; A partition structure is located in the partition region. The partition structure penetrates the gate structure and extends downward to the top of the substrate. The partition structure is aligned with the extension direction of the fin. Fins of adjacent device regions are isolated by the partition structure, and the partition structure divides the corresponding gate structure in the extension direction of the gate structure. In this process, after the gate structure is formed, the gate structure and the fin in the isolation region are etched away to form a groove that exposes the top surface of the substrate and is consistent with the extension direction of the fin, and the groove is filled; and during the etching process of removing the gate structure and the fin, the gate structure located in the device region supports the fin, and the gate structure is a metal gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an isolation layer located on the substrate exposed by the fin, the isolation layer covering a portion of the sidewall of the fin; The partition structure also extends through the isolation layer located in the partition area.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an interlayer dielectric layer located on a substrate on the side of the gate structure and the isolation structure, the interlayer dielectric layer covering the sidewalls of the gate structure and the isolation structure.

4. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the partition structure includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a device region and a partition region, the substrate including a substrate and fins disposed on the substrate of the device region and the partition region, a gate structure is formed on the top of the substrate of the device region and the partition region, the gate structure covering a portion of the top and a portion of the sidewalls of the fin; In the isolation region, the gate structure and the fin are etched away to form a groove that exposes the top surface of the substrate and is consistent with the extension direction of the fin; A partition structure is formed in the groove; During the etching process to remove the gate structure and the fin, the gate structure located in the device region supports the fin, and the gate structure is a metal gate structure.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of providing the substrate, an interlayer dielectric layer is also formed on the substrate on the side of the gate structure, and the interlayer dielectric layer covers the sidewall of the gate structure.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the isolation region, the gate structure and the fin are sequentially etched away in the same step.

9. The method for forming a semiconductor structure as described in claim 6 or 8, characterized in that, In the isolation region, the step of etching away the gate structure and the fin includes: forming a mask layer with a mask opening on the top of the gate structure, the extension direction of the mask opening being consistent with the extension direction of the fin, and the mask opening being located on top of the gate structure and the fin in the isolation region; using the mask layer as a mask, etching the gate structure and the fin in the isolation region along the mask opening.

10. The method for forming a semiconductor structure as described in claim 6 or 7, characterized in that, The step of forming a partition structure in the groove includes: forming an isolation material layer in the top of the gate structure and in the groove; taking the top of the gate structure as a stop position, planarizing the isolation material layer above the top of the gate structure, and using the remaining isolation material layer in the groove as the partition structure.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of providing the substrate, an isolation layer is formed on the substrate exposed by the fin, the isolation layer covers part of the sidewall of the fin, and the gate structure is formed on the isolation layer; In the isolation region, during the step of etching away the gate structure and the fin, the isolation layer is also etched.

12. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the isolation region, the etching process for removing the gate structure and the fins includes a dry etching process.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

14. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of forming the partition structure in the groove, the material of the partition structure includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon carbide.

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