Thin-film transistor

Abstract

The application discloses a thin film transistor, which comprises a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source and a drain. The semiconductor layer comprises a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first shallow doped region, a second shallow doped region and a third shallow doped region. The first heavily doped region is located between the first semiconductor region and the second semiconductor region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. The first heavily doped region and the third heavily doped region are respectively located on two sides of the second semiconductor region. The first shallow doped region is located between the first heavily doped region and the first semiconductor region. The second shallow doped region is located between the first semiconductor region and the second heavily doped region. The third shallow doped region is located between the second semiconductor region and the first heavily doped region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third shallow doped region respectively. The top gate is electrically connected to the bottom gate. The source and the drain are electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer respectively.

Description

Technical Field

[0001] This invention relates to a thin-film transistor. Background Technology

[0002] Generally, flat panel displays use thin-film transistors (TFTs) to control the operation of each pixel; therefore, the quality of the TFTs directly affects the display's quality. As the resolution of flat panel displays continues to improve, the size of TFTs must also shrink. However, when the size of TFTs shrinks, smaller TFTs are less likely to have ideal electrical properties. Therefore, how to combine new designs to improve the electrical properties of TFTs is a major challenge for researchers. Summary of the Invention

[0003] This invention provides a thin-film transistor with excellent electrical properties.

[0004] The thin-film transistor of the present invention includes a bottom gate, a buffer layer, a semiconductor layer, a gate insulating layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The buffer layer is disposed on the bottom gate. The semiconductor layer is disposed on the buffer layer. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region is located between the first semiconductor region and the second semiconductor region. The first heavily doped region and the second heavily doped region are respectively located on opposite sides of the first semiconductor region. The first heavily doped region and the third heavily doped region are respectively located on opposite sides of the second semiconductor region. The first lightly doped region is located between the first heavily doped region and the first semiconductor region. The second lightly doped region is located between the first semiconductor region and the second heavily doped region. The third lightly doped region is located between the second semiconductor region and the first heavily doped region. The two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The gate insulating layer is disposed on the semiconductor layer. A top gate and a first auxiliary conductive pattern are disposed on a gate insulating layer and overlapped with a first semiconductor region and a second semiconductor region of a semiconductor layer, respectively, wherein the top gate is electrically connected to the bottom gate. The source and drain are electrically connected to a third heavily doped region and a second heavily doped region of the semiconductor layer, respectively. Attached Figure Description

[0005] Figures 1A to 1F This is a cross-sectional schematic diagram of the manufacturing process of a thin-film transistor according to the first embodiment of the present invention.

[0006] Figure 2 This is a top view schematic diagram of a thin-film transistor according to the first embodiment of the present invention.

[0007] Figure 3 This is a cross-sectional schematic diagram of a thin-film transistor according to a second embodiment of the present invention.

[0008] Figure 4This is a top view schematic diagram of a thin-film transistor according to a second embodiment of the present invention.

[0009] In the attached figures, the following labels are used:

[0010] 100, 100A: Thin-film transistor

[0011] 110: Bottom gate

[0012] 120: Buffer layer

[0013] 130, 130', 130”: Semiconductor layer

[0014] 131, 132, 133, 134, 135, 136, 137, 138-1, 138-2, 138-3, 138-4: Partial

[0015] 131a: First Semiconductor Region

[0016] 132a: First shallow doped region

[0017] 133a: Second shallow doped region

[0018] 134a: Second semiconductor region

[0019] 134a1, 134a2, 136a1, 136a2: End

[0020] 135a: Third shallow doped region

[0021] 136a: Third Semiconductor Region

[0022] 137a: Fourth shallow doped region

[0023] 138a: First doped region

[0024] 138b: Second doped region

[0025] 138c: Third doped region

[0026] 138d: Fourth doped region

[0027] 140: Gate insulation layer

[0028] 151: Top gate

[0029] 152: First auxiliary conductive pattern

[0030] 152e1, 152e2, 153e1, 153e2: Edges

[0031] 153: Second auxiliary conductive pattern

[0032] 161: First photoresist structure

[0033] 161': First photoresist pattern

[0034] 162: Second photoresist structure

[0035] 162a, 163a: Part One

[0036] 162b, 163b: Part Two

[0037] 162': Second photoresist pattern

[0038] 163: Third photoresist structure

[0039] 163': Third photoresist pattern

[0040] 171: Source Extreme

[0041] 172: Drain

[0042] A-A', B-B': section line

[0043] H161, H161', H162a, H162b, H162', H163a, H163b, H163': Thickness

[0044] i1, i2, i3, i4: Boundary

[0045] MT: Main transistor

[0046] ST1: First Sub-Transistor

[0047] ST2: Second Sub-Transistor

[0048] W1: First width

[0049] W2: Second width

[0050] W3: Third width

[0051] y: direction Detailed Implementation

[0052] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0053] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or an intermediate element may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected" to another element, no intermediate element is present. As used herein, "connection" can refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may involve the presence of other elements between the two elements.

[0054] As used herein, “about,” “approximately,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement under discussion and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0056] Figures 1A to 1F This is a cross-sectional schematic diagram of the manufacturing process of a thin-film transistor according to the first embodiment of the present invention.

[0057] Please refer to Figure 1A First, a bottom gate 110 is formed on a substrate (not shown). In this embodiment, the material of the bottom gate 110 is light-shielding. For example, in this embodiment, the material of the bottom gate 110 may be a metal. However, the invention is not limited thereto. According to other embodiments, the material of the bottom gate 110 may also be other conductive materials, such as alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials and other conductive materials.

[0058] Please refer to Figure 1A Next, a buffer layer 120 is formed on a substrate (not shown) to cover the bottom gate 110. In this embodiment, the material of the buffer layer 120 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material, or a combination thereof.

[0059] Please refer to Figure 1ANext, a semiconductor layer 130 is formed on the buffer layer 120. The semiconductor layer 130 is not yet doped. For example, in this embodiment, the semiconductor layer 130 may be made of polycrystalline silicon. However, the invention is not limited thereto, and in other embodiments, the semiconductor layer 130 may also be made of amorphous silicon, microcrystalline silicon, monocrystalline silicon, organic semiconductor materials, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials, or combinations thereof.

[0060] Please refer to Figure 1A Next, a gate insulating layer 140 is formed to cover the semiconductor layer 130. In this embodiment, the material of the gate insulating layer 140 may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material, or a combination thereof.

[0061] Please refer to Figure 1A Next, a top gate 151 and a first auxiliary conductive pattern 152 are formed on the gate insulating layer 140. The top gate 151 and the first auxiliary conductive pattern 152 are disposed on the gate insulating layer 140. In this embodiment, a second auxiliary conductive pattern 153 may also be formed simultaneously with the formation of the top gate 151 and the first auxiliary conductive pattern 152. The second auxiliary conductive pattern 153 is disposed on the gate insulating layer 140, and the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 are spaced apart. In this embodiment, the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 are made of metal. However, the present invention is not limited to this. According to other embodiments, the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 may also be made of other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

[0062] Please refer to Figure 1A Next, a first photoresist structure 161 and a second photoresist structure 162 are formed on the top gate 151 and the first auxiliary conductive pattern 152, respectively. The first photoresist structure 161 has a generally uniform thickness H161. The second photoresist structure 162 includes a first part 162a and a second part 162b with different thicknesses. The thickness H162a of the first part 162a of the second photoresist structure 162 is generally the same as the thickness H161 of the first photoresist structure 161, and the thickness H162b of the second part 162b of the second photoresist structure 162 is less than the thickness H162a of the first part 162a of the second photoresist structure 162.

[0063] In this embodiment, while forming the first photoresist structure 161 and the second photoresist structure 162, a third photoresist structure 163 can also be formed on the second auxiliary conductive pattern 153. The third photoresist structure 163 includes a first part 163a and a second part 163b with different thicknesses. The thickness H163a of the first part 163a of the third photoresist structure 163 is approximately the same as the thickness H161 of the first photoresist structure 161, and the thickness H163b of the second part 163b of the third photoresist structure 163 is less than the thickness H163a of the first part 163a of the third photoresist structure 163.

[0064] Please refer to Figure 1A and Figure 1B Next, an ashing process is performed to remove a portion of the first photoresist structure 161, a portion of the second photoresist structure 162, and a portion of the third photoresist structure 163, thereby forming the first photoresist pattern 161', the second photoresist pattern 162', and the third photoresist pattern 163', respectively.

[0065] After the ashing process, the thickness H161 of the first photoresist structure 161 is reduced to a thickness H161' to form a first photoresist pattern 161'. The first photoresist pattern 161' has a substantially uniform thickness H161'. The first photoresist pattern 161' extends beyond the top gate 151 and shields multiple portions 131, 132, and 133 of the semiconductor layer 130 located directly below the top gate 151 and on both sides of the top gate 151, respectively.

[0066] After the ashing process, the second portion 162b of the thinner second photoresist structure 162 (H162b) is completely removed, and the thickness H162a of the first portion 162a of the second photoresist structure 162 is reduced to thickness H162', thus forming the second photoresist pattern 162'. The first auxiliary conductive pattern 152 shields a portion 134 of the semiconductor layer 130 directly beneath it. The second photoresist pattern 162' extends beyond the first auxiliary conductive pattern 152. The portion of the second photoresist pattern 162' extending beyond the first auxiliary conductive pattern 152 shields a portion 135 of the semiconductor layer 130 to the right of the first auxiliary conductive pattern 152.

[0067] After the ashing process, the second portion 163b of the thinner third photoresist structure 163 (H163b) is completely removed, and the thickness H163a of the first portion 163a of the third photoresist structure 163 is reduced to thickness H163', forming the third photoresist pattern 163'. The second auxiliary conductive pattern 153 shields a portion 136 of the semiconductor layer 130 directly beneath it. The third photoresist pattern 163' extends beyond the second auxiliary conductive pattern 153. The portion of the third photoresist pattern 163' extending beyond the second auxiliary conductive pattern 153 shields a portion 137 of the semiconductor layer 130. The first photoresist pattern 161', the second photoresist pattern 162', the third photoresist pattern 163', the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 do not shield other portions 138-1, 138-2, 138-3, and 138-4 of the semiconductor layer 130.

[0068] Please refer to Figure 1B and Figure 1C Next, using the first photoresist pattern 161', the second photoresist pattern 162', the third photoresist pattern 163', the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 as masks, a heavy doping process is performed, so that multiple portions 138-1, 138-2, 138-3, and 138-4 of the semiconductor layer 130 that are not masked by the first photoresist pattern 161', the second photoresist pattern 162', the third photoresist pattern 163', the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 are heavily doped, thereby forming the first heavily doped region 138a, the second heavily doped region 138b, the third heavily doped region 138c, and the fourth heavily doped region 138d of the semiconductor layer 130', respectively. On the other hand, the various portions 131, 132, 133, 134, 135, 136, and 137 of the semiconductor layer 130, which are shielded by the first photoresist pattern 161', the second photoresist pattern 162', the third photoresist pattern 163', the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153, retain their original characteristics.

[0069] Please refer to Figure 1C and Figure 1D Next, the first photoresist pattern 161', the second photoresist pattern 162', and the third photoresist pattern 163' are removed. After the removal of the first photoresist pattern 161', the second photoresist pattern 162', and the third photoresist pattern 163', multiple portions 132, 133, 135, and 137 of the semiconductor layer 130, which were originally covered by the first photoresist pattern 161', the second photoresist pattern 162', and the third photoresist pattern 163', are no longer covered by the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153.

[0070] Please refer to Figure 1D and Figure 1E Next, using the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 as a mask, a shallow doping process is performed so that multiple portions 132, 133, 135, and 137 of the semiconductor layer 130' not masked by the top gate 151, the first auxiliary conductive pattern 152, and the second auxiliary conductive pattern 153 are shallowly doped to form the first shallow doped region 132a, the second shallow doped region 133a, the third shallow doped region 135a, and the fourth shallow doped region 137a of the semiconductor layer 130". After the shallow doping process is completed, multiple portions 131, 134, and 136 of the semiconductor layer 130" are not doped, and the multiple portions 131, 134, and 136 of the semiconductor layer 130" can be referred to as the first semiconductor region 131a, the second semiconductor region 134a, and the third semiconductor region 136a of the semiconductor layer 130", respectively.

[0071] Please refer to Figure 1F Next, a source 171 and a drain 172 are formed, and the source 171 and the drain 172 are electrically connected to the third doped region 138c and the fourth doped region 138d of the semiconductor layer 130, respectively. Thus, the thin-film transistor 100 of this embodiment is completed.

[0072] Figure 2 This is a top view schematic diagram of a thin-film transistor according to the first embodiment of the present invention. Figure 1F correspond Figure 2 The section line A-A'.

[0073] Please refer to Figure 1F and Figure 2 The thin-film transistor 100 includes a bottom gate 110, a buffer layer 120 disposed on the bottom gate 110, a semiconductor layer 130” disposed on the buffer layer 120, a gate insulating layer 140 disposed on the semiconductor layer 130”, a top gate 151 disposed on the gate insulating layer 140, a first auxiliary conductive pattern 152, a source 171, and a drain 172.

[0074] Semiconductor layer 130” includes a first semiconductor region 131a, a second semiconductor region 134a, a first heavily doped region 138a, a second heavily doped region 138b, a third heavily doped region 138c, a first lightly doped region 132a, a second lightly doped region 133a, and a third lightly doped region 135a. A top gate 151 and a first auxiliary conductive pattern 152 are respectively superimposed on the first semiconductor region 131a and the second semiconductor region 134a of semiconductor layer 130”. The top gate 151 is electrically connected to the bottom gate 110. In this embodiment, the first auxiliary conductive pattern 152 is floating.

[0075] The first heavily doped region 138a is located between the first semiconductor region 131a and the second semiconductor region 134a. The first heavily doped region 138a and the second heavily doped region 138b are located on opposite sides of the first semiconductor region 131a, and the first heavily doped region 138a and the third heavily doped region 138c are located on opposite sides of the second semiconductor region 134a. The first lightly doped region 132a is located between the first heavily doped region 138a and the first semiconductor region 131a. The second lightly doped region 133a is located between the first semiconductor region 131a and the second heavily doped region 138b. The third lightly doped region 135a is located between the second semiconductor region 134a and the first heavily doped region 138a. The two ends 134a1 and 134a2 of the second semiconductor region 134a are directly connected to the third heavily doped region 138c and the third lightly doped region 135a, respectively.

[0076] In this embodiment, the semiconductor layer 130” may optionally include a third semiconductor region 136a, a fourth lightly doped region 137a, and a fourth heavily doped region 138d. The second heavily doped region 138b is located between the second lightly doped region 133a and the third semiconductor region 136a. The third semiconductor region 136a is located between the second heavily doped region 138b and the fourth lightly doped region 137a. The fourth lightly doped region 137a is located between the third semiconductor region 136a and the fourth heavily doped region 138d. The two ends 136a1 and 136a2 of the third semiconductor region 136a are directly connected to the second heavily doped region 138b and the fourth lightly doped region 137a, respectively.

[0077] In this embodiment, the thin-film transistor 100 may also optionally include a second auxiliary conductive pattern 153 disposed on the gate insulating layer 140 and overlapping the third semiconductor region 136a of the semiconductor layer 130”. In this embodiment, the second auxiliary conductive pattern 153 is floating.

[0078] The source 171 and drain 172 are electrically connected to the third heavily doped region 138c and the fourth heavily doped region 138d of the semiconductor layer 130”, respectively. In this embodiment, the source 171 is directly electrically connected to the third heavily doped region 138c of the semiconductor layer 130, and the drain 172 is directly electrically connected to the fourth heavily doped region 138d of the semiconductor layer 130. The drain 172 is electrically connected to the second heavily doped region 138b of the semiconductor layer 130” through the fourth heavily doped region 138d, the fourth lightly doped region 137a and the third semiconductor region 136a of the semiconductor layer 130.

[0079] In this embodiment, the boundary i1 between the second semiconductor region 134a and the third lightly doped region 135a, and the boundary i2 between the second semiconductor region 134a and the third heavily doped region 138c, are substantially aligned with the opposite edges 152e1 and 152e2 of the first auxiliary conductive pattern 152, respectively. In this embodiment, the boundary i3 between the third semiconductor region 136a and the second heavily doped region 138b, and the boundary i4 between the third semiconductor region 136a and the fourth lightly doped region 137a, are substantially aligned with the opposite edges 153e1 and 153e2 of the second auxiliary conductive pattern 153, respectively.

[0080] Please refer to Figure 2 In this embodiment, the top gate 151 has a first width W1 in the y-direction, the first auxiliary conductive pattern 152 has a second width W2 in the y-direction, and the second auxiliary conductive pattern 153 has a third width W3 in the y-direction, wherein the second width W2 and the third width W3 are smaller than the first width W1. For example, in this embodiment, the first width W1 is greater than or equal to 1.5 μm and less than or equal to 6 μm, the second width W2 is greater than or equal to 0.5 μm and less than or equal to 1 μm, and the third width W3 is greater than or equal to 0.5 μm and less than or equal to 1 μm, but the present invention is not limited thereto.

[0081] Please refer to Figure 1F and Figure 2 The thin-film transistor 100 may include a main transistor MT and a first sub-transistor ST1. The main transistor MT includes a top gate 151, a portion of a bottom gate 110 electrically connected to the top gate 151, a first semiconductor region 131a, a first lightly doped region 132a, a second lightly doped region 133a, a source 171, and a drain 172, wherein the first lightly doped region 132a and the second lightly doped region 133a are generally symmetrically disposed on both sides of the first semiconductor region 131a. In other words, the lightly doped regions of the main transistor MT are symmetrically designed. The first sub-transistor ST1 includes a first auxiliary conductive pattern 152, a second semiconductor region 134a, a third heavily doped region 138c, a third lightly doped region 135a, a source 171, and a drain 172, wherein the third lightly doped region 135a is provided on one side of the second semiconductor region 134a, while no lightly doped region is provided between the other side of the second semiconductor region 134a and the third heavily doped region 138c. In other words, the shallow doped region of the first sub-transistor ST1 is designed asymmetrically.

[0082] In this embodiment, the thin-film transistor 100 may further include a second sub-transistor ST2. The second sub-transistor ST2 includes a second auxiliary conductive pattern 153, a portion of the bottom gate 110, a third semiconductor region 136a, a second heavily doped region 138b, and a fourth lightly doped region 137a. The fourth lightly doped region 137a is provided on one side of the third semiconductor region 136a, while no lightly doped region is provided between the other side of the third semiconductor region 136a and the second heavily doped region 138b. That is, the lightly doped region of the second sub-transistor ST2 is asymmetrically arranged.

[0083] The thin-film transistor 100 includes at least the aforementioned main transistor MT and the aforementioned first sub-transistor ST1. Notably, the top gate 151 and bottom gate 110 of the main transistor MT are electrically connected, the shallow doped region of the main transistor MT is symmetrically designed, while the shallow doped region of the first sub-transistor ST1 is asymmetrically designed. This improves the electron mobility and turn-on current of the thin-film transistor 100.

[0084] It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals used to represent the same or similar components, and descriptions of the same technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0085] Figure 3 This is a cross-sectional schematic diagram of a thin-film transistor according to a second embodiment of the present invention. Figure 4 This is a top view schematic diagram of a thin-film transistor according to a second embodiment of the present invention. Figure 3 right Figure 4 The section line B-B'.

[0086] Figure 3 and Figure 4 Thin-film transistor 100A and Figure 1F and Figure 2 Similar to the thin-film transistor 100, the difference between the two is: Figure 3 and Figure 4 The 100A thin-film transistor is omitted. Figure 1F and Figure 2 The second sub-transistor ST2.

[0087] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A thin-film transistor, characterized in that, include: One bottom gate; A buffer layer is disposed on the bottom gate; A semiconductor layer is disposed on the buffer layer, wherein the semiconductor layer includes: A first semiconductor region and a second semiconductor region; A first heavily doped region, a second heavily doped region, and a third heavily doped region, wherein the first heavily doped region is located between the first semiconductor region and the second semiconductor region, the first heavily doped region and the second heavily doped region are respectively located on both sides of the first semiconductor region, and the first heavily doped region and the third heavily doped region are respectively located on both sides of the second semiconductor region; and A first shallow doped region, a second shallow doped region, and a third shallow doped region, wherein the first shallow doped region is located between the first heavily doped region and the first semiconductor region, the second shallow doped region is located between the first semiconductor region and the second heavily doped region, and the third shallow doped region is located between the second semiconductor region and the first heavily doped region, and the two ends of the second semiconductor region are directly connected to the third heavily doped region and the third shallow doped region, respectively. A gate insulating layer is disposed on the semiconductor layer; A top gate and a first auxiliary conductive pattern are disposed on the gate insulating layer and respectively overlapped on the first semiconductor region and the second semiconductor region of the semiconductor layer, wherein the top gate is electrically connected to the bottom gate; and A source and a drain are electrically connected to the third doped region and the second doped region of the semiconductor layer, respectively.

2. The thin-film transistor as claimed in claim 1, characterized in that, The boundary between the second semiconductor region and the third lightly doped region and the boundary between the second semiconductor region and the third heavily doped region are substantially aligned with the opposite two edges of the first auxiliary conductive pattern.

3. The thin-film transistor as claimed in claim 1, characterized in that, The first auxiliary conductive pattern is floating.

4. The thin-film transistor as claimed in claim 1, characterized in that, The top gate has a first width in one direction, the first width being greater than or equal to 1.5 μm and less than or equal to 6 μm, and the first auxiliary conductive pattern has a second width in the same direction, the second width being greater than or equal to 0.5 μm and less than or equal to 1 μm.

5. The thin-film transistor as claimed in claim 1, characterized in that, The semiconductor layer further includes a third semiconductor region, a fourth lightly doped region, and a fourth heavily doped region. The second heavily doped region is located between the second lightly doped region and the third semiconductor region. The third semiconductor region is located between the second heavily doped region and the fourth lightly doped region. The fourth lightly doped region is located between the third semiconductor region and the fourth heavily doped region. The drain is electrically connected to the fourth heavily doped region of the semiconductor layer, and both ends of the third semiconductor region are directly connected to the second heavily doped region and the fourth lightly doped region, respectively. The thin-film transistor further includes a second auxiliary conductive pattern disposed on the gate insulating layer and superimposed on the third semiconductor region of the semiconductor layer.

6. The thin-film transistor as claimed in claim 5, characterized in that, The boundary between the third semiconductor region and the second heavily doped region and the boundary between the third semiconductor region and the fourth lightly doped region are substantially aligned with the opposite two edges of the second auxiliary conductive pattern.

7. The thin-film transistor as claimed in claim 5, characterized in that, The second auxiliary conductive pattern is floating.

8. The thin-film transistor as claimed in claim 5, characterized in that, The top gate has a first width in one direction, the first width being greater than or equal to 1.5 μm and less than or equal to 6 μm, and the second auxiliary conductive pattern has a third width in the same direction, the third width being greater than or equal to 0.5 μm and less than or equal to 1 μm.

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