Display panel and display device

Abstract

This invention relates to a display panel and a display device. In a narrow bezel design, the display panel of this invention does not compress the distribution range of the light-emitting functional layer. Instead, it removes the light-emitting functional layer covering the conductive traces, the planarization layer, and a portion of the pixel definition layer in the non-display area using laser etching. This ensures that the boundary of the light-emitting functional layer in the non-display area is located between the second trace sub-area and the display area. Therefore, in a narrow bezel design, the light-emitting functional layer avoids covering the conductive traces in the non-display area, preventing abnormal electrical connections between the conductive traces in the non-display area and the second conductive layer.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays, also known as organic electroluminescent displays or organic light-emitting semiconductors, offer numerous advantages. OLEDs boast low voltage requirements, high energy efficiency, fast response times, lightweight, thinness, simple structure, low cost, wide viewing angles, near-infinite contrast ratios, low power consumption, and extremely high response speeds, making them one of the most important display technologies today.

[0003] To improve the user experience, the bezels of display panels are gradually being reduced. To meet customer demands, display panel manufacturers are also simultaneously developing narrow bezel technology.

[0004] Currently, to prevent the light-emitting functional layer from affecting the electrical connection performance between the conductive units and the cathode, the light-emitting functional layer is designed with a precision margin in mind during bezel design. The extent of the light-emitting functional layer's distribution within the bezel is related to the manufacturer's production capabilities. When implementing a narrow bezel design, the distribution range of the light-emitting functional layer can be compressed, but this may result in the light-emitting functional layer being too thin in some openings at the edges of the pixel definition layer, leading to abnormal light emission in the display panel. Furthermore, current processes may not be able to compress the distribution range of the light-emitting functional layer. On the other hand, if the distribution range of the light-emitting functional layer is not compressed, it may cause the light-emitting functional layer to cover the conductive units in the non-display area, affecting the connection between the conductive units and the cathode in the non-display area, leading to abnormal scrapping of the display panel. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel and display device that can solve the problems of abnormal light emission and high manufacturing difficulty in the existing technology when the distribution range of the light-emitting functional layer is compressed; and abnormal scrapping of the display panel due to not compressing the distribution range of the light-emitting functional layer.

[0006] To address the aforementioned problems, the present invention provides a display panel comprising: a display area and a non-display area disposed on at least one side of the display area, the non-display area comprising: a first trace sub-region, a gate driving sub-region, and a second trace sub-region disposed sequentially closer to the display area; the display panel further comprising: a substrate; a driving circuit layer disposed on one side of the substrate; the driving circuit layer comprising: a pixel driving circuit disposed in the display area, a first trace disposed in the first trace sub-region, a gate driving circuit disposed in the gate driving sub-region, and a second trace disposed in the second trace sub-region, the gate driving circuit being electrically connected to a corresponding pixel driving circuit, and the second trace being electrically connected to a corresponding pixel driving circuit; a planarization layer disposed on the side of the driving circuit layer away from the substrate; and a first conductive layer disposed on the planarization layer away from the substrate. On one side of the substrate, the first conductive layer includes: a conductive trace disposed in the non-display area and a first electrode disposed in the display area, the first electrode being electrically connected to the corresponding pixel driving circuit, and the conductive trace being electrically connected to the first trace; a pixel definition layer disposed on the side of the first conductive layer away from the substrate, the pixel definition layer having a pixel opening corresponding to the first electrode; a light-emitting functional layer disposed on the side of the pixel definition layer away from the substrate, the light-emitting functional layer covering the display area and extending to the non-display area, the boundary of the light-emitting functional layer in the non-display area being between the second trace sub-area and the display area; and a second conductive layer disposed on the side of the light-emitting functional layer away from the substrate, the second conductive layer covering the display area and extending to the non-display area, and being electrically connected to the conductive trace.

[0007] Furthermore, the boundary of the light-emitting functional layer in the non-display area is located between the second trace and the display area.

[0008] Furthermore, the conductive traces are spaced apart from the light-emitting functional layer, and the second conductive layer is in direct contact with at least a portion of the upper surface of the flat layer located between the conductive traces and the light-emitting functional layer.

[0009] Furthermore, the roughness of at least a portion of the conductive traces on the surface away from the substrate is greater than the roughness of the surface of the first electrode on the surface away from the substrate.

[0010] Furthermore, the thickness of the planarization layer located between the conductive trace and the pixel definition layer is less than the thickness of the planarization layer located in the display area.

[0011] Furthermore, the pixel definition layer has a stepped structure on the side near the non-display area, and the boundary of the light-emitting functional layer in the non-display area is located between the stepped structure and the display area.

[0012] Furthermore, the second conductive layer covers the stepped structure.

[0013] Furthermore, the display panel further includes: a first dam disposed on the side of the planarization layer away from the substrate, and at least a portion of the conductive traces disposed between the first dam and the planarization layer; and a second dam disposed on the side of the planarization layer away from the substrate and located on the side of the first dam away from the display area, wherein at least a portion of the conductive traces are disposed between the first dam and the planarization layer.

[0014] Furthermore, the display panel further includes an encapsulation layer disposed on the side of the second conductive layer away from the substrate. The encapsulation layer includes a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked sequentially. The first inorganic encapsulation sublayer is in direct contact with the upper surface of the conductive trace between the first dam and the second dam.

[0015] To address the aforementioned problems, the present invention also provides a display device comprising the display panel described herein.

[0016] The advantages of this invention are: when the display panel of this invention is designed with a narrow bezel, the distribution range of the light-emitting functional layer is not compressed. The light-emitting functional layer covering the conductive traces, the planarization layer, and part of the pixel definition layer in the non-display area is removed by laser etching, so that the boundary of the light-emitting functional layer in the non-display area is located between the second trace sub-area and the display area. Thus, when the bezel is designed with a narrow bezel, the light-emitting functional layer is prevented from covering the conductive traces in the non-display area, and the phenomenon of abnormal electrical connection between the conductive traces in the non-display area and the second conductive layer is avoided. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a plan view of the display panel according to Embodiment 1 of the present invention;

[0019] Figure 2 yes Figure 1 AA section diagram;

[0020] Figure 3 This is a schematic diagram of the structure of the light-emitting unit and the light-emitting functional layer on the pixel electrode in Embodiment 1;

[0021] Figure 4 This is a diagram illustrating the manufacturing steps of the display panel according to Embodiment 1 of the present invention;

[0022] Figure 5 This is a schematic diagram of the light-emitting functional layer on the laser-etched conductive unit in Embodiment 1 of the present invention;

[0023] Figure 6 This is a schematic diagram of the display panel structure according to Embodiment 2 of the present invention;

[0024] Figure 7 This is a schematic diagram of the light-emitting functional layer on the laser-etched conductive unit in Embodiment 2 of the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] 100. Display panel; 101. Display area;

[0027] 102. Non-display area; 1021. First wiring sub-area;

[0028] 1022, Gate driving sub-region; 1023, Second routing sub-region;

[0029] 1. Substrate; 2. Driving circuit layer;

[0030] 3. Planarization layer; 4. First conductive layer;

[0031] 5. Pixel definition layer; 6. Emissive layer;

[0032] 7. Second conductive layer; 8. First dam;

[0033] 9. Second dam; 10. Light-emitting unit;

[0034] 21. Pixel driving circuit; 22. First trace;

[0035] 23. Gate drive circuit; 24. Second trace;

[0036] 25. Insulation layer;

[0037] 41. Conductive trace; 42. First electrode;

[0038] 51. Stepped structure;

[0039] 61. First light-emitting functional layer; 62. Second light-emitting functional layer. Detailed Implementation

[0040] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, and to demonstrate that the present invention can be implemented, making the disclosed technical content of the present invention clearer and enabling those skilled in the art to more easily understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein. The following description of the embodiments is not intended to limit the scope of the present invention.

[0041] The directional terms used in this invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this invention, and not for limiting the scope of protection of this invention.

[0042] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component.

[0043] Example 1

[0044] This embodiment provides a display device. The display device includes mobile phones, computers, MP3 players, MP4 players, tablet computers, televisions, or digital cameras, etc. The display device includes a display panel 100. The display panel 100 includes a display area 101 and a non-display area 102 disposed on at least one side of the display area 101.

[0045] like Figure 1 As shown, in this embodiment, the display panel 100 includes a display area 101 and a non-display area 102 surrounding the display area 101.

[0046] like Figure 2 As shown, the non-display area 102 includes: a first wiring sub-area 1021, a gate driving sub-area 1022, and a second wiring sub-area 1023, which are arranged sequentially and gradually close to the display area 101.

[0047] like Figure 2 As shown, the display panel 100 includes: a substrate 1, a driving circuit layer 2, a planarization layer 3, a first conductive layer 4, a pixel definition layer 5, a light-emitting functional layer 6, and a second conductive layer 7.

[0048] The substrate 1 is made of materials including glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate. In this embodiment, the substrate 1 is made of polyimide, which gives it good impact resistance and effectively protects the display panel 100.

[0049] The driving circuit layer 2 is disposed on one side of the substrate 1. The driving circuit layer 2 includes: a pixel driving circuit 21, a first trace 22, a gate driving circuit 23, a second trace 24, and an insulating layer 25.

[0050] The pixel driving circuit 21 is disposed on one side of the substrate 1 of the display area 101. Multiple pixel driving circuits 21 are disposed at intervals on the substrate 1 of the display area 101. Each pixel driving circuit 21 includes film layers such as an active layer (not shown), a gate (not shown), a source / drain electrode (not shown), and a gate insulating layer (not shown).

[0051] The first trace 22 is disposed on one side of the substrate 1 of the first trace sub-region 1021. In this embodiment, the first trace 22 is a low-voltage power supply line.

[0052] The gate driving circuit 23 is disposed on one side of the substrate 1 of the gate driving sub-region 1022. The gate driving circuit 23 is electrically connected to the corresponding pixel driving circuit 21.

[0053] The second trace 24 is disposed on one side of the substrate 1 of the second trace sub-region 1023. In this embodiment, the second trace 24 is a reset signal line. The second trace 24 is electrically connected to the corresponding pixel driving circuit 21.

[0054] The insulating layer 25 is disposed on the substrate 1 between two adjacent pixel driving circuits 21, on the substrate 1 between the first trace 22 and the gate driving circuit 23, on the substrate 1 between the gate driving circuit 23 and the second trace 24, and on the substrate 1 between the second trace 24 and the pixel driving circuit 21. The insulating layer 25 may be formed by extending an insulating film layer such as the gate insulating layer of the pixel driving circuit 21.

[0055] The planarization layer 3 is disposed on the side of the driving circuit layer 2 away from the substrate 1. The material of the planarization layer 3 can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc. The main purpose of the planarization layer 3 is to provide a flat surface for the fabrication of the film layer on the side away from the substrate 1.

[0056] The first conductive layer 4 is disposed on the side of the planarization layer 3 away from the substrate 1. The first conductive layer 4 includes conductive traces 41 disposed in the non-display area 102 and first electrodes 42 disposed in the display area 101. The first electrode 42 is electrically connected to a corresponding pixel driving circuit 21, and the conductive traces 41 are electrically connected to the first traces 22. Specifically, each first electrode 42 passes through the planarization layer 3 and is electrically connected to the drain of a corresponding pixel driving circuit 21. In this embodiment, the material of the first electrode 42 is the same as the material of the conductive traces 41, thus allowing the first electrode 42 and the conductive traces 41 to be fabricated using the same process. In other embodiments, the material of the first electrode 42 may be different from the material of the conductive traces 41.

[0057] In this embodiment, the pixel definition layer 5 is disposed on the side of the first conductive layer 4 away from the substrate 1, and the pixel definition layer 5 has a pixel opening corresponding to the first electrode 42. It is worth noting that, in this embodiment, the boundary line between the display area 101 and the non-display area 102 is the boundary of the projection of the outermost pixel opening of the pixel definition layer 5 onto the substrate 1.

[0058] The light-emitting functional layer 6 is disposed on the side of the pixel definition layer 5 away from the substrate 1, and the light-emitting functional layer 6 covers the display area 101 and extends to the non-display area 102.

[0059] In this design, the boundary of the light-emitting functional layer 6 in the non-display area 102 is located between the second trace sub-area 1023 and the display area 101. Specifically, the boundary of the light-emitting functional layer 6 in the non-display area 102 is located between the second trace 24 and the display area 101. Therefore, when the display panel 100 is designed with a narrow bezel, the distribution range of the light-emitting functional layer 6 is not compressed. The light-emitting functional layer 6, which covers the conductive trace 41, the planarization layer 3, and part of the pixel definition layer 5 in the non-display area 102, is removed by laser etching. This ensures that the boundary of the light-emitting functional layer 6 in the non-display area 102 is located between the second trace 24 and the display area 101. Consequently, in the narrow bezel design, the light-emitting functional layer 6 is prevented from covering the conductive trace 41 in the non-display area 102, thus preventing abnormal electrical connections between the conductive trace 41 and the second conductive layer 7 in the non-display area 102.

[0060] The second conductive layer 7 is disposed on the side of the light-emitting functional layer 6 away from the substrate 1. The second conductive layer 7 covers the display area 101 and extends to the non-display area 102, and is electrically connected to the conductive trace 41.

[0061] The conductive trace 41 is spaced apart from the light-emitting functional layer 6, and the second conductive layer 7 is in direct contact with at least a portion of the upper surface of the flat layer 3 located between the conductive trace 41 and the light-emitting functional layer 6.

[0062] To achieve the narrow bezel design, the structure of the non-display area 102 needs to be compressed. In this embodiment, the display panel 100 also includes a first dam 8 and a second dam 9.

[0063] The first dam 8 is disposed on the side of the flat layer 3 away from the substrate 1, and at least a portion of the conductive traces 41 are disposed between the first dam 8 and the flat layer 3.

[0064] The second dam 9 is disposed on the side of the planarization layer 3 away from the substrate 1 and on the side of the first dam 8 away from the display area 101, wherein at least a portion of the conductive traces 41 are disposed between the first dam 8 and the planarization layer 3.

[0065] like Figure 3 As shown, the display panel 100 also includes a plurality of light-emitting units 10. The light-emitting units 10 are disposed one-to-one within the pixel openings of the pixel definition layer 5.

[0066] like Figure 3 As shown, the light-emitting functional layer 6 includes a first light-emitting functional layer 61 and a second light-emitting functional layer 62.

[0067] The first light-emitting functional layer 61 is disposed between the light-emitting unit 10 and the first electrode 42, and extends to cover the surface of the pixel definition layer 5 on the side away from the substrate 1. Specifically, the first light-emitting functional layer 61 includes film structures such as a hole injection layer, a hole transport layer, and an electron blocking layer.

[0068] The second light-emitting functional layer 62 is disposed on the side of the light-emitting unit 10 away from the substrate 1 and extends to cover the first light-emitting functional layer 61. Specifically, the second light-emitting functional layer 62 includes film structures such as an electron transport layer, an electron injection layer, and a hole blocking layer.

[0069] The display panel 100 further includes an encapsulation layer (not shown) disposed on the side of the second conductive layer 7 away from the substrate 1. The encapsulation layer includes a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked in sequence. The first inorganic encapsulation sublayer is in direct contact with the upper surface of the conductive trace 41 between the first dam 8 and the second dam 9.

[0070] like Figure 4As shown, this embodiment also provides a method for fabricating the display panel 100 of this embodiment, including the following steps: S1, providing a substrate 1, defining a display area 101 and a non-display area 102 disposed on at least one side of the display area 101 on the substrate 1, the non-display area 102 including: a first wiring sub-region 1021, a gate driving sub-region 1022, and a second wiring sub-region 1023 disposed sequentially close to the display area 101; S2, fabricating a driving circuit layer 2 on the substrate 1 within the non-display area 102, the driving circuit... Layer 2 includes: a pixel driving circuit 21 disposed in the display area 101, a first trace 22 disposed in the first trace sub-region 1021, a gate driving circuit 23 disposed in the gate driving sub-region 1022, and a second trace 24 disposed in the second trace sub-region 1023. The gate driving circuit 23 is electrically connected to the corresponding pixel driving circuit 21, and the second trace 24 is electrically connected to the corresponding pixel driving circuit 21; S3, a planarization layer 3 is prepared on the side of the driving circuit layer 2 away from the substrate 1; S4, A first conductive layer 4 is formed on the side of the planarization layer 3 away from the substrate 1. The first conductive layer 4 includes: a conductive trace 41 disposed in the non-display area 102 and a first electrode 42 disposed in the display area 101. The first electrode 42 is electrically connected to the corresponding pixel driving circuit 21. The conductive trace 41 is electrically connected to the first trace 22. S5. A pixel definition layer 5 is formed on the side of the first conductive layer 4 away from the substrate 1. The pixel definition layer 5 has a pixel opening corresponding to the first electrode 42. S6. A light-emitting functional layer 6 is formed on the side of the pixel definition layer 5 away from the substrate 1. The light-emitting functional layer 6 covers the display area 101 and extends to the non-display area 102. The boundary of the light-emitting functional layer 6 in the non-display area 102 is located between the second trace sub-area 1023 and the display area 101. S7. A second conductive layer 7 is formed on the side of the light-emitting functional layer 6 away from the substrate 1. The second conductive layer 7 covers the display area 101 and extends to the non-display area 102, and is electrically connected to the conductive trace 41.

[0071] In this embodiment, the conductive trace 41 and the first electrode 42 are prepared using the same process. In other embodiments, the conductive trace 41 and the first electrode 42 can also be prepared separately.

[0072] like Figure 5As shown, in step S6, when designing a narrow bezel, since the distribution range of the light-emitting functional layer 6 is not compressed, the light-emitting functional layer 6 will cover the flat layer 3 and conductive traces 41 in the non-display area. The light-emitting functional layer 6 covering the conductive traces 41, the flat layer 3, and part of the pixel definition layer 5 in the non-display area 102 is removed by laser etching. This makes the boundary of the light-emitting functional layer 6 in the non-display area 102 between the second trace 24 and the display area 101. Thus, in the narrow bezel design, the light-emitting functional layer 6 is prevented from covering the conductive traces 41 in the non-display area 102, and the abnormal electrical connection between the conductive traces 41 and the second conductive layer 7 in the non-display area 102 is avoided.

[0073] When removing the light-emitting functional layer 6 by laser etching, due to the limitations of the current laser etching process, the surface of some of the conductive traces 41 on the side away from the substrate 1 is rough. The roughness of at least some of the conductive traces 41 on the side away from the substrate 1 is greater than the roughness of the surface of the first electrode 42 on the side away from the substrate 1.

[0074] When laser etching removes the light-emitting functional layer 6, due to the limitations of the current laser etching process precision, the thickness of the flattening layer 3 located between the conductive trace 41 and the pixel definition layer 5 is less than the thickness of the flattening layer 3 located in the display area 101.

[0075] Example 2

[0076] like Figure 6 As shown, this embodiment includes most of the technical features of embodiment 1. The difference between this embodiment and embodiment 1 is that in this embodiment, the pixel definition layer 5 of the non-display area has at least one step structure 51 on the side near the non-display area 102. The boundary of the light-emitting functional layer 6 in the non-display area 102 is located between the step structure 51 and the display area 102. The second conductive layer 7 covers the step structure 51. The shape of the step structure 51 includes at least one of right angles and rounded corners. In this embodiment, the step structure 51 is a right angle. Specifically, in this embodiment, before laser etching removes the light-emitting functional layer 6, at least one step structure 51 is formed on the side of the pixel definition layer 5 of the non-display area 102 near the non-display area 102. In other embodiments, at least one step structure 51 can be formed on the side of the pixel definition layer 5 of the non-display area 102 near the non-display area 102 during the laser etching process to remove the light-emitting functional layer 6.

[0077] like Figure 7As shown, when designing a narrow bezel, because the distribution range of the light-emitting functional layer is not compressed, the light-emitting functional layer 6 will cover the planarization layer 3 and conductive traces 41 of the non-display area 102. The light-emitting functional layer 6 covering the conductive traces 41, the planarization layer 3, and part of the pixel definition layer 5 of the non-display area 102 is removed by laser etching. This makes the boundary of the light-emitting functional layer 6 in the non-display area 102 between the second trace 24 and the display area 101. Thus, in the narrow bezel design, the light-emitting functional layer 6 is prevented from covering the conductive traces 41 of the non-display area 102, and the abnormal electrical connection between the conductive traces 41 and the second conductive layer 7 of the non-display area 102 is avoided.

[0078] The above provides a detailed description of a display panel and display device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: A display area and a non-display area disposed on at least one side of the display area, wherein the non-display area includes: a first wiring sub-region, a gate driving sub-region, and a second wiring sub-region disposed sequentially and gradually closer to the display area; The display panel also includes: substrate; A driving circuit layer is disposed on one side of the substrate; the driving circuit layer includes: a pixel driving circuit disposed in the display area, a first trace disposed in the first trace sub-region, a gate driving circuit disposed in the gate driving sub-region, and a second trace disposed in the second trace sub-region, wherein the gate driving circuit is electrically connected to the corresponding pixel driving circuit, and the second trace is electrically connected to the corresponding pixel driving circuit. A planarization layer is disposed on the side of the driving circuit layer away from the substrate; A first conductive layer is disposed on the side of the planarization layer away from the substrate. The first conductive layer includes: a conductive trace disposed in the non-display area and a first electrode disposed in the display area. The first electrode is electrically connected to the corresponding pixel driving circuit, and the conductive trace is electrically connected to the first trace. A pixel definition layer is disposed on the side of the first conductive layer away from the substrate, and the pixel definition layer has a pixel opening corresponding to the first electrode; A light-emitting functional layer is disposed on the side of the pixel definition layer away from the substrate. The light-emitting functional layer covers the display area and extends into the non-display area. The boundary of the light-emitting functional layer in the non-display area is located between the second trace sub-area and the display area. A second conductive layer is disposed on the side of the light-emitting functional layer away from the substrate. The second conductive layer covers the display area and extends to the non-display area, and is electrically connected to the conductive trace. The conductive traces are spaced apart from the light-emitting functional layer, and the second conductive layer is in direct contact with at least a portion of the upper surface of the flat layer located between the conductive traces and the light-emitting functional layer.

2. The display panel according to claim 1, characterized in that, The boundary of the light-emitting functional layer in the non-display area is located between the second trace and the display area.

3. The display panel according to claim 1, characterized in that, The surface roughness of at least a portion of the conductive traces on the side away from the substrate is greater than the surface roughness of the first electrode on the side away from the substrate.

4. The display panel according to claim 1, characterized in that, The thickness of the planarization layer located between the conductive trace and the pixel definition layer is less than the thickness of the planarization layer located in the display area.

5. The display panel according to claim 2, characterized in that, The pixel definition layer has a stepped structure on the side near the non-display area, and the boundary of the light-emitting functional layer in the non-display area is located between the stepped structure and the display area.

6. The display panel according to claim 5, characterized in that, The second conductive layer covers the stepped structure.

7. The display panel according to claim 1, characterized in that, The display panel also includes: A first dam is disposed on the side of the planarization layer away from the substrate, and at least a portion of the conductive traces are disposed between the first dam and the planarization layer; The second dam is disposed on the side of the planarization layer away from the substrate and on the side of the first dam away from the display area, wherein at least a portion of the conductive traces are disposed between the first dam and the planarization layer.

8. The display panel according to claim 7, characterized in that, The display panel also includes: An encapsulation layer is disposed on the side of the second conductive layer away from the substrate, and the encapsulation layer includes a first inorganic encapsulation sublayer, an organic encapsulation sublayer, and a second inorganic encapsulation sublayer stacked in sequence. The first inorganic encapsulation sublayer is in direct contact with the upper surface of the conductive trace between the first dam and the second dam.

9. A display device, characterized in that, The display panel includes any one of claims 1-8.

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