Electrostatic withstand voltage test apparatus and electrostatic withstand voltage test method

Abstract

On the mounting substrate (8), there are multiple terminals (9a-9c) and conductor patterns that are electrically connected to multiple pins of a semiconductor device, respectively. The electrostatic withstand voltage test apparatus (100) includes a metal plate (4) on which the mounting substrate (8) is mounted, a power supply (2) for applying voltage to the metal plate (4), an insulator (5) disposed between the metal plate (4) and the mounting substrate (8), a switch circuit (6) connecting the multiple terminals (9a-9d) and a grounding wire, and a control unit (7) for controlling the switch circuit (6). The switch circuit (6) includes multiple first switches (6a-6c), which are configured to correspond to the multiple terminals (9a-9c) respectively, and the corresponding terminals are connected to the grounding wire (24). When the charge accumulated in the conductor pattern is discharged to the grounding wire (24) through the semiconductor device, the control unit (7) turns on at least one of the multiple first switches (6a-6c).

Description

Technical Field

[0001] This disclosure relates to an electrostatic withstand voltage test apparatus and an electrostatic withstand voltage test method. Background Technology

[0002] With the miniaturization of semiconductor devices such as integrated circuits and discrete devices, the risk of failure due to electrostatic discharge (ESD) has increased. When using semiconductor devices, ESD management is required to determine the required withstand voltage for ESD and to prevent failures in conjunction with this withstand voltage. Therefore, ESD withstand voltage tests are performed on all semiconductor devices (see, for example, Japanese Patent Application Publication No. 2000-206177 (Patent Document 1)).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2000-206177 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] In previous electrostatic discharge (ESD) tests, an ESD was generated at one terminal of a semiconductor device. However, even with an ESD at one terminal, the semiconductor device sometimes does not fail due to voltage generated in the manufacturing environment.

[0008] In a structure where a connector is inserted into multiple pins on a substrate on which a semiconductor device is mounted, the terminals of the multiple pins simultaneously make electrical contact with multiple terminals of the semiconductor device. In this structure, electrostatic discharge (ESD) is generated in the semiconductor device via multiple pins. Therefore, compared to a structure that generates ESD via a single pin, a large current can flow into the semiconductor device in a short time. As a result, the possibility of semiconductor device failure increases. Consequently, in conventional ESD withstand voltage tests that generate ESD at a single terminal, it becomes impossible to accurately measure the withstand voltage of the semiconductor device at the manufacturing site.

[0009] This disclosure was made to address such problems, and its purpose is to provide an electrostatic withstand voltage test apparatus and an electrostatic withstand voltage test method that can accurately measure the electrostatic withstand voltage of semiconductor devices mounted on a substrate.

[0010] means for solving problems

[0011] In one aspect of this disclosure, an electrostatic discharge (ESD) withstand voltage test apparatus measures the ESD withstand voltage of a semiconductor device on a mounting substrate. The semiconductor device has multiple pins. Multiple terminals and conductor patterns, each electrically connected to one of the pins, are provided on the mounting substrate. The ESD withstand voltage test apparatus includes a metal plate mounting the mounting substrate, a power supply for applying voltage to the metal plate, an insulator disposed between the metal plate and the mounting substrate, a switching circuit connecting the multiple terminals to a grounding wire, and a control unit for controlling the switching circuit. The switching circuit includes multiple first switches configured to correspond to the multiple terminals, and connecting the corresponding terminals to the grounding wire. When discharging charge accumulated in the conductor patterns through the semiconductor device to the grounding wire, the control unit turns on at least one of the selected first switches.

[0012] In another aspect of this disclosure, the electrostatic discharge (ESD) withstand voltage test method is an ESD withstand voltage test method for determining the ESD withstand voltage of a semiconductor device on a mounting substrate. The semiconductor device has multiple pins. On the mounting substrate, multiple terminals and conductor patterns are provided, each electrically connected to one of the multiple pins. The ESD withstand voltage test method includes a step of inducing electrostatic discharge in the semiconductor device. The step of inducing electrostatic discharge in the semiconductor device includes the following steps: charging the conductor pattern by applying a voltage to a metal plate disposed opposite to the conductor pattern and separated by an insulator; and discharging the charge accumulated in the conductor pattern through the semiconductor device to a grounding wiring. The discharge step includes the following steps: turning on at least one of a plurality of first switches, the plurality of first switches being configured to correspond to the plurality of terminals respectively, and connecting the corresponding terminals to the grounding wiring.

[0013] The effects of the invention

[0014] According to this disclosure, an electrostatic withstand voltage test apparatus and an electrostatic withstand voltage test method are provided that can accurately measure the electrostatic withstand voltage of semiconductor devices in a manufacturing environment. Attached Figure Description

[0015] Figure 1 It is a top view of a magnified portion of a semiconductor device.

[0016] Figure 2 This is a cross-sectional view of a semiconductor device.

[0017] Figure 3 This is a diagram that schematically illustrates a structural example of the electrostatic withstand voltage test apparatus according to Embodiment 1.

[0018] Figure 4 It is shown Figure 3 The diagram shows the wiring structure of the semiconductor device, switching circuit, and power lines.

[0019] Figure 5It is a diagram used to illustrate the process of charging a conductor pattern.

[0020] Figure 6 This is a diagram used to illustrate the process of discharging charges onto a conductor pattern.

[0021] Figure 7 This diagram illustrates the process of removing static electricity from a metal plate.

[0022] Figure 8 This is a diagram illustrating an example of the structure of a measuring apparatus for measuring the electrical characteristics of a semiconductor device.

[0023] Figure 9 This is a flowchart illustrating the processing flow of the electrostatic withstand voltage test method in Embodiment 1.

[0024] Figure 10 This is a diagram that schematically illustrates a structural example of the electrostatic withstand voltage test apparatus of Embodiment 2.

[0025] Figure 11 This is a flowchart illustrating the processing flow of the electrostatic withstand voltage test method in Embodiment 2.

[0026] Figure 12 This is a diagram illustrating the process of measuring the electrical characteristics of semiconductor devices.

[0027] Figure 13 This is a diagram used to illustrate the process of generating electrostatic discharge. Detailed Implementation

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the same or equivalent parts in the drawings will be labeled with the same reference numerals, and their descriptions will generally not be repeated.

[0029] Implementation method 1.

[0030] (Example of a semiconductor device structure)

[0031] First, use Figure 1 and Figure 2 Hereinafter, an example of the structure of a semiconductor device that is the test object of the electrostatic withstand voltage test method of Embodiment 1 will be described. Figure 1 This is a top view of a portion of the semiconductor device 20 after being magnified. Figure 2 This is a cross-sectional view of the semiconductor device 20. Additionally, in Figure 2 The image shows a semiconductor device 20 installed in an electronic device.

[0032] like Figure 1 and Figure 2As shown, the semiconductor device 20 has a mounting substrate 8 and a semiconductor device 10. The mounting substrate 8 includes a conductor pattern 8a and an insulating layer 8b stacked on the conductor pattern 8a. The conductor pattern 8a occupies most of the area of ​​the mounting substrate 8 in top view and forms a GND pattern.

[0033] Semiconductor device 10 is mounted on the surface of mounting substrate 8. Semiconductor device 10 has at least one semiconductor element 10e, sealing resin 10f, and multiple pins. Semiconductor element 10e is, for example, composed of IGBT (Insulated Gate Bipolar Transistor), MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor), diode, etc.

[0034] Multiple pins are electrically connected to at least one semiconductor element 10e via conductive lines (not shown). A sealing resin 10f seals the at least one semiconductor element 10e and a portion of the multiple pins. Thus, a portion of the multiple pins is exposed from the sealing resin 10f. The multiple pins include pins 10a to 10c for power supply or signal input, and a GND pin 10d for ground voltage (GND) supply.

[0035] On the surface of the mounting substrate 8, power supply or signal input wiring 12a-12c, GND wiring 12d, and a plurality of terminals 9 are formed. The plurality of terminals 9 include power supply or signal input terminals 9a-9c and GND terminal 9d.

[0036] Wiring 12a-12c is electrically insulated from conductor pattern 8a. GND wiring 12d is electrically connected to conductor pattern 8a via GND terminal 9d disposed within insulating layer 8b. The first end of wiring 12a-12c is connected to pins 10a-10c of semiconductor device 10, respectively. The second end of wiring 12a-12c is connected to terminals 9a-9c, respectively. The first end of GND wiring 12d is connected to GND pin 10d of semiconductor device 10. The second end of GND wiring 12d is connected to GND terminal 9d.

[0037] In the manufacturing process of electronic devices, semiconductor devices 20 are housed inside a housing 13 formed of resin or the like. By inserting connectors 14 into the terminals 9a to 9c of semiconductor devices 20, terminals 9a to 9c are electrically connected to other devices 15 via connectors 14.

[0038] (Electrostatic discharge)

[0039] Next, the electrostatic discharge that can occur in the manufacturing environment of electronic devices will be explained in detail.

[0040] In the manufacturing process of electronic devices, the housing 13 housing the semiconductor device 20 is energized relative to GND, and the conductor pattern 8a (GND pattern) provided within the mounting substrate 8 is sometimes energized. Additionally, as... Figure 2 As shown, conductor pattern 8a is electrically connected to GND pin 10d of semiconductor device 10 via GND terminal 9d and GND wiring 12d.

[0041] In the manufacturing process, it is assumed that the pins 10a of the semiconductor device 10 are electrically connected to other devices 15 via connector 14 while the conductor pattern 8a is energized.

[0042] In this situation, the pin 10a of the semiconductor device 10 is electrically connected to the terminal 9a on the mounting substrate 8. Therefore, when the connector 14 is inserted into the terminal 9a, the charge accumulated in the conductor pattern 8a flows from the GND pin 10d through the semiconductor element 10e and the wiring inside the pin 10a, terminal 9a, connector 14, and device 15 into GND. That is, an electrostatic discharge corresponding to the amount of charge accumulated in the conductor pattern 8a is generated in the semiconductor device 20, and therefore, the semiconductor device 10 may malfunction.

[0043] Here, in the model assuming electrostatic discharge of the mounting substrate, there is a Charge Board Event (CBE). CBE refers to the model where the charge accumulated on the mounting substrate is discharged due to the insertion of a connector into a charged mounting substrate or contact between the mounting substrate and a metal tool. Typically, mounting substrates have an area several hundred times larger than semiconductor devices, and the amount of charge accumulated on the mounting substrate increases proportionally to this area.

[0044] In mounting substrates, conductive GND patterns occupying most of the substrate area are widely used to combat noise. The electrostatic capacitance C, representing the capacitance of charges stored in the semiconductor device and the mounting substrate respectively, is determined based on the formula C = ε(S / D), where ε is the relative permittivity, S is the area of ​​the counter electrode, and D is the distance between the counter electrodes. As mentioned above, the area S of the GND pattern is larger than that of the semiconductor device; therefore, the electrostatic capacitance C of the mounting substrate is larger than that of the semiconductor device.

[0045] The amount of charge Q stored in the semiconductor device and the mounting substrate is determined based on the relationship Q = CV, where V is the voltage applied between the counter electrodes. As mentioned above, the electrostatic capacitance C of the mounting substrate is larger than that of the semiconductor device. Therefore, when the applied voltages V are equal, the mounting substrate stores more charge than the semiconductor device.

[0046] The energy W of electrostatic discharge is determined based on the formula W = Q × V / 2. When the applied voltage V of the semiconductor device and the mounting substrate are equal, the amount of charge Q accumulated on the mounting substrate is greater than that on the semiconductor device; therefore, the energy W of the electrostatic discharge is also greater. Therefore, in... Figure 1 and Figure 2 In the semiconductor device 20 shown, although no faults caused by electrostatic discharge occur in the individual semiconductor device 10, faults caused by electrostatic discharge may occur in the semiconductor device 10 by mounting the semiconductor device 10 on the mounting substrate 8. Therefore, it is necessary to perform an electrostatic withstand voltage test according to CBE while the semiconductor device 10 is mounted on the mounting substrate 8 to measure the electrostatic withstand voltage of the semiconductor device 10 in the manufacturing process of the electronic device.

[0047] (Electrostatic withstand voltage test)

[0048] Next, the electrostatic withstand voltage test of Embodiment 1 will be described. First, using... Figure 3 An example of the structure of the electrostatic withstand voltage test apparatus of Embodiment 1 will be described.

[0049] (1) Example of the structure of an electrostatic withstand voltage test device

[0050] Figure 3 This is a diagram that schematically illustrates a structural example of the electrostatic withstand voltage test apparatus according to Embodiment 1.

[0051] like Figure 3 As shown, the electrostatic withstand voltage test apparatus 100 of Embodiment 1 is used to determine... Figure 1 and Figure 2 The device shown is an electrostatic withstand voltage test apparatus for the semiconductor device 20. The electrostatic withstand voltage test apparatus 100 includes a switch 1, a DC power supply 2, a resistor 3, a metal plate 4, an insulator 5, a switching circuit 6, a control unit 7, and power lines 21 to 24.

[0052] DC power supply 2 is connected between power line 21 on the high-voltage side and power line 22 on the low-voltage side. Power line 22 is composed of grounding wiring. DC power supply 2 is configured to switch the magnitude of the voltage output to power line 21.

[0053] Resistor 3 is connected between power line 21 and metal plate 4. Switch 1 is connected between power lines 21 and 23 and resistor 3. Switch 1 can be a semiconductor switch or a mechanical switch. Representative semiconductor switches include IGBTs or MOSFETs. Mechanical switches are, for example, relays or other switching devices. Switch 1 corresponds to one embodiment of the "second switch".

[0054] The switch 1 is configured to electrically connect the resistor 3 to either the power line 21 or the power line 23 according to a control signal from the control unit 7. As an example, the switch 1 has three contacts 1a to 1c. Contacts 1a and 1b are fixed contacts, and contact 1c is a movable contact that selectively connects to contacts 1a and 1b. Contact 1a is connected to the first terminal of power line 21, contact 1b is connected to the first terminal of power line 23, and contact 1c is connected to the first terminal of the resistor 3. The second terminal of power line 21 is connected to the positive terminal of the DC power supply 2, the second terminal of power line 23 is connected to power line 22, and the second terminal of the resistor 3 is connected to the metal plate 4.

[0055] By connecting contact 1c of switch 1 to contact 1a, the power line 21 is electrically connected to the resistor 3. Therefore, the voltage supplied from the DC power source 2 to the power line 21 can be applied to the metal plate 4 via the resistor 3. On the other hand, by connecting contact 1c of switch 1 to contact 1b, the power line 23 is electrically connected to the resistor 3. Therefore, the charge accumulated in the metal plate 4 can be released towards the power line 22 via the power line 23.

[0056] In the following description, connecting contact 1c to contact 1a is referred to as "closing (conducting) contact 1a", and connecting contact 1c to contact 1b is referred to as "closing contact 1b". Furthermore, in switch 1, when contact 1a is closed, contact 1b is open (non-conducting), and when contact 1b is closed, contact 1a is open.

[0057] The insulator 5 has a flat plate shape and is disposed on the metal plate 4. The semiconductor device 20 is disposed on the insulator 5. The insulator 5 ensures electrical insulation between the metal plate 4 and the conductor pattern 8a. By providing the insulator 5 between the metal plate 4 and the conductor pattern 8a, a capacitor with the metal plate 4 and the conductor pattern 8a as electrodes can be simulated. Therefore, when a voltage is applied to the metal plate 4, charge can be stored in the metal plate 4. In addition, the specifications of the insulator 5 need to be determined according to the test voltage. This is because if an insulator 5 with an insulation withstand voltage lower than the test voltage is used, the insulation of the insulator 5 may be damaged during voltage application.

[0058] A switching circuit 6 is connected between terminal 9 of semiconductor device 20 and power line 24. Power line 24 is formed by grounding wiring. The switching circuit 6 has a plurality of switches 6a to 6c. The plurality of switches 6a to 6c correspond to an embodiment of "a plurality of first switches".

[0059] For switches 6a to 6c, mercury relays can be used, for example. The contacts of a mercury relay are covered with mercury. In other mechanical relays, a momentary switching action occurs when the switch is opened. Because mercury has high viscosity, this switching action does not occur in mercury relays. Therefore, highly reproducible electrostatic withstand voltage tests can be performed.

[0060] Switches 6a to 6c are used to reproduce the Figure 2 The electrostatic discharge that occurs when the pins 10a to 10c of the semiconductor device 10 are electrically connected to other devices 15 via connector 14. Specifically, switch 6a is connected between terminal 9a and power line 24. Switch 6b is connected between terminal 9b and power line 24. Switch 6c is connected between terminal 9c and power line 24. Switches 6a to 6c are configured to connect / disconnect the corresponding terminal 9 and power line 24 by turning on (conducting) or off (not conducting) according to a control signal from control unit 7.

[0061] By turning on switches 6a to 6c, the scene was reproduced. Figure 2 The pins 10a to 10c of the semiconductor device 10 shown are electrically connected to the connector 14, thus enabling the simulation of the electrostatic discharge based on CBE (substrate charge event) described above. Furthermore, in Figure 3 In the example, the number of switches included in the switching circuit 6 is set to 3, but the number of switches can be multiple.

[0062] The control unit 7 controls the connection and disconnection of the switch 1 and the switch circuit 6. The control unit 7 can be configured, for example, as a microcomputer. Specifically, the control unit 7 includes a CPU (Central Processing Unit) 71 and a memory 72 for storing programs and data. Through software processing implemented by the CPU 71 executing the program, the control actions described later can be performed. Alternatively, some or all of the control actions can be implemented using hardware processing, such as built-in dedicated electronic circuits, instead of software processing.

[0063] The memory 72 includes ROM (Read Only Memory) and RAM (Random Access Memory). ROM can store programs executed by CPU 71. RAM can temporarily store data used by CPU 71 during program execution and can function as temporary data storage used as a working area.

[0064] The control unit 7 can independently control the switching on and off of the plurality of switches 6a to 6c included in the switching circuit 6. Therefore, the control unit 7 can turn on any one of the plurality of switches 6a to 6c. Alternatively, the control unit 7 can turn on two or more switches simultaneously. That is, the control unit 7 can turn on at least one of the plurality of switches 6a to 6c.

[0065] Figure 4 It is shown Figure 3 The diagram shows the wiring structure of the semiconductor device 20, the switching circuit 6, and the power line 24. Figure 4 As shown, the electrostatic withstand voltage test apparatus 100 also has multiple probes 11a to 11c. Hereinafter, probes 11a to 11c will sometimes be referred to simply as "probe 11".

[0066] For probe 11, a spring probe can be used, for example. The spring probe has a movable part with a built-in spring, which slides via the spring when pressure is applied to the front end. This sliding ensures contact between probe 11 and terminal 9.

[0067] The first terminals of multiple probes 11a-11c are respectively connected to the first terminals of multiple switches 6a-6c. The second terminals of multiple switches 6a-6c are connected to the power line 24. The second terminals of multiple probes 11a-11c are respectively connected to multiple terminals 9a-9c of the semiconductor device 20. Additionally, in Figure 4 In this example, the number of probes 11 is set to 3, but the number of probes 11 is the same as the number of switches in the switching circuit 6.

[0068] (2) Electrostatic withstand voltage test method

[0069] Next, the electrostatic withstand voltage test method of Embodiment 1 will be described.

[0070] The electrostatic withstand voltage test method of Implementation Method 1 is configured to, by means of... Figure 3 The electrostatic withstand voltage test apparatus 100 shown controls the switching on and off of switch 1 and switch circuit 6 to perform the charging of conductor pattern 8a on the mounting substrate 8 and the discharge of charge accumulated in conductor pattern 8a. This achieves an electrostatic withstand voltage test simulating electrostatic discharge based on CBE (substrate charging event).

[0071] (2-1) Process of charging conductor pattern 8a

[0072] In the electrostatic withstand voltage test method of Embodiment 1, in order to generate electrostatic discharge based on CBE, a process is first performed to charge the conductor pattern 8a of the mounting substrate 8. Figure 5 This is a diagram used to illustrate the process of charging conductor pattern 8a.

[0073] In this process, firstly, Figure 3 The electrostatic discharge withstand voltage test apparatus 100 shown is set to its initial state. In the initial state, contact 1b of switch 1 is turned on (i.e., contact 1a is turned off), and switches 6a to 6c of switch circuit 6 are turned off. Next, a semiconductor device 20 is set as the test object for the electrostatic discharge withstand voltage test apparatus 100 in the initial state. That is, a mounting substrate 8 is provided on the insulator 5.

[0074] Next, probes 11a to 11c are operated by using a drive unit (not shown), such as... Figure 5 As shown, probes 11a to 11c are respectively brought into contact with terminals 9a to 9c of semiconductor device 20. Through the contact of probes 11a to 11c, terminals 9a to 9c are electrically connected to the first terminals of switches 6a to 6c. However, switches 6a to 6c are all in the open state, therefore, terminals 9a to 9c are electrically disconnected from the power line 24 (i.e., GND).

[0075] Next, as Figure 5 As shown, contact 1a of switch 1 is set to closed (i.e., contact 1b is opened). When contact 1a is closed, as indicated by the arrow in the figure, the voltage supplied from DC power supply 2 to power line 21 is applied to metal plate 4 via switch 1 and resistor 3. As a result, positive charge accumulates in metal plate 4. Furthermore, although in Figure 5 In the example, the metal plate 4 accumulates positive charge, but by using a structure that accumulates negative charge, the experiment was able to reproduce the state of the mounting substrate 8 being negatively charged.

[0076] Additionally, resistor 3 is provided to limit the inrush current when voltage is applied to metal plate 4. Resistor 3 has a resistance value of several MΩ. By providing resistor 3, the current capacitance of DC power supply 2 can be reduced, resulting in the miniaturization of DC power supply 2.

[0077] The conductor pattern 8a, positioned opposite the metal plate 4 and separated by the insulator 5, is electrically neutral in the initial state of the electrostatic withstand voltage test apparatus 100; therefore, positive and negative charges exist in equal amounts. When the contact 1a is closed and a voltage is applied to the metal plate 4, there is no path for charge to flow out in the conductor pattern 8a; therefore, as... Figure 5 As shown, polarization occurs. Furthermore, although polarization occurs, the positive and negative charges present in conductor pattern 8a remain equal. Through polarization, the charge 12 in conductor pattern 8a generates electric field lines relative to GND; therefore, conductor pattern 8a has a potential relative to GND.

[0078] (2-2) The process of discharging the charge on conductor pattern 8a

[0079] Next, a process is performed to discharge the charge accumulated in the conductor pattern 8a. In this process, the charge 12 accumulated in the conductor pattern 8a is discharged to GND via the semiconductor device 10, thereby reproducing the electrostatic discharge based on CBE. Figure 6 This is a diagram illustrating the process of discharging charge 12 on conductor pattern 8a.

[0080] In this process, while keeping contact 1a of switch 1 in the closed state, at least one of switches 6a to 6c of switch circuit 6 is turned on. Figure 6 In this example, switches 6a to 6c are simultaneously turned on. By turning on switch 6a, pin 10a of semiconductor device 10 is electrically connected to GND via terminal 9a, probe 11a, switch 6a, and power line 24. Pins 10b and 10c of semiconductor device 10 are also electrically connected to GND by turning on switches 6b and 6c.

[0081] The semiconductor device 10 is simultaneously electrically connected to GND via multiple pins 10a to 10c, such as... Figure 6 As indicated by the arrows, an electrical path is formed between the conductor pattern 8a and GND via the semiconductor device 10. This electrical path branches into multiple electrical paths within the range from pins 10a to 10c to GND. The charge 12 accumulated in the conductor pattern 8a flows into the semiconductor device 10 and then into GND through these multiple electrical paths.

[0082] When two or more of the switches 6a to 6c constituting the switching circuit 6 are simultaneously turned on, multiple electrical paths are formed between the pin of the semiconductor device 10 and GND. Therefore, compared to the case where only a single switch is turned on, the overall impedance of the discharge path of the charge 12 of the conductor pattern 8a decreases. Then, due to this decrease in impedance, the current flowing in the discharge path increases. However, since the entire current flows through the GND pin 10d of the semiconductor device 10 in a single terminal, the current exceeds the allowable value and increases, potentially causing electrostatic discharge (ESD) damage.

[0083] Furthermore, the overall impedance of the discharge path can be changed by adjusting the number of switches switched on in switching circuit 6. The overall impedance of the discharge path decreases as the number of switches switched on increases. As a result, the current flowing in the discharge path increases. Figure 2 As shown, in the manufacturing process, the contact pattern of each terminal 9 changes each time the connector 14 is inserted into multiple terminals 9. Therefore, it is necessary to measure the electrostatic withstand voltage when the contact pattern with the terminal 9 changes.

[0084] According to the electrostatic discharge withstand voltage test apparatus 100 of Embodiment 1, the path of electrostatic discharge is controlled by the switching circuit 6, thus enabling electrostatic discharge to be generated at a selected terminal 9 among the multiple terminals 9a to 9c. That is, since the switches 6a to 6c are connected to the pins 10a to 10c of the semiconductor device 10 in a one-to-one correspondence, electrostatic discharge can be generated using only the selected terminal 9. In this way, the electrostatic discharge withstand voltage can be measured by assuming the change in the contact pattern of each terminal 9 when the connector 14 is inserted into the multiple terminals 9a to 9c.

[0085] Furthermore, when performing an electrostatic withstand voltage test using, for example, a connector 14 without using the switching circuit 6, it can be affected by various factors such as the surrounding environment (humidity, etc.), the speed and angle at which the connector 14 is inserted, and contamination of the connector 14. Therefore, even when performing an electrostatic withstand voltage test under the same test conditions, reproducible test results may not be obtained. On the other hand, the electrostatic withstand voltage test apparatus 100 of Embodiment 1 uses the switching circuit 6 in the formation of the discharge path, thus suppressing the aforementioned influences of the surrounding environment, and as a result, can perform electrostatic withstand voltage tests with high reproducibility.

[0086] (2-3) The process of removing static electricity from metal plate 4

[0087] At the end of the electrostatic discharge, a process is performed to remove static electricity from metal plate 4. Figure 7 This diagram illustrates the process of removing static electricity from metal plate 4.

[0088] In this process, such as Figure 7 As shown, by turning off all switches 6a to 6c of the switching circuit 6, the pins 10a to 10c of the semiconductor device 10 are electrically disconnected from GND. Then, the contact 1b of the switch 1 is turned on (i.e., the contact 1a is turned off).

[0089] When contact 1b is turned on, metal plate 4 is electrically connected to GND via resistor 3, electric field line 23, and electric field line 22. The charge accumulated in metal plate 4 flows into GND via resistor 3, electric field line 23, and electric field line 22. After de-energizing metal plate 4, probes 11a-11c are activated, releasing them from contact with terminals 9a-9c. Thus, the electrostatic withstand voltage test apparatus 100 returns to its initial state.

[0090] (Methods for troubleshooting semiconductor devices)

[0091] Next, the method for determining the fault of semiconductor device 10 in the electrostatic withstand voltage test of Embodiment 1 will be described.

[0092] The fault determination of semiconductor device 10 is based on the results of electrical measurements of semiconductor device 10 performed before and after electrostatic discharge. Figure 8 This is a diagram showing an example of the structure of a measuring apparatus for measuring the electrical characteristics of a semiconductor device 10.

[0093] like Figure 8 As shown, the measuring apparatus 110 for measuring the electrical characteristics of the semiconductor device 10 includes a measuring unit 16, a calculating unit 17, and a plurality of probes 11a to 11d. For example, a spring probe can be used for the probes 11.

[0094] The first terminals of the plurality of probes 11a to 11d are connected to the measuring device 16. The second terminals of the plurality of probes 11a to 11c are respectively connected to the plurality of terminals 9a to 9c of the semiconductor device 20. The second terminal of the plurality of probes 11d is connected to the GND terminal 9d of the semiconductor device 20. Additionally, in Figure 8 In the example, the number of probes 11 is set to 4, but the number of probes 11 can be multiple.

[0095] The measuring device 16 is a part used to measure the electrical characteristics of the semiconductor device 10, such as a curve plotter including a voltage source or a current source. The measuring device 16 is configured to measure the voltage between the terminals of the semiconductor device 10 and the current flowing to the semiconductor device 10.

[0096] The probes 11a to 11d are operated by using a drive unit (not shown), such as... Figure 8 As shown, probes 11a to 11d are brought into contact with terminals 9a to 9d of semiconductor device 20, respectively. By bringing probes 11a to 11d into contact, the measuring device 16 is electrically connected to pins 10a to 10d of semiconductor device 10 via probes 11a to 11d and terminals 9a to 9d.

[0097] The arithmetic unit 17 is connected to the measuring unit 16 and receives the measured values ​​of the voltage and current between the terminals of the semiconductor device 10 from the measuring unit 16. Based on the measured values, the arithmetic unit 17 determines whether the semiconductor device 10 has malfunctioned.

[0098] Specifically, before and after the electrostatic discharge (ESD) test, the electrical characteristics of the semiconductor device 10 are measured using the measuring instrument 16, and the measured values ​​of the electrical characteristics before and after the test are compared in the arithmetic unit 17. When the semiconductor device 10 malfunctions due to ESD, its resistance changes. For example, in the case of an open-circuit fault, the resistance of the semiconductor device 10 increases, and no current flows even when voltage is applied. On the other hand, in the case of a short-circuit fault, the resistance of the semiconductor device 10 decreases, and current flows immediately when voltage is applied. Therefore, if the change in the measured values ​​of the electrical characteristics of the semiconductor device 10 is confirmed before and after the ESD withstand voltage test, it can be determined that the semiconductor device 10 has malfunctioned.

[0099] (Electrostatic withstand voltage test procedure)

[0100] Figure 9 This is a flowchart illustrating the processing flow of the electrostatic withstand voltage test method in Embodiment 1.

[0101] like Figure 9 As shown, the electrostatic withstand voltage test method of Embodiment 1 includes: a step of measuring the electrical characteristics of the semiconductor device 10 before electrostatic discharge occurs; a step of generating electrostatic discharge; and a step of measuring the electrical characteristics of the semiconductor device 10 after electrostatic discharge occurs.

[0102] In the process of measuring the electrical characteristics of the semiconductor device 10 before electrostatic discharge occurs, using Figure 8 The measuring device 110 shown measures the electrical characteristics (first electrical characteristics) of the semiconductor device 10.

[0103] Specifically, firstly, in step S01, the measuring device 16 is connected to terminals 9a to 9d of the semiconductor device 20. In step S01, probes 11a to 11d are brought into contact with terminals 9a to 9d respectively.

[0104] Next, in step S02, the electrical characteristics of the semiconductor device 10 are measured. In step S02, at least one of the switches 6a to 6c and switch 6d of the switching circuit 6 are turned on, and voltage and / or current are applied to the semiconductor device 10 from the measuring device 16. The measured values ​​of the electrical characteristics of the semiconductor device 10, as measured by the measuring device 16, are sent to the arithmetic unit 17. The arithmetic unit 17 stores the measured values ​​of the electrical characteristics of the semiconductor device 10 as initial characteristics in the storage unit.

[0105] After the measurement of the electrical characteristics of the semiconductor device 10 is completed, in step S03, the probes 11a to 11d are activated to release the contact with terminals 9a to 9d, thereby removing the measuring device 16 from terminals 9a to 9d.

[0106] Next, in the process of generating electrostatic discharge, using Figure 3 The electrostatic withstand voltage test apparatus 100 shown causes the semiconductor device 10 to generate electrostatic discharge based on CBE (substrate charge event).

[0107] Specifically, firstly, in step S04, the semiconductor device 20, which is set to be tested, is placed on the electrostatic withstand voltage test apparatus 100 in its initial state. In step S04, a mounting substrate 8 is placed on the insulator 5. Furthermore, since the electrostatic withstand voltage test apparatus 100 is in its initial state, the contact 1b of the switch 1 is turned on.

[0108] Next, through step S05, probes 11a to 11c are activated, thereby, as Figure 5 As shown, probes 11a-11c are brought into contact with terminals 9a-9c of semiconductor device 20, respectively. This connects terminals 9a-9c to switches 6a-6c of switching circuit 6. However, since switches 6a-6c are all in the off state, terminals 9a-9c are electrically disconnected from power line 24 (i.e., GND).

[0109] Next, in step S06, the voltage supplied from the DC power supply 2 to the power line 21 is set. This voltage becomes the voltage applied to the metal plate 4.

[0110] When the applied voltage from DC power supply 2 is set, contact 1a of switch 1 is closed (i.e., contact 1b is opened) via step S07. When contact 1a is closed, the voltage supplied from DC power supply 2 to power line 21 is applied to metal plate 4 via switch 1 and resistor 3. As a result, as Figure 5 As shown, positive charges are accumulated in the metal plate 4, and the conductor pattern 8a is charged.

[0111] Next, proceeding to step S08, while keeping contact 1a of switch 1 in the closed state, at least one of the switches 6a to 6c of the switch circuit 6 is turned on. At this time, by simultaneously turning on two or more switches, two or more pins 10a to 10c of the semiconductor device 10 are simultaneously electrically connected to GND, thus forming multiple electrical paths through the semiconductor device 10 between the conductor pattern 8a and GND. When the charge 12 accumulated in the conductor pattern 8a flows into the semiconductor device 10, it flows into GND through these multiple electrical paths.

[0112] Next, in step S09, all switches 6a to 6c of the switching circuit 6 are turned off, thereby disconnecting pins 10a to 10c of the semiconductor device 10 from GND. Furthermore, contact 1b of switch 1 is turned on (i.e., contact 1a is turned off). With contact 1b turned on, the charge accumulated in the metal plate 4 flows into GND via resistor 3, electric field line 23, and electric field line 22.

[0113] After de-energizing the metal plate 4, in step S10, the probes 11a to 11c are activated to release the contact with terminals 9a to 9c, thereby removing the switching circuit 6 from terminals 9a to 9c.

[0114] Next, in the process of measuring the electrical characteristics of the semiconductor device 10 after electrostatic discharge, the following steps are performed: Figure 8 The measuring device 110 shown is used to measure the electrical characteristics (second electrical characteristics) of the semiconductor device 10.

[0115] Specifically, firstly, in step S11, the measuring device 16 is connected to terminals 9a to 9d of the semiconductor device 20. Secondly, in step S11, probes 11a to 11d are brought into contact with terminals 9a to 9d respectively.

[0116] Next, the electrical characteristics of the semiconductor device 10 are measured in step S12. The process of step S12 is the same as that of step S02. That is, at least one of the switches 6a to 6c of the switching circuit 6 and switch 6d are turned on, and voltage and / or current are applied to the semiconductor device 10 from the measuring device 16.

[0117] After obtaining the measured values ​​of the electrical characteristics of the semiconductor device 10 from the measuring unit 16, the arithmetic unit 17 enters step S13, compares the measured values ​​of the electrical characteristics (second electrical characteristics) obtained in step S12 with the initial characteristics (first electrical characteristics) obtained in step S02, and thereby determines whether the semiconductor device 10 has malfunctioned.

[0118] If the semiconductor device 10 is determined to have malfunctioned (if the determination in S13 is yes), the electrostatic discharge (ESD) withstand voltage test ends. Conversely, if the semiconductor device 10 is determined not to have malfunctioned (i.e., is functioning normally) (if the determination in S13 is no), the process proceeds to step S14, where the arithmetic unit 17 determines whether the applied voltage from the DC power supply 2 can be further increased. In step S14, if the current applied voltage reaches the upper limit of the voltage range that the DC power supply 2 can output, it is determined that the applied voltage cannot be increased. If the applied voltage cannot be increased (if the determination in S14 is no), the ESD withstand voltage test ends.

[0119] On the other hand, if the current applied voltage does not reach the upper limit (when S14 determines yes), the arithmetic unit 17 determines that the applied voltage can be increased, returns to step S04, and executes the electrostatic discharge generation process again. In this process, the applied voltage is changed to a higher voltage value than the current voltage value through step S06. Then, by executing the processes of steps S07 to S10, electrostatic discharge is generated in the semiconductor device 10. Next, by executing the processes of steps S11 to S14, the electrical characteristics of the semiconductor device 10 are measured, and the presence or absence of a fault in the semiconductor device 10 is determined based on the comparison between the measured value and the initial characteristics.

[0120] As explained above, according to the electrostatic withstand voltage test apparatus and method of Embodiment 1, electrostatic discharge can be generated simultaneously in multiple terminals 9 of the mounting substrate 8 provided on the semiconductor device 20. Therefore, it is possible to measure the electrostatic withstand voltage in a process where electrostatic discharge is generated due to simultaneous contact between metal and multiple terminals 9 as when a connector is inserted into multiple terminals 9. In this way, the electrostatic withstand voltage of the semiconductor device 10 on the mounting substrate 8 can be accurately measured.

[0121] Furthermore, according to the electrostatic withstand voltage test apparatus and method of Embodiment 1, the electrostatic discharge generation path is controlled by the switching circuit 6, thus enabling electrostatic discharge to be generated in the terminal 9 selected from the plurality of terminals 9. In this way, the electrostatic withstand voltage can be measured by assuming the change in the contact pattern of each terminal 9 when the connector is inserted into the plurality of terminals 9.

[0122] Furthermore, electrostatic discharge is generated by switching multiple switches 6a to 6c in the switching circuit 6, thus suppressing the influence of the surrounding environment and achieving highly reproducible electrostatic withstand voltage tests.

[0123] Implementation method 2.

[0124] In Embodiment 1 described above, a separate structure for the electrostatic withstand voltage testing apparatus 100 and the measuring device 110 was presented. However, a structure integrating the electrostatic withstand voltage testing apparatus and the measuring device is also possible. In this structure, a switch can be used to selectively drive the electrostatic withstand voltage testing apparatus and the measuring device.

[0125] (Structural example of an electrostatic withstand voltage test apparatus)

[0126] Figure 10 This is a diagram that schematically illustrates a structural example of the electrostatic withstand voltage test apparatus of Embodiment 2.

[0127] like Figure 10 As shown, the electrostatic withstand voltage test apparatus 100A of Embodiment 2 is for... Figure 3 The electrostatic withstand voltage test apparatus 100 of Embodiment 1 shown is obtained by adding a measuring device 16, a calculating unit 17, and a switch 18, and by replacing the switch circuit 6 and the control unit 7 with a switch circuit 6A and a control unit 7A, respectively. In the electrostatic withstand voltage test apparatus 100A, the measuring device 16 and the calculating unit 17 are... Figure 8 The measuring device 16 and the arithmetic unit 17 in the measuring device 110 shown are the same, so the description is omitted.

[0128] Switch 18 is connected between power lines 25, 26 and power line 24. A semiconductor switch or a mechanical switch can be used for switch 18. Switch 18 corresponds to one embodiment of the "third switch".

[0129] Switch 18 is configured to electrically connect power line 25 to either power line 24 or power line 26 according to a control signal from control unit 7A. As an example, switch 18 has three contacts 18a to 18c. Contacts 18a and 18b are fixed contacts, and contact 18c is a movable contact that selectively connects to contacts 18a and 18b. Contact 18a is connected to the first terminal of power line 25, contact 18b is connected to the first terminal of power line 24, and contact 18b is connected to the first terminal of power line 26. The second terminal of power line 25 is connected to the first terminal of switches 6a to 6c in switch circuit 6A. The second terminal of power line 26 is connected to the measuring device 16.

[0130] Switching circuit 6A is connected between terminal 9 of semiconductor device 20 and power line 25 and measuring device 16. Switching circuit 6A is for... Figure 3 The switch circuit 6 shown is obtained by adding a switch 6d. The switch 6d is connected between the GND terminal 9d and the measuring device 16. A semiconductor switch or a mechanical switch can be used for the switch 6d. The switch 6d is configured to be turned on / off according to the control signal from the control unit 7A, thereby electrically connecting / disconnecting the GND terminal 9d and the measuring device 16.

[0131] By connecting contact 18c of switch 18 to contact 18a, power line 25 and power line 24 are electrically connected, thus forming... Figure 3 The electrostatic withstand voltage test apparatus 100 is shown. On the other hand, by connecting contacts 18c and 18b of switch 18, power lines 25 and 26 are electrically connected. Therefore, terminals 9a to 9c of semiconductor device 20 are connected to the tester 16 via switches 6a to 6c. Thus, a [structure / system] can be formed. Figure 8 The measuring device 110 shown. That is, the electrostatic withstand voltage test device 100A is configured to switch between the electrostatic withstand voltage test device 100 and the measuring device 110.

[0132] In the following description, connecting contact 18c to contact 18a is referred to as "closing contact 18a", and connecting contact 18c to contact 18b is referred to as "closing contact 18b". Furthermore, in switch 18, when contact 18a is closed, contact 18b is open, and when contact 18b is closed, contact 18a is closed.

[0133] The control unit 7A controls the opening and closing of switches 1 and 18 and the switch circuit 6A. The control unit 7A can be configured, for example, as a microcomputer. Specifically, the control unit 7A includes a CPU 71 and a memory 72 for storing programs and data. The control actions described later can be executed through software processing based on the program executed by the CPU 71. Alternatively, some or all of the control actions can be implemented using hardware processing, such as built-in dedicated electronic circuits, instead of software processing.

[0134] Like control unit 7, control unit 7A can independently control the switching on and off of the plurality of switches 6a to 6c included in switch circuit 6. Therefore, control unit 7A can turn on at least one of the plurality of switches 6a to 6c.

[0135] (Electrostatic withstand voltage test method)

[0136] Next, use Figures 11 to 13 The electrostatic withstand voltage test method of Embodiment 2 will be described. Figure 11 This is a flowchart illustrating the processing flow of the electrostatic withstand voltage test method in Embodiment 2. Figure 11 Flowcharts and Figure 9 Compared to the flowchart shown, the control of switch 18 and switch circuit 6A is different.

[0137] like Figure 11 As shown, the electrostatic withstand voltage test method of Embodiment 2 includes: a step of measuring the electrical characteristics of the semiconductor device 10 before electrostatic discharge occurs; a step of generating electrostatic discharge; and a step of measuring the electrical characteristics of the semiconductor device 10 after electrostatic discharge occurs.

[0138] In the process of measuring the electrical characteristics of the semiconductor device 10 before electrostatic discharge occurs, using Figure 10 The measuring device 16 and the arithmetic unit 17 shown are used to measure the electrical characteristics (first electrical characteristics) of the semiconductor device 10. Figure 12 This is a diagram illustrating the process of measuring the electrical characteristics of semiconductor device 10.

[0139] Specifically, firstly, through step S21, the semiconductor device 20, which is set to the electrostatic withstand voltage test device 100A in its initial state, is set to be the test object. In the initial state, the contact 1b of switch 1 is set to be closed (that is, the contact 1a is opened).

[0140] Next, in step S22, the probes (not shown) are brought into contact with terminals 9a to 9d of the semiconductor device 20, thereby electrically connecting terminals 9a to 9d to switches 6a to 6d of the switching circuit 6A. However, since switches 6a to 6d are all in the off state, terminals 9a to 9c are electrically disconnected from the power line 25, and the GND terminal 9d is electrically disconnected from the measuring device 16.

[0141] In step S23, contact 18b of switch 18 is turned on (i.e., contact 18a is turned off). Next, in step S24, the electrical characteristics of semiconductor device 10 are measured. In step S24, at least one of switches 6a to 6c and switch 6d of switch circuit 6A are turned on, and voltage and / or current are applied to semiconductor device 10 from measuring device 16. The measured values ​​of the electrical characteristics of semiconductor device 10, as measured by measuring device 16, are sent to arithmetic unit 17. Arithmetic unit 17 stores the measured values ​​of the electrical characteristics of semiconductor device 10 as initial characteristics in the storage unit.

[0142] When the measurement of the electrical characteristics of the semiconductor device 10 is completed, in step S25, all switches 6a to 6d of the switching circuit 6A are set to open.

[0143] Next, in the process of generating electrostatic discharge, the semiconductor device 10 is made to generate electrostatic discharge based on CBE (substrate charge event). Figure 13 This is a diagram used to illustrate the process of generating electrostatic discharge.

[0144] Specifically, firstly, in step S26, contact 18a of switch 18 is set to closed (i.e., contact 18b is opened). Meanwhile, contact 1b of switch 1 remains closed.

[0145] Next, in step S27, the voltage supplied from the DC power supply 2 to the power line 21 is set. This voltage becomes the voltage applied to the metal plate 4. When the applied voltage from the DC power supply 2 is set, in step S28, contact 1a of switch 1 is turned on (i.e., contact 1b is turned off). When contact 1a is turned on, the voltage supplied from the DC power supply 2 to the power line 21 is applied to the metal plate 4 via switch 1 and resistor 3.

[0146] Next, proceeding to step S29, while keeping contact 1a of switch 1 in the closed state, at least one of switches 6a to 6c in switch circuit 6A is turned on. Meanwhile, switch 6d remains open. Figure 13In this example, switches 6a to 6c are simultaneously turned on. In step S29, by simultaneously turning on two or more of the multiple switches 6a to 6c, two or more of the pins 10a to 10c of the semiconductor device 10 are simultaneously electrically connected to GND, thus forming multiple electrical paths through the semiconductor device 10 between the conductor pattern 8a and GND. When the charge 12 accumulated in the conductor pattern 8a flows into the semiconductor device 10, it flows into GND through these multiple electrical paths.

[0147] Next, in step S30, all switches 6a to 6c of the switching circuit 6A are turned off, thereby disconnecting the pins 10a to 10c of the semiconductor device 10 from GND. Furthermore, contact 1b of switch 1 is turned on (i.e., contact 1a is turned off). With contact 1b turned on, the charge accumulated in the metal plate 4 flows into GND via resistor 3, electric field line 23, and electric field line 22.

[0148] Next, in the process of measuring the electrical characteristics of the semiconductor device 10 after electrostatic discharge, the following steps are performed: Figure 10 The measuring device 16 and the arithmetic unit 17 shown are used to measure the electrical characteristics (second electrical characteristics) of the semiconductor device 10.

[0149] Specifically, firstly, through step S31, contact 18b of switch 18 is set to ON (i.e., contact 18a is opened), and contact 1b of switch 1 is set to ON (i.e., contact 1a is opened). In addition, all switches 6a to 6d of switch circuit 6A are OFF.

[0150] Next, in step S32, the electrical characteristics (second electrical characteristics) of the semiconductor device 10 are measured. The process of step S32 is the same as that of step S24. That is, at least one of the switches 6a to 6c of the switching circuit 6A and switch 6d are turned on, and voltage and / or current are applied to the semiconductor device 10 from the measuring device 16.

[0151] When the arithmetic unit 17 obtains the measured value of the electrical characteristics of the semiconductor device 10 from the measuring unit 16, it enters step S33 and compares the measured value of the electrical characteristics (second electrical characteristics) obtained in step S32 with the initial characteristics (first electrical characteristics) obtained in step S24, thereby determining whether the semiconductor device 10 has malfunctioned.

[0152] If the semiconductor device 10 is determined to have malfunctioned (if S33 is true), the electrostatic discharge (ESD) withstand voltage test ends. Conversely, if the semiconductor device 10 is determined not to have malfunctioned (if S33 is false), the process proceeds to step S34, where the arithmetic unit 17 determines whether the applied voltage from the DC power supply 2 can be further increased. If the applied voltage cannot be increased (if S34 is false), the ESD withstand voltage test ends.

[0153] On the other hand, if the applied voltage can be increased (if the determination in S34 is yes), the process returns to step S26 and executes the electrostatic discharge generation process again. In this process, the applied voltage is changed to a higher voltage value than the current voltage value in step S27. Then, by executing the processes in steps S28 to S30, electrostatic discharge is generated in the semiconductor device 10. Next, by executing the processes in steps S31 to S34, the electrical characteristics of the semiconductor device 10 are measured, and the presence or absence of a fault in the semiconductor device 10 is determined based on a comparison of the measured values ​​with the initial characteristics.

[0154] As explained above, in the electrostatic withstand voltage test apparatus and electrostatic withstand voltage test method of Embodiment 2, electrostatic discharge can also be generated simultaneously in multiple terminals 9 of the mounting substrate 8 provided on the semiconductor device 20 by controlling the switches 6a to 6c of the switching circuit 6A. Therefore, the same effect as that of the electrostatic withstand voltage test apparatus and electrostatic withstand voltage test method of Embodiment 1 can be obtained.

[0155] Furthermore, regarding the above-described embodiments and modifications, from the outset of the application, it is planned to include combinations not mentioned in the specification, and to appropriately combine the structures described in the embodiments to the extent that no adverse effects or contradictions will occur.

[0156] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of this disclosure is set forth in the claims, not in the foregoing description, and includes all modifications within the same meaning and scope as the claims.

[0157] Explanation of reference numerals in the attached figures

[0158] 1. Switches 6a-6d and 18, contacts 1a-1c and 18a-18c, 2. DC power supply, 3. Resistor, 4. Metal plate, 5. Insulator, 6. 6A switch circuit, 7. 7A control unit, 8. Mounting substrate, 8a conductor pattern, 8b insulating layer, 9. 9a-9d terminals, 10. Semiconductor device, 10a-10d pins, 10e semiconductor element, 10f sealing resin, 11. 11a-11d probes, 12 charge, 12a-12c wiring, 13. Housing, 14. Connector, 15. Equipment, 16. Measuring device, 17. Arithmetic unit, 20. Semiconductor device, 21-26. Power line, 71. CPU, 72. Memory, 100A electrostatic withstand voltage test device, 110 measuring device.

Claims

1. An electrostatic withstand voltage test device for measuring an electrostatic withstand voltage of a semiconductor device mounted on a mounting substrate, wherein the semiconductor device has a plurality of pins, a plurality of terminals and a conductor pattern are provided on the mounting substrate so as to be electrically connected to the plurality of pins, respectively, the electrostatic withstand voltage test device comprises: a metal plate that mounts the mounting substrate; a power source that applies a voltage to the metal plate; an insulator that is arranged between the metal plate and the mounting substrate; a switching circuit that is connected between the plurality of terminals and a ground wiring; and a control section that controls the switching circuit, the switching circuit includes a plurality of first switches that are provided so as to correspond to the plurality of terminals, respectively, and connect the corresponding terminals to the ground wiring, and the control section turns on at least one first switch selected from the plurality of first switches when causing a charge accumulated in the conductor pattern to discharge to the ground wiring via the semiconductor device, and causes the charge accumulated in the conductor pattern to flow into the semiconductor device via the terminal corresponding to the selected at least one first switch and to discharge to the ground wiring via the semiconductor device.

2. The electrostatic withstand voltage test device according to claim 1, wherein the electrostatic withstand voltage test device further comprises a second switch that selectively connects the metal plate to the power source or the ground wiring in accordance with a control signal from the control section, the control section performs the following processes: turns off the plurality of first switches and connects the metal plate to the power source via the second switch, thereby electrifying the conductor pattern, turns on the at least one first switch, thereby causing the charge accumulated in the conductor pattern to discharge to the ground wiring via the semiconductor device, and turns off the at least one first switch and connects the metal plate to the ground wiring via the second switch, thereby de-electrifying the metal plate.

3. The electrostatic withstand voltage test device according to claim 1, wherein the electrostatic withstand voltage test device further comprises a plurality of probes that connect the plurality of first switches to the plurality of terminals, respectively, and the plurality of probes each have a movable portion that slides when a front end thereof is pressed.

4. The electrostatic withstand voltage test device according to claim 2, wherein the electrostatic withstand voltage test device further comprises a plurality of probes that connect the plurality of first switches to the plurality of terminals, respectively, and the plurality of probes each have a movable portion that slides when a front end thereof is pressed.

5. The electrostatic withstand voltage test device according to any one of claims 1 to 4, wherein the plurality of first switches each include a mercury relay.

6. The electrostatic withstand voltage test device according to any one of claims 1 to 4, wherein the electrostatic withstand voltage test device further comprises: a measurer that measures an electrical characteristic of the semiconductor device; a calculator that determines a failure of the semiconductor device based on a measured value of the electrical characteristic measured by the measurer; and ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A third switch is configured to selectively connect the switching circuit to the measurer or the ground wiring in accordance with a control signal from the control section.

7. An electrostatic withstand voltage test method for measuring an electrostatic withstand voltage of a semiconductor device mounted on a mounting substrate, wherein the semiconductor device has a plurality of pins, and a plurality of terminals and a conductor pattern are provided on the mounting substrate to be electrically connected to the plurality of pins, respectively, the electrostatic withstand voltage test method includes a step of causing the semiconductor device to generate electrostatic discharge, the step of causing the semiconductor device to generate electrostatic discharge includes steps of: charging the conductor pattern by applying a voltage to a metal plate disposed opposite the conductor pattern with an insulator interposed therebetween; and discharging electric charges accumulated in the conductor pattern to a ground wiring via the semiconductor device, the step of discharging includes steps of: turning on at least one first switch selected from a plurality of first switches configured to be provided corresponding to the plurality of terminals, respectively, and connect the corresponding terminal to the ground wiring, to cause the electric charges accumulated in the conductor pattern to flow into the semiconductor device via the terminal corresponding to the at least one first switch selected and to be discharged to the ground wiring via the semiconductor device.

8. The electrostatic withstand voltage test method according to claim 7, wherein the electrostatic withstand voltage test method further includes steps of: turning off the at least one first switch and connecting the metal plate to the ground wiring, thereby de-energizing the metal plate.

9. The electrostatic withstand voltage test method according to claim 7, wherein the step of causing the semiconductor device to generate electrostatic discharge further includes a step of bringing a plurality of probes provided corresponding to the plurality of first switches, respectively, to the plurality of terminals.

10. The electrostatic withstand voltage test method according to claim 8, wherein the step of causing the semiconductor device to generate electrostatic discharge further includes a step of bringing a plurality of probes provided corresponding to the plurality of first switches, respectively, to the plurality of terminals.

11. The electrostatic withstand voltage test method according to any one of claims 7 to 10, wherein the electrostatic withstand voltage test method further includes steps of: measuring a first electrical characteristic of the semiconductor device before the step of causing the semiconductor device to generate electrostatic discharge is performed; measuring a second electrical characteristic of the semiconductor device after the step of causing the semiconductor device to generate electrostatic discharge is performed; and determining a failure of the semiconductor device by comparing the first electrical characteristic with the second electrical characteristic.

12. The electrostatic withstand voltage test method according to claim 11, wherein the step of causing the semiconductor device to generate electrostatic discharge includes a step of causing the semiconductor device determined to be normal in the step of determining to generate electrostatic discharge again, the step of generating electrostatic discharge again includes a step of increasing a voltage applied to the metal plate. ​

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