Transmission circuit

Abstract

The primary side transmitter (600) drives the primary side input (512) of the isolation barrier (510) in response to transitions of the input signal (D in ). The secondary side receiver (700) generates an output signal (D out ) having logic values corresponding to signals produced at the secondary side output (514) of the isolation barrier (510). The secondary side transmitter (800) drives the secondary side input (516) of the isolation barrier (510) in accordance with the output signal (D out ). The primary side receiver (900) generates a return signal (D return ) having logic values corresponding to signals produced at the primary side output (518) of the isolation barrier (510). The primary side transmitter (600) repeats the driving of the primary side input (512) of the isolation barrier (510) until the logic values of the input signal (D in ) and the return signal (D return ) are identical.

Description

Technical Field

[0001] This disclosure relates to signal transmission between two insulated regions. Background Technology

[0002] In systems such as commercial power supplies, motors, measuring instruments, vehicle-mounted, industrial, and medical equipment, high electrical insulation is required for digital signal transmission between semiconductor chips for the purpose of (i) protecting the human body or equipment from surge currents or high voltages, or (ii) preventing malfunctions caused by noise separation, or (iii) protecting transistors in signal transmission between areas with large potential differences.

[0003] To ensure the insulation of signal transmission, wireless, optical coupling, capacitor, transformer, and GMR (Giant Magneto Resistive) methods have been proposed.

[0004] In digital signal transmission with insulating layers, even if the input logic signal does not change, external noise such as large changes in the common voltage (reference voltage) may cause malfunctions. Mismatch problems may occur in the logic signal levels between the primary side (transmitter TX side) and the secondary side (receiver RX side).

[0005] In systems where reliability is required, such as medical devices, aerospace equipment, or automotive / industrial equipment, this problem is unacceptable.

[0006] Therefore, through the communication IC between the insulating layers, electrical countermeasures are implemented to improve common-mode transient immunity (CMTI), and systematic countermeasures are taken.

[0007] As a systemic countermeasure, the following solutions are proposed.

[0008] (Existing Example 1)

[0009] In Example 1, even if there is no input logic transition for a certain period, the TX side compensates for the TX-RX logic mismatch when transmission fails or there is no signal by sending periodic refresh pulses based on a timer. On the RX side, if there is no logic signal transition for a certain period, the output is set to a predetermined safe level by monitoring a timer.

[0010] (Existing Example 2)

[0011] In Example 2, using OOK (On-Off Keying) or FSK (Frequency Shift Keying) can typically determine the logic state as either L or H. Even signal changes caused by erroneous actions can be immediately corrected to the correct value.

[0012] As an electrical countermeasure, the following solutions are typically adopted.

[0013] • A transformer that uses magnetic field coupling to prevent noise transmission between the primary and secondary windings caused by the electric field.

[0014] • Signal transmission between the primary and secondary windings is achieved via differential signaling. This is almost essential in capacitor-based (electric field coupling) systems with lower CMTI (Continuous Coupling Intake).

[0015] • Increase transmission power to improve the signal-to-noise ratio. However, this method has limitations due to the increased power requirements.

[0016] • This can be addressed using standard circuit designs, such as filtering to remove noise and employing hysteresis circuits. However, limitations exist when the signal-to-noise ratio (S / N) is low at frequencies or voltage levels.

[0017] Existing technical documents

[0018] Patent documents

[0019] Patent Document 1: U.S. Patent No. 8,873,644

[0020] Patent Document 2: U.S. Patent No. 9,853,749

[0021] Non-patent literature

[0022] Non-patent literature 1: Wei Zhang, Mateo Begue, "Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers", Texas Instruments, Application Report: SLUA909, August 2018 Summary of the Invention

[0023] The technical problem that the invention aims to solve

[0024] The inventors of this invention studied existing countermeasures and ultimately recognized the following technical problems.

[0025] (Existing Example 1)

[0026] When there is a logic mismatch between the primary and secondary sides, a response delay occurs due to the timer cycle. Furthermore, with a long refresh cycle, it is necessary to allow for extended periods of logic mismatch. On the other hand, shortening the refresh cycle increases power consumption. Moreover, it is difficult to determine the optimal refresh cycle based on changing conditions.

[0027] Furthermore, even with continuous transmission failures, the RX side was not corrected to the correct signal level. The RX side watch timer was originally set up not for logical matching, but for the fail-safe function to handle transmission failures such as malfunctions.

[0028] Both TX and RX require stable peripheral circuitry (oscillators, etc.) for timers, and consume power even when there is no signal, which also increases the area cost.

[0029] (Existing Example 2)

[0030] Increased power consumption occurs to transmit the carrier frequency, even when there is no signal. Furthermore, the demodulation circuitry, including the bias circuit, requires constant current, increasing area costs. Moreover, the degradation of EMI (Electromagnetic Interference) caused by the carrier frequency, or the increased power consumption or circuit area of ​​countermeasure circuits (spread spectrum), are unavoidable.

[0031] Thus, existing methods are overly complex, requiring numerous components and a large area, resulting in many drawbacks. Consequently, these circuits are difficult to implement, hindering cost reduction and low power consumption.

[0032] This disclosure was made in view of such technical problems, and one of the exemplary purposes of one of its solutions is to provide an isolated signal transmission circuit capable of eliminating logic mismatch with low power consumption.

[0033] Methods for solving technical problems

[0034] One aspect of this disclosure relates to a transmission circuit. The transmission circuit includes: an insulating layer; a primary-side transmitter that drives a primary-side input of the insulating layer in response to a change in an input signal; a secondary-side receiver that generates an output signal having a logic value corresponding to a signal generated at a secondary-side output of the insulating layer; a secondary-side transmitter that drives a secondary-side input of the insulating layer according to the output signal; and a primary-side receiver that generates a return signal having a logic value corresponding to a signal generated at a primary-side output of the insulating layer. The primary-side transmitter repeats the driving of the primary-side input of the insulating layer until the logic value of the input signal matches that of the return signal.

[0035] Furthermore, any combination of the above-mentioned constituent elements, or any scheme that transforms the manifestation of this disclosure between methods, apparatuses, etc., is also valid as a solution of the present invention.

[0036] Invention Effects

[0037] According to one scheme disclosed herein, logical mismatches can be resolved with low power consumption. Attached Figure Description

[0038] Figure 1 This is a circuit diagram of the transmission circuit in the implementation method.

[0039] Figure 2 yes Figure 1 The timing diagram of the transmission circuit under normal conditions.

[0040] Figure 3 yes Figure 1 Timing diagram for errors in the transmission circuit.

[0041] Figure 4 This is a block diagram of the transmission circuit of Embodiment 1.

[0042] Figure 5 This is a timing diagram illustrating the signal transmission in Embodiment 1.

[0043] Figure 6 This is a circuit diagram showing an example of the structure of a primary-side transmitter.

[0044] Figure 7 This is a circuit diagram showing a specific structural example of a primary-side transmitter.

[0045] Figure 8 This is a circuit diagram showing an example of the structure of a secondary-side receiver.

[0046] Figure 9 This is a circuit diagram showing an example of the overall structure of a transmission circuit.

[0047] Figure 10 (a) to (c) are shown Figure 9 The timing diagram of the operation of the transmission circuit.

[0048] Figure 11 (a) and (b) are circuit diagrams of the transmission circuit in Example 2.

[0049] Figure 12 (a) and (b) are explanations of... Figure 9 Timing diagram of problems arising in the transmission circuit.

[0050] Figure 13 This is a circuit diagram showing the structure of the primary side of the transmission circuit in Embodiment 3.

[0051] Figure 14This is a circuit diagram showing the structure of the secondary side of the transmission circuit in Embodiment 3.

[0052] Figure 15 This is a timing diagram showing the operation of the transmission circuit in Embodiment 3.

[0053] Figure 16 This is the circuit diagram of the secondary receiver in Variation Example 1.

[0054] Figure 17 This is the circuit diagram of the secondary receiver in variation example 2.

[0055] Figure 18 This is a circuit diagram of an insulated converter with a transmission circuit.

[0056] Figure 19 This is a circuit diagram of a half-bridge converter with transmission circuitry. Detailed Implementation

[0057] (Summary of the implementation method)

[0058] This summary provides an overview of several exemplary embodiments of this disclosure. This summary serves as a preface to the subsequent detailed description, aiming to provide a basic understanding of the embodiments and briefly illustrating several concepts of one or more embodiments, and is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not a comprehensive overview of all embodiments that should be considered, nor is it intended to limit the indispensable components of the embodiments. For convenience, "an embodiment" is sometimes used to indicate one or more embodiments (examples or variations) disclosed in this specification.

[0059] One embodiment of the transmission circuit includes: an insulating layer; a primary-side transmitter that drives a primary-side input of the insulating layer in response to a change in an input signal; a secondary-side receiver that generates an output signal having a logic value corresponding to a signal generated at a secondary-side output of the insulating layer; a secondary-side transmitter that drives a secondary-side input of the insulating layer according to the output signal; and a primary-side receiver that generates a return signal having a logic value corresponding to a signal generated at a primary-side output of the insulating layer. The primary-side transmitter repeats the driving of the primary-side input of the insulating layer until the logic values ​​of the input signal and the return signal are consistent.

[0060] In this transmission circuit, by adding a return channel for transmitting information from the secondary side to the primary side, the primary-side transmitter can determine whether the information has been transmitted correctly. Furthermore, by repeating the signal transmission until the information is correctly transmitted, the signal can be reliably transmitted to the secondary side. Because signal retransmission is minimized, matching can be achieved with minimal power consumption. Additionally, the primary-side input and primary-side output of the insulating layer can be independent ports or the same port. Similarly, the secondary-side input and secondary-side output of the insulating layer can be independent ports or the same port.

[0061] In one embodiment, the primary-side transmitter may include: a first comparator circuit that compares the logic values ​​of an input signal and a return signal; a first oscillation circuit that controls oscillation and stops based on the comparison result of the first comparator circuit; and a first output unit that drives the primary-side input of the insulating layer based on the input signal and a first pulse signal generated by the first oscillation circuit. According to this structure, the primary-side input of the insulating layer can be repeatedly driven during periods when the input signal and the return signal are inconsistent.

[0062] In one embodiment, the first oscillation circuit may also include a ring oscillator.

[0063] In one embodiment, the primary transmitter may pulse drive the primary side of the insulating layer with a first polarity when the input signal is high, and pulse drive the primary side of the insulating layer with a second polarity when the input signal is low.

[0064] In one embodiment, the insulating layer may also include a first transformer, whose primary winding is connected to a primary-side transmitter and whose secondary winding is connected to a secondary-side receiver. The primary-side transmitter can supply a pulse current of a first polarity to the primary winding of the first transformer when the input signal is high, and generate a pulse current of a second polarity when the input signal is low. The secondary-side receiver may include: a latching circuit, with a set terminal connected to one end of the secondary winding of the first transformer and a reset terminal connected to the other end of the secondary winding; a first switch disposed between a common voltage node generating a common voltage and the set terminal, which is turned on when the output of the latching circuit is high; and a second switch disposed between the common voltage node and the reset terminal, which is turned on when the output of the latching circuit is low.

[0065] According to this structure, by controlling the first and second switches based on the state of the latching circuit, and by controlling the state of the secondary winding of the first transformer, an operation equivalent to that of a pulse-set / reset type transmission circuit can be achieved with a single transformer. This structure has the advantages of the pulse-set / reset type, and since only one transformer is needed, the circuit area can be reduced. Furthermore, it eliminates the transmission speed limitation caused by the time delay deviation between two transformers, thus enabling further high-speed transmission.

[0066] In one embodiment, the secondary-side receiver may further include a switch control unit that controls the first switch and the second switch according to the state of the latch circuit. The switch control unit disconnects the second switch after the transition of the pulse current of the first polarity ends, and disconnects the first switch after the transition of the pulse current of the second polarity ends. This suppresses voltage jumps at the terminals of the secondary winding and improves stability.

[0067] In one embodiment, the switch control unit can turn off the second switch after a predetermined time after the first switch is turned on, and turn off the first switch after a predetermined time after the second switch is turned on. Thus, by fixing the voltage of the set terminal and reset terminal during the period when both the first and second switches are on, the state transition of the latching circuit can be prevented, further stabilizing the circuit operation.

[0068] In one embodiment, the primary-side transmitter may additionally drive the primary-side input of the insulating layer after the logic values ​​of the input signal and the return signal are consistent. The secondary-side transmitter may repeat the driving of the secondary-side input of the insulating layer during periods when the current output signal is inconsistent with the previous output signal. According to this structure, the secondary-side transmitter stops operating after correctly transmitting the return signal, and is also resistant to anomalies in the return channel.

[0069] In one embodiment, the secondary-side transmitter may include: a second comparator circuit that compares the previous logic value of the output signal with the current logic value of the output signal; a second oscillation circuit that controls oscillation and stops based on the comparison result of the second comparator circuit; and a second output unit that drives the secondary-side input of the insulating layer based on the second pulse signal generated by the second oscillation circuit during oscillation.

[0070] In one embodiment, the transmission circuit may further include a spike removal circuit for removing spike pulses from the output of the secondary receiver.

[0071] In one embodiment, the common voltage may be the ground voltage, and the first and second switches may be NMOS transistors.

[0072] In one embodiment, the common voltage may be the power supply voltage, and the first and second switches may be PMOS transistors.

[0073] In one embodiment, the latch circuit may include a first NOR gate and a second NOR gate that are cross-connected.

[0074] In one embodiment, the latch circuit may include a first NAND gate and a second NAND gate that are cross-connected.

[0075] In one embodiment, the common voltage may be ground voltage, and the first and second switches may be NMOS transistors. The transmission circuit may further include: a first inverter that receives the inverted output of the latch circuit at its input node and whose output node is connected to the gate of the first switch; and a second inverter that receives the output of the latch circuit at its input node and whose output node is connected to the gate of the second switch.

[0076] In one embodiment, the common voltage may be ground voltage, and the first and second switches may be NMOS transistors. The transmission circuit may further include: a first NAND gate that receives the inverted output of the latch circuit at a first input node, and whose output node is connected to the gate of the first switch; a first delay circuit that delays the output of the first NAND gate; a second NAND gate that receives the output of the latch circuit at a first input node, receives the output of the first delay circuit at a second input node, and whose output node is connected to the gate of the second switch; and a second delay circuit that delays the output of the second NAND gate and supplies it to the second input node of the first NAND gate.

[0077] In one embodiment, the common voltage may be the power supply voltage, and the first and second switches may be PMOS transistors. The transmission circuit may further include: a third inverter that receives the output of the latch circuit at the input node and whose output node is connected to the gate of the first switch; and a fourth inverter that receives the inverted output of the latch circuit at the input node and whose output node is connected to the gate of the second switch.

[0078] (Implementation Method)

[0079] The preferred embodiments will now be described with reference to the accompanying drawings. The same or equivalent constituent elements, components, and processes shown in the various drawings are labeled with the same reference numerals, and repeated descriptions are omitted where appropriate. Furthermore, the embodiments are not intended to limit the invention but are illustrative, and not all features or combinations thereof described in the embodiments are essential parts of the invention.

[0080] In this specification, the term "the state of connection between component A and component B" includes the case where component A and component B are physically and directly connected, as well as the case where component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved through their coupling.

[0081] Similarly, the phrase "the state in which component C is positioned between component A and component B" means, in addition to the cases where component A and component C are directly connected, or component B and component C are directly connected, the cases where they are indirectly connected via other components without substantially affecting their electrical connection state or impairing the function or effect achieved through their coupling.

[0082] Figure 1 This is a circuit diagram of the transmission circuit 500 according to the embodiment. The transmission circuit 500 includes an insulating layer 510, a primary-side transmitter 600, a secondary-side receiver 700, a secondary-side transmitter 800, and a primary-side receiver 900. The transmission circuit 500 receives the input signal D on the primary side 502. in On the secondary side, 504 generates a signal with the input signal D. in The corresponding logic value output signal D out .

[0083] The insulating layer 510 is composed of passive components such as transformers or capacitors, ensuring electrical insulation between the primary side 502 and the secondary side 504. The insulating layer 510 has a primary-side input 512, a secondary-side output 514, a secondary-side input 516, and a primary-side output 518. Driving the primary-side input 512 changes the electrical state of the secondary-side output 514. Similarly, driving the secondary-side input 516 changes the electrical state of the primary-side output 518. Furthermore, the primary-side input 512 and the primary-side output 518 can share the same port, and the secondary-side output 514 and the secondary-side input 516 can share the same port.

[0084] The primary-side transmitter 600 responds to the input signal D in The conversion drives the primary-side input 512 of the insulating layer 510. The secondary-side output 514 of the insulating layer 510 generates an electrical signal S corresponding to the drive of the primary-side transmitter 600. RX2 The driving configuration of the primary-side transmitter 600 (which can serve as the driving signal S) TX1 (Understanding the pattern, waveform, and polarity of the input signal D) in The transition from low to high, and the input signal D in The transition from high to low is different, resulting in a 514 output on the secondary side, producing different forms of electrical signals S that can be distinguished. RX2 .

[0085] The secondary receiver 700 generates an electrical signal S from the secondary output 514 of the insulating layer 510. RX2 The form of the output signal D, that is, the output signal D having a logic value corresponding to the electrical state of the secondary-side output 514. out When the signal is transmitted normally, the output signal D... out The logic value and the input signal D in The logical values ​​are consistent.

[0086] The primary-side transmitter 600 and the secondary-side receiver 700 form a signal D from the input signal. in Forward channel transmitted from primary side 502 to secondary side 504.

[0087] The secondary transmitter 800 outputs signal D. out When the signal changes, the secondary side input 516 of the driving insulating layer 510 is activated. The primary side output 518 of the insulating layer 510 generates an electrical signal S corresponding to the drive of the secondary side transmitter 800. RX1 The driving method of the secondary transmitter 800 (as driving signal S) TX2 (The pattern, waveform, or polarity of the output signal D is considered.) out The transition from low to high, and the output signal D out The transition from high to low is different, resulting in the primary-side output 518 generating different forms of electrical signals S that can be distinguished. RX1 .

[0088] The primary-side receiver 900 generates a signal S that is produced by the primary-side output 518 in the insulating layer 510. RX1 In the form of a return signal D, which has a logic value corresponding to the electrical state of the primary-side output 518. return .

[0089] The secondary transmitter 800 and the primary receiver 900 form a signal D that outputs the signal D. out The return channel from the secondary side 504 back to the primary side 502.

[0090] The primary-side transmitter 600 repeatedly drives the primary-side input 512 of the insulating layer 510 until the input signal D. in With return signal D return The logical values ​​are consistent.

[0091] In addition, electrical signal S TX1 S RX2 S TX2 S RX1 It can be a voltage signal or a current signal.

[0092] The above describes the basic structure of the transmission circuit 500. Its operation will now be explained.

[0093] Figure 2 yes Figure 1 The timing diagram of the transmission circuit 500 during normal operation. At time t0, the input signal D... in When transitioning from low to high, the primary-side transmitter 600 generates the first state. electrical signal S TX1 As a result, output 514 is generated on the secondary side of the insulating layer 510, producing the first state. electrical signal S RX2 The secondary receiver 700 detects the first state. electrical signal S RX2After that, output a high output signal D out .

[0094] The secondary transmitter 800 outputs signal D. out After transitioning to a higher state, the first state is generated. electrical signal S TX2 As a result, output 518 is generated on the primary side of insulating layer 510, producing a first state. electrical signal S RX1 The primary-side receiver 900 detected the first state. electrical signal S RX1 Then, output a high return signal D. return .

[0095] When the transmission circuit 500 is working normally, the input signal D in After transitioning to high, return signal D return Immediately transitions to high, input signal D in With return signal D return The logical values ​​are consistent. Therefore, the primary-side transmitter 600 stops in the first state. electrical signal S TX1 The generation of the signal awaits the next input signal D. in The transformation.

[0096] At time t1, the input signal D in When transitioning from high to low, the primary-side transmitter 600 generates a second state. electrical signal S TX1 As a result, output 514 is generated on the secondary side of insulating layer 510, producing a second state. electrical signal S RX2 The secondary receiver 700 detects the second state. electrical signal S RX2 After that, output a low output signal D. out .

[0097] The secondary transmitter 800 outputs signal D. out When it transitions to low, a second state is generated. electrical signal S TX2 As a result, output 518 is generated on the primary side of insulating layer 510, producing a second state. electrical signal S RX1 The primary-side receiver 900 detects the second state. electrical signal S RX1 Then, output a low return signal D. return .

[0098] When the transmission circuit 500 is working normally, the input signal Din After transitioning to low, return signal D return Immediately switch to low, input signal D in With return signal D return The logical values ​​are consistent. Therefore, the primary-side transmitter 600 stops in the second state. electrical signal S TX1 The generation of the next input signal D in The transformation is in standby mode.

[0099] Figure 3 yes Figure 1 Timing diagram for error in transmission circuit 500. At time t0, input signal D... in When transitioning from low to high, the primary side transmitter 600 generates the first state. electrical signal S TX1 .

[0100] Assuming that due to some anomaly, output 514 on the secondary side of insulating layer 510 does not produce the first state. electrical signal S RX2 The secondary receiver 700 did not detect the first state. electrical signal S RX2 Therefore, the output signal D of the secondary receiver 700 out It remains at a low level.

[0101] At this time, since no output signal D occurs... out Due to the change in the state, the secondary-side transmitter 800 does not drive the secondary-side input 516 of the insulating layer 510. Therefore, the primary-side output 518 of the insulating layer 510 does not produce a state change, and the output of the primary-side receiver 900, i.e., the return signal D, remains unchanged. return It remains at a low level.

[0102] Return signal D return With input signal D in The logical values ​​are inconsistent. Therefore, the primary transmitter 600 generates the first state again at time t1. electrical signal S TX1 Assuming that due to some anomaly, output 514 is generated on the secondary side of insulating layer 510, and the first state is not produced. electrical signal S RX2 At this time, similar to the previous time, the secondary receiver 700 was unable to detect the first state. electrical signal S RX2 Output signal D out It remains at a low level.

[0103] Since no output signal D is generated outThe change means that the secondary-side transmitter 800 does not drive the secondary-side input 516 of the insulating layer 510, and the output of the primary-side receiver 900 is the return signal D. return It remains at a low level.

[0104] Return signal D return With input signal D in The logical values ​​are inconsistent. Therefore, the primary transmitter 600 generates the first state at time t2. electrical signal S TX1 The electrical signal S TX1 After normal transmission to the secondary side, output 514 is generated on the secondary side of the insulating layer 510, producing the first state. electrical signal S RX2 The secondary receiver 700 outputs a high output signal D. out .

[0105] The secondary transmitter 800 outputs signal D. out After transforming into a high state, the first state is generated. electrical signal S TX2 As a result, output 518 is generated on the primary side of insulating layer 510, producing a first state. electrical signal S RX1 The primary-side receiver 900 detects the first state. electrical signal S RX1 Then, output a high return signal D. return .

[0106] As a result, the return signal D return With input signal D in The logical values ​​are consistent. Thus, the primary-side transmitter 600 stops in its first state. electrical signal S TX1 The generation of .

[0107] The above describes the operation of the transmission circuit 500. In this transmission circuit 500, by adding a return channel for information to be returned from the secondary side 504 to the primary side 502, the primary side transmitter 600 can determine whether the information has been transmitted correctly. Furthermore, by repeating the transmission of the signal until the information is transmitted correctly, the signal can be reliably transmitted to the secondary side 504.

[0108] The transmission circuit 500 stops operating after the signal is transmitted correctly, thus resulting in a smaller increase in power consumption and the advantage of suppressing EMI.

[0109] This disclosure or the present invention can be used as Figure 1The invention may be understood through block diagrams or circuit diagrams, or may involve various devices and methods derived from the above description, but is not limited to a specific structure. The following description is not intended to narrow the scope of the invention, but rather to aid in understanding the nature or operation of the invention, or to clarify it, by providing more specific structural examples or embodiments.

[0110] (Example 1)

[0111] Figure 4 This is a block diagram of the transmission circuit 500A of Embodiment 1. The insulating layer 510 includes a transformer T1 for the forward channel and a transformer T2 for the return channel. Transformers T1 and T2 each have a primary winding Wp and a secondary winding Ws. The primary winding Wp of transformer T1 corresponds to the primary-side input 512, and the secondary winding Ws of transformer T1 corresponds to the secondary-side output 514. The secondary winding Ws of transformer T2 corresponds to the secondary-side input 516, and the primary winding Wp of transformer T2 corresponds to the primary-side output 518.

[0112] The primary-side transmitter 600 supplies a drive signal I to the primary winding Wp of transformer T1. TX1 In the secondary winding Ws of transformer T1, a current signal I is generated. TX1 The corresponding voltage signal V RX2 Current signal I TX1 and voltage signal V RX2 Corresponding to Figure 1 electrical signal S TX1 R RX2 .

[0113] The voltage V generated by the secondary winding Ws of transformer T1 RX2 It is represented by equation (1).

[0114] V RX2 =M·dI TX1 / dt…(1)

[0115] M is a cross-differentiation, with M = k√(L) TX L RX ) indicates that k is the coupling coefficient. L TX L RX The self-inductance of the primary winding Wp and the secondary winding Ws.

[0116] Figure 5 This is a timing diagram illustrating the signal transmission in Embodiment 1. In this embodiment, the primary-side transmitter 600 will respond to the input signal D. in The current signal I whose polarity (or orientation) changes with the level of change. TX1 It is supplied to the primary winding Wp. Specifically, the input signal D in When the current signal I changes from low to high... TX1The pulse current Ip is of the first polarity, which corresponds to the electrical signal S. TX1 First state Conversely, the input signal D in When the current signal I transitions from high to low... TX1 The pulse current In is of the second polarity, which corresponds to the electrical signal S. TX1 second state

[0117] In the secondary winding Ws of transformer T1, a current with the same characteristics as the driving current I is generated. TX1 The polarity of the pulsed voltage signal V corresponds to the polarity of the signal. RX2 The secondary-side receiver 700 detects the voltage signal V. RX2 The polarity is determined, and the output signal D is changed accordingly. out The logical value. In this example, based on the positive polarity voltage signal V. RX2 Output signal D out Transitioning to high, based on the negative polarity of the voltage signal V RX2 Output signal D out It changed to low.

[0118] return Figure 4 The primary-side transmitter 600 generates the input signal D. in High, return signal D return During periods of low inconsistency, a positive polarity pulse current Ip is repeatedly generated. Furthermore, the primary-side transmitter 600 generates the input signal D. in Low, return signal D return During periods of high inconsistency, a negative polarity pulse current In is repeatedly generated.

[0119] The return channel, including the secondary-side transmitter 800, the primary-side receiver 900, and the transformer T2, can employ the same transmission method as the forward channel. Specifically, the secondary-side transmitter 800 supplies a drive current I to the secondary winding Ws of the transformer T2. TX2 Output signal D out When it transitions to high, the current signal I TX2 The pulse current Ip is of the first polarity, which corresponds to the electrical signal S. TX2 First state Conversely, when the output signal D out When it turns low, the current signal I TX2 This is a pulse current of the second polarity, corresponding to the electrical signal S. TX2 second state

[0120] In the primary winding Wp of transformer T2, a current signal I is generated. TX2 The corresponding voltage signal VRX1 The primary-side receiver 900 detects the voltage signal V. RX1 The polarity of the signal is determined, and the return signal D is changed accordingly. return The logical value. For example, based on the positive polarity voltage signal V. RX1 Output signal D return Transitioning to high, based on the negative polarity of the voltage signal V RX1 Return signal D return It changed to low.

[0121] Figure 6 This is a circuit diagram showing a structural example of a primary-side transmitter 600A. The primary-side transmitter 600A includes a first comparator circuit 610, a first oscillation circuit 620, and a first output section 630. The first comparator circuit 610 compares the input signal D. in and return signal D return The logic value is input to the enable terminal of the first oscillation circuit 620, where the comparison result of the first comparison circuit 610 is input. If the comparison result is inconsistent, the circuit becomes enabled (oscillation), generating a first pulse signal Sp1 at a predetermined frequency. If the comparison result is consistent, the circuit becomes disabled (stop). The frequency of the first pulse signal Sp1 specifies the repetition period of the signal transmission retry, and the pulse width of the first pulse signal Sp1 specifies the pulse width of the pulse currents Ip and In.

[0122] The first output unit 630 outputs the signal D based on the input signal D. in The first pulse signal Sp1 drives the primary-side input 512 of the insulating layer 510. Specifically, the input signal D... in When the first pulse signal Sp1 is active, a drive current I of the first polarity is output. TX1 (Pulse signal Ip). Input signal D in When the first pulse signal Sp1 is at a low level, a second polarity drive current I is output. TX2 (Pulse current In).

[0123] Figure 7 This is a circuit diagram showing a specific structural example of the primary-side transmitter 600A. The first output section 630 is an H-bridge circuit, including push-pull output stages (inverters) 632 and 634. One output stage 632 takes the input signal D... in The signal is inverted and supplied to one end of the primary winding Wp. Input signal D in During the high period, the output Vo1 of the output stage 632 is low (GND1), and the input signal D... in During the period when it is low, the output Vo1 of the output stage 632 is high (VDD1).

[0124] Output stage 634 receives control pulses D from the first oscillator circuit 620. delay ( Figure 6 The pulse signal Sp1) is inverted and supplied to the other end of the primary winding Wp. Control pulse D delay During the high period, the output Vo2 of the output stage 634 is low (GND1), and the control pulse D... delay During the period when it is low, the output Vo2 of the output stage 634 is high (VDD1).

[0125] The first comparison circuit 610 includes, for example, an XOR (exclusive XOR) gate 612 to generate a representation of the input signal D. in With return signal D return Consistent and inconsistent signals are supplied to the enable terminal (negative logic) ENB of the first oscillation circuit 620.

[0126] The first oscillation circuit 620 can be understood as a type of ring oscillator, referred to in this specification as a pulse-output type (or intermittent oscillation type) ring oscillator 621. The pulse-output type ring oscillator 621 oscillates during the period when the enable terminal EN is high, generating a control pulse D. delay The pulse output type ring oscillator 621 includes a specified control pulse D. delay At least one delay element D1, D2 of the frequency (period).

[0127] AND gates 622, XOR gates 623, and 624 are inserted into a pulse-output ring oscillator 621. AND gate 622 cuts off the pulse-output ring oscillator 621, stopping its oscillation, while the enable signal EN is low. Furthermore, the combination of AND gate 622 and the inverting delay element D3 determines the duty cycle of the control pulse Ddelay.

[0128] XOR gate 623, based on input signal D in AND the output logic value of the AND gate 622, causing the control pulse D to... delay The polarity is reversed. The XOR gate 624 operates according to the control pulse D. delay With return signal D return The logic value of the control pulse D makes the control pulse D delay The polarity is reversed.

[0129] Figure 8 This is a circuit diagram showing an example of the structure of a secondary-side receiver 700. The secondary-side receiver 700 includes a latching circuit 710, a switch control unit 720C, a first switch swp, and a second switch swn.

[0130] In the latching circuit 710, the set terminal (S) is connected to one end of the secondary winding Ws of the transformer T1, and the reset terminal (R) is connected to the other end of the secondary winding Ws of the transformer T1.

[0131] The latch circuit 710 can be any two-input latch circuit with set and reset inputs, without restrictions on logic polarity or structure. In this embodiment, the latch circuit 710 is a NOR-type SR latch, including two NOR gates 712 and 714 crossed at an angle.

[0132] The first switch, swp, is set to generate a common voltage V. COM Between the common voltage node COM and the set terminal (S), the output D of the latch circuit 710 out When the voltage is high, it becomes ON. The second switch swn is set between the common voltage node COM and the reset terminal (R), and the latch circuit 710 becomes ON when the output is low. In this example, the common voltage V COM The voltage is grounded (GND2), and the first switch (swp) and the second switch (swn) are NMOS transistors. Alternatively, the common voltage (VCOM) can be used as the power supply voltage (VDD2), in which case the first switch (swp) and the second switch (swn) can also be used as PMOS transistors.

[0133] The switch control unit 720C outputs signal D based on the state of the latch circuit 710. out The logic values ​​control the first switch (swp) and the second switch (swn).

[0134] Switch control unit 720C waits for current pulse I TX The transition (tail edge) ends, disconnecting the first switch (swp) and the second switch (swn). That is, the switch control unit 720C activates the pulse current I of the first polarity. TX After the transition is complete, the second switch swn is disconnected, and the pulse current I of the second polarity is applied. TX After the transition is complete, disconnect the first switch swp.

[0135] Here, the switch control unit 720C could utilize a simple delay, but in this embodiment, a delay based on a non-overlapping circuit is employed. After the first switch SWP is turned on, the switch control unit 720C turns off the second switch SWN after a predetermined time; after the second switch SWN is turned on, the first switch SWP is turned off after a predetermined time. Thus, by setting the period during which the first switch SWP and the second switch SWN are both on, the voltage V at the set terminal and the reset terminal is controlled. RXS V RXR Both are fixed to ground GND2, thereby further stabilizing the signal.

[0136] The switch control unit 720C includes a first NAND gate 726, a first delay circuit 728, a second NAND gate 730, and a second delay circuit 732.

[0137] The first NAND gate 726 receives the inverted output D of the latch circuit 710 at the first input node. outb The output node is connected to the gate of the first switch swp. The first delay circuit 728 delays the output V of the first NAND gate 726. RST1 The second NAND gate 730 receives the output D of the latch circuit 710 at the first input node. out The second input node receives the output of the first delay circuit 728, and the output node is connected to the gate of the second switch swn. The second delay circuit 732 converts the output V of the second NAND gate 730 into a voltage. RST2 The delay is then supplied to the second input node of the first NAND gate 726.

[0138] Figure 9 This is a circuit diagram showing an example of the overall structure of the transmission circuit 500A. The structure of the primary-side transmitter 600 and the secondary-side receiver 700 is similar to... Figure 7 , Figure 8 The primary receiver 900 can be configured in the same way as the secondary receiver 700.

[0139] The secondary-side transmitter 800 includes a pre-driver 840 and a second output section 830. The second output section 830 is an H-bridge circuit, including push-pull output stages (inverters) 832 and 834. One output stage 832 outputs signal D... out The phase is reversed and supplied to one end of the secondary winding Ws of transformer T2. Output signal D out During the high period, the output Vo1 of the output stage 832 is low (GND2), and the output signal D... out During the period when it is low, the output Vo1 of the output stage 832 is high (VDD2).

[0140] Output stage 834 receives control pulses D from pre-driver 840 odelay The phase is reversed, and the power is supplied to the other end of the secondary winding Ws of transformer T2. Control pulse D odelay During the high period, the output Vo2 of the output stage 834 is low (GND12), and the control pulse D... odelay During the period when it is low, the output Vo2 of the output stage 834 is high (VDD2).

[0141] The pre-driver 840 includes a delayed output signal D out And generate control pulse D odelay The delay circuit 842.

[0142] The above is a structural example of a 500A transmission circuit. Its operation will now be explained.

[0143] Figure 10 (a) to (c) are shown Figure 9 The timing diagram for the operation of the 500A transmission circuit. Figure 10 (a) shows the operation under normal conditions. Input signal D in When transitioning to high, with the return signal D return Since the inconsistency is not resolved, the first oscillation circuit 620 is enabled, resulting in the generation of a pulse current Ip of the first polarity.

[0144] When the pulse current Ip is correctly transmitted to the secondary side 504, the output signal D out It becomes high, and returns signal D. return It also becomes high, the input signal D in and return signal D return The logic values ​​are consistent. As a result, the first oscillation circuit 620 stops, and the pulse current Ip also stops.

[0145] Input signal D in When transitioning to low, it corresponds to the return signal D. return The inconsistency causes the first oscillation circuit 620 to become enabled, resulting in the generation of a pulse current In of the second polarity. When the pulse current In is correctly transmitted to the secondary side 504, the output signal D... out Become low, return signal D return It also becomes low, the input signal D in With return signal D return The logic values ​​are consistent. As a result, the first oscillation circuit 620 stops, and the pulse current In also stops.

[0146] Figure 10 (b) shows the action when the transmission of pulse current Ip1 from the primary side transmitter 600 to the secondary side receiver 700 fails.

[0147] Input signal D in When transitioning to a high level, it is related to the return signal D. return The inconsistency causes the first oscillation circuit 620 to become enabled, resulting in the generation of a pulse current Ip1 of the first polarity.

[0148] When the transmission of pulse current Ip1 fails, the output signal D... out The input signal D remains low. in And represents the output signal D out The return signal D return The mismatch persists. As a result, the first oscillation circuit 620 continues to oscillate, thus the primary-side transmitter 600 generates a second pulse current Ip2. When the pulse current Ip2 is successfully transmitted, the output signal D...out Transform to high, input signal D in And represents the output signal D out The return signal D return Consistent. As a result, the first oscillation circuit 620 becomes disabled and stops operating, and will not generate pulse current Ip thereafter.

[0149] Figure 10 (c) shows the operation of the secondary receiver 700 when the input changes, even though the input signal Din does not change, due to noise and other factors.

[0150] One end V of the secondary winding Ws of transformer T1 RXR2 When noise Nx is generated, the output signal D out Switch to low, return signal D return It becomes low. As a result, the input signal D in and return signal D return The inconsistency becomes apparent, and the first oscillation circuit 620 enters the enabled state. At this time, the input signal D... in The voltage is high, thus generating a pulse current Ipx of the first polarity. When this pulse current Ipx is transmitted to the secondary side 504, the output signal D is generated. out Transition to high, return signal D return It is also high. As a result, the input signal Din and the return signal D... return In line with this, the first oscillation circuit 620 becomes disabled.

[0151] The above describes the operation of transmission circuit 500A. According to this transmission circuit 500, in the event of a mismatch between the primary side 502 and the secondary side 504, matching can be achieved by sending a smaller number of additional transmission pulses Ip and In.

[0152] Furthermore, since it can be constructed using logic circuits that do not flow a constant current, the current consumption during signal transitions is zero. Therefore, it can operate by consuming current proportional to the data transmission speed, significantly reducing power consumption.

[0153] (Example 2)

[0154] Figure 11 Figures (a) and (b) are circuit diagrams of the transmission circuit 500B in Embodiment 2. In the transmission circuit 500B, the secondary-side receiver 700 further includes a spike removal circuit 740. (See diagram for reference.) Figure 11 As shown in (b), the spike removal circuit 740 includes a hysteresis trigger 742 and a delay circuit 744.

[0155] The delay circuit 744 delays the input signal (i.e., the output of the secondary-side receiver 700). The hysteresis flip-flop 742 receives the input signal at the first input node and the output of the delay circuit 744 at the second input node. The hysteresis flip-flop 742 can also be called a Muller C-Element. It retains the previous output value when the logic of the two inputs IN1 and IN2 is inconsistent. When both inputs IN1 and IN2 are low, the output is low; when both inputs IN1 and IN2 are high, the output is high.

[0156] According to Example 2, it is possible to remove in Figure 10 In the case of (c), the output signal D out The generated pulse has a shorter pulse width than the delay of the delay circuit 744.

[0157] (Example 3)

[0158] In Example 1, if an anomaly occurs in the return channel, there may be unnecessary power consumption or the mismatch may be impossible to eliminate.

[0159] Figure 12 (a) and (b) are explanations of... Figure 9 Timing diagram of the problem occurring in the 500A transmission circuit. Figure 12 (a) shows that the return signal D cannot be sent correctly. return In this situation, although the output signal D out With input signal D in The logical values ​​are consistent, but the return signal D is correct. return With input signal D in The inconsistency causes the primary-side transmitter 600 to repeatedly generate pulse current Ip, which consumes useless power.

[0160] Figure 12 (b) shows the returned signal D due to noise Ny. return In the case of switching to an incorrect voltage level, the primary-side transmitter 600 repeatedly generates a pulse current Ip of the first polarity, consuming useless power.

[0161] also, Figure 12 The mismatch of (a) or (b) in the input signal D in It was not eliminated before the transformation.

[0162] In Example 3, a structure that can solve this problem is described. Figure 13 This is a circuit diagram showing the structure of the primary side 502C of the transmission circuit 500C in Embodiment 3.

[0163] In embodiment 3, the primary-side transmitter 600C receives the input signal D. inWith return signal D return After the logic value matches, an additional drive is performed on the primary side input 512 of the insulating layer. That is, the input signal D... in When the signal is high, an additional pulse current Ip is generated, and the input signal D... in When the value is low, an additional pulse current In is generated.

[0164] The primary-side transmitter 600C includes a first oscillation circuit 620C and an oscillator controller 640. The first oscillation circuit 620C is an enabled pulse-output ring oscillator 621, except... Figure 7 In addition to the first oscillation circuit 620, a level-sensitive latch (D latch) 626 is also included. The level-sensitive latch 626 receives a return signal D at input node D. return When the gate (inverting logic) is input with the enable signal ENB, and the enable signal ENB is low, the return signal D is triggered. return pass.

[0165] In addition to the first comparator circuit 610, the oscillator controller 640 also includes a D flip-flop 642 and an OR gate 644. The first comparator circuit 610 determines the input signal D. in and return signal D return Consistency and inconsistency.

[0166] The D flip-flop 642 retains the output of the first comparator circuit 610 from the previous iteration. The OR gate 644 outputs the logical sum of the output of the first comparator circuit 610 and the output of the D flip-flop 642. The input signal D is continuously applied in both loops. in With return signal D return When consistent, the output of OR gate 644 makes the enable signal (negative logic) ENB valid (low).

[0167] Based on this structure, in the input signal D in and return signal D return After the logic values ​​are consistent, by adding another drive to the primary side input 512 of the insulating layer, control pulse D can be continuously generated. idelay until the input signal D in With return signal D return The logical values ​​are generated consecutively twice.

[0168] Figure 14 This is a circuit diagram showing the structure of the secondary side 504C of the transmission circuit 500C in Embodiment 3.

[0169] The spike pulse removal circuit 740C includes a hysteresis trigger 742, a delay circuit 744, an OR gate 746, and a D flip-flop 748, in addition to these. When a voltage signal is generated on the secondary winding Ws of transformer T1, the output of OR gate 746 goes high, and the D flip-flop 748 takes the output value of delay circuit 744. The D flip-flop 748 retains the previous output signal D. out .

[0170] The secondary transmitter 800C of the transmission circuit 500C outputs the signal D at the current output signal D. out0 Compared with the previous output signal D out1 During the period of inconsistency, the secondary side of the repeated insulation layer, namely the secondary winding Ws of transformer T2, is driven.

[0171] The secondary transmitter 800C can be connected with... Figure 7 The primary-side transmitter 600 is similarly configured, including a second comparator circuit 810, a second oscillation circuit 820, and a second output section 830. The second comparator circuit 810 converts the previous output signal D... out1 With the current output signal D out0 The logic values ​​are compared to generate an enable signal ENB representing the comparison result. The second oscillation circuit 820 is an enable pulse output ring oscillator.

[0172] The above describes the structure of the transmission circuit 500C in Example 3. Figure 15 This is a timing diagram showing the operation of the transmission circuit 500C in Embodiment 3.

[0173] According to Embodiment 3, the secondary transmitter 800 returns signal D... return Once the data is transmitted correctly, it stops working and is also tolerant of anomalies in the return channel.

[0174] The embodiments described are merely illustrative. Those skilled in the art should understand that various modifications can be made to the combination of these constituent elements or processing techniques, and such modifications are also within the scope of this invention or this disclosure. The following describes such modifications.

[0175] The structure of the secondary receiver 700 is not limited to Figure 8 In addition, the following variations are also applicable to the primary-side receiver 900.

[0176] (Variation Example 1)

[0177] Figure 16This is a circuit diagram of the secondary-side receiver 700 in Modified Example 1. The switch control unit 720 can be composed of two inverters 722 and 724. The input node of the first inverter 722 is connected to the inverted output QB of the latch circuit 710, and the output node is connected to the gate of the first switch swp. The input node of the second inverter 724 is connected to the output Q of the latch circuit 710, and the output node is connected to the gate of the second switch swn.

[0178] (Variation Example 2)

[0179] Figure 17 This is the circuit diagram of the secondary-side receiver 700 in Variation Example 2. In the above description, the common voltage V... COM It is set as the ground voltage GND2, but is not limited to this. In this variation 2, the common voltage V COM Let the power supply voltage be VDD2. Furthermore, the first switch (swp) and the second switch (swn) are constructed from PMOS transistors.

[0180] Furthermore, in Variation 2, the latch circuit 710 includes a first NAND gate 716 and a second NAND gate 718 connected in a cross configuration. This latch circuit 710 operates with negative logic, and the voltage V at the set terminal SB... RX1 It is set when it transitions from high to low, and the voltage V at the reset terminal RB is... RX2 It is reset when it transitions from high to low.

[0181] The switch control unit 720 includes a third inverter 734 and a fourth inverter 736. The third inverter 734 receives the output D of the latch circuit 710 at the input node. out The output node is connected to the gate of the first switch swp. The fourth inverter 736 receives the inverted output D of the latch circuit 710 at its input node. outb The output node is connected to the gate of the second switch swn.

[0182] Alternatively, the switch control unit 720 can be configured as follows: Figure 8 The 720C switch control unit.

[0183] (Variation Example 3)

[0184] The structures of the secondary receiver 700 and the primary receiver 900 are not limited to the above-described cases, and can be constructed using known technologies.

[0185] (Variation Example 4)

[0186] The structures of the first and second oscillating circuits are not limited to the above-described cases; the order of the constituent elements can be changed, or the positive / negative logic polarity can be altered.

[0187] (Variation Example 5)

[0188] In Examples 1-3, the case where the insulating layer 510 includes two transformers was described, but it is not limited to this and may include a capacitor. In this case, the structure of the primary-side transmitter 600, secondary-side receiver 700, secondary-side transmitter 800, and primary-side receiver 900 can be changed according to known techniques as capacitors. Alternatively, the insulating layer 510 may include a single transformer, through which signals are transmitted and received bidirectionally.

[0189] (use)

[0190] Finally, the purpose of transmission circuit 500 will be explained.

[0191] Figure 18 This is a circuit diagram of an isolation converter 1000 with transmission circuitry 500. Controller 1100 is configured on the secondary side to output voltage V. OUT The pulse signal is generated in a manner close to the target value. The transmission circuit 500 uses the pulse signal Sp generated by the controller 1100 as the input signal D. in The signal is received and transmitted to the primary side of the isolation converter 1000. The gate driver 1200 transmits the signal to the primary side of the transmission circuit 500 via the output signal D. out The corresponding gate signal drives the primary-side switching transistor M1.

[0192] Figure 19 This is a circuit diagram of a half-bridge converter 2000 with transmission circuitry 500. The half-bridge converter 2000 includes a high-side transistor MH and a low-side transistor ML. The gate driver 2002 drives the low-side transistor ML according to a PWM signal.

[0193] The high-side transistor MH is an N-channel transistor. The driving circuit 2004 for the high-side transistor MH uses the voltage V at the connection node between the high-side transistor MH and the switching transistor ML, i.e., the switching node. SW It operates based on a reference (GND2). Furthermore, the power supply voltage (VDD2) for the drive circuit 2004 is generated by the bootstrap circuit.

[0194] The transmission circuit 500 transmits the PWM signal from the region based on the ground voltage GND1 to the region based on the ground voltage GND2 (=Vsw).

[0195] According to the embodiments, the present invention is described using specific statements. However, the embodiments only illustrate the principles and applications of the present invention. Various modifications or configuration changes are allowed for the embodiments without departing from the spirit of the present invention as defined in the claims.

[0196] Industrial availability

[0197] This disclosure can be used in electronic circuits.

[0198] Explanation of reference numerals in the attached figures

[0199] 500 Transmission Circuit

[0200] 510 Insulating layer

[0201] 512 Primary side input

[0202] 514 Secondary Output

[0203] 516 Secondary input

[0204] 518 Primary-side output

[0205] T1 Transformer

[0206] T2 Transformer

[0207] 600 Primary Side Launcher

[0208] 610 First Comparator Circuit

[0209] 612 XOR Gate

[0210] 620 First Oscillator Circuit

[0211] 621 Pulse Output Type Ring Oscillator

[0212] 622 AND Gate

[0213] XOR gates 623 and 624

[0214] 630 First Output Section

[0215] 632, 634 output stages

[0216] 700 secondary receiver

[0217] SWP First Switch

[0218] SWN second switch

[0219] 710 latch circuit

[0220] 720 Switch Control Unit

[0221] 740 Spike Pulse Removal Circuit

[0222] 742 Hysteresis Trigger

[0223] 744 Delay Circuit

[0224] 800 secondary side transmitters

[0225] 810 Second Comparator Circuit

[0226] 820 Second Oscillator Circuit

[0227] 830 Second Output Section

[0228] 840 Pre-Driver

[0229] 900 Primary-side receiver

[0230] Wp primary winding

[0231] Ws secondary winding

[0232] COM common voltage node

Claims

1. A transmission circuit, comprising: Insulating layer, The primary-side transmitter, in response to a change in the input signal, drives the primary-side input of the insulating layer. The secondary-side receiver generates an output signal having a logic value corresponding to the signal generated on the secondary side of the insulating layer. The secondary-side transmitter, based on the output signal, drives the secondary-side input of the insulating layer, and The primary-side receiver generates a return signal having a logic value corresponding to the signal generated at the primary-side output of the insulating layer. The primary-side transmitter repeats the drive of the primary-side input of the insulating layer until the logic values ​​of the input signal and the return signal are consistent. The primary-side transmitter includes: A first comparison circuit compares the input signal with the logic value of the return signal; The first oscillation circuit controls the oscillation and stops it based on the comparison result of the first comparator circuit; and The first output unit drives the primary side input of the insulating layer according to the input signal and the first pulse signal generated by the first oscillation circuit.

2. The transmission circuit according to claim 1, The first oscillation circuit includes a ring oscillator.

3. The transmission circuit according to claim 1 or 2, When the input signal is high, the primary-side transmitter pulses the primary side of the insulating layer with a first polarity, and when the input signal is low, it pulses the primary side of the insulating layer with a second polarity.

4. The transmission circuit according to claim 1, The insulating layer includes a first transformer whose primary winding is connected to the primary-side transmitter and whose secondary winding is connected to the secondary-side receiver. When the input signal is high, the primary-side transmitter supplies a pulse current of a first polarity to the primary winding of the first transformer, and generates a pulse current of a second polarity when the input signal is low.

5. The transmission circuit according to claim 4, The secondary receiver includes: The latching circuit has a set terminal connected to one end of the secondary winding of the first transformer, and a reset terminal connected to the other end of the secondary winding of the transformer. The first switch is positioned between the common voltage node that generates the common voltage and the set terminal, and is turned on when the output of the latch circuit is high; as well as The second switch is located between the common voltage node and the reset terminal, and is turned on when the output of the latch circuit is low.

6. The transmission circuit according to claim 5, The secondary receiver also includes a switch control unit that controls the first switch and the second switch according to the state of the latch circuit. The switch control unit disconnects the second switch after the transition of the pulse current of the first polarity ends, and disconnects the first switch after the transition of the pulse current of the second polarity ends.

7. The transmission circuit according to claim 6, After the first switch is turned on, the switch control unit disconnects the second switch after a predetermined time, and after the second switch is turned on, disconnects the first switch after a predetermined time.

8. The transmission circuit according to any one of claims 1, 2, 4, and 5, After the logic values ​​of the input signal and the return signal are consistent, the primary-side transmitter additionally drives the primary-side input of the insulating layer. The secondary-side transmitter repeats the driving of the secondary-side input of the insulating layer during the period when the current output signal is inconsistent with the previous output signal.

9. The transmission circuit according to claim 8, The secondary transmitter includes: The second comparison circuit compares the previous logic value of the output signal with the current logic value of the output signal. The second oscillation circuit controls the oscillation to stop based on the comparison result of the second comparator circuit. as well as The second output unit drives the secondary side input of the insulating layer according to the second pulse signal generated by the second oscillation circuit during the oscillation of the second oscillation circuit.

10. The transmission circuit according to any one of claims 1, 2, 4, and 5, further comprising: A spike removal circuit that removes glitch signals from the output of the secondary receiver.

11. A transmission circuit, comprising: Insulating layer, The primary-side transmitter, in response to a change in the input signal, drives the primary-side input of the insulating layer. The secondary-side receiver generates an output signal having a logic value corresponding to the signal generated on the secondary side of the insulating layer. The secondary-side transmitter, based on the output signal, drives the secondary-side input of the insulating layer, and The primary-side receiver generates a return signal having a logic value corresponding to the signal generated at the primary-side output of the insulating layer. The primary-side transmitter repeats the drive of the primary-side input of the insulating layer until the logic values ​​of the input signal and the return signal are consistent. The insulating layer includes a first transformer whose primary winding is connected to the primary-side transmitter and whose secondary winding is connected to the secondary-side receiver. The primary-side transmitter supplies a pulse current of a first polarity to the primary winding of the first transformer when the input signal is high, and generates a pulse current of a second polarity when the input signal is low. The secondary receiver includes: The latching circuit has a set terminal connected to one end of the secondary winding of the first transformer, and a reset terminal connected to the other end of the secondary winding of the transformer. A first switch is positioned between the common voltage node that generates the common voltage and the set terminal, and is turned on when the output of the latch circuit is high; and The second switch is located between the common voltage node and the reset terminal, and is turned on when the output of the latch circuit is low.

12. The transmission circuit according to claim 11, The secondary receiver also includes a switch control unit that controls the first switch and the second switch according to the state of the latch circuit. The switch control unit disconnects the second switch after the transition of the pulse current of the first polarity ends, and disconnects the first switch after the transition of the pulse current of the second polarity ends.

13. The transmission circuit according to claim 12, After the first switch is turned on, the switch control unit disconnects the second switch after a predetermined time, and after the second switch is turned on, disconnects the first switch after a predetermined time.

14. The transmission circuit according to claim 11, After the logic values ​​of the input signal and the return signal are consistent, the primary-side transmitter additionally drives the primary-side input of the insulating layer. The secondary-side transmitter repeats the driving of the secondary-side input of the insulating layer during the period when the current output signal is inconsistent with the previous output signal.

15. The transmission circuit according to claim 14, The secondary transmitter includes: The second comparison circuit compares the previous logic value of the output signal with the current logic value of the output signal. The second oscillation circuit controls the oscillation to stop based on the comparison result of the second comparator circuit. as well as The second output unit drives the secondary side input of the insulating layer according to the second pulse signal generated by the second oscillation circuit during the oscillation of the second oscillation circuit.

16. The transmission circuit according to claim 11, further comprising: A spike removal circuit that removes glitch signals from the output of the secondary receiver.

17. A transmission circuit, comprising: Insulating layer, The primary-side transmitter, in response to a change in the input signal, drives the primary-side input of the insulating layer. The secondary-side receiver generates an output signal having a logic value corresponding to the signal generated on the secondary side of the insulating layer. The secondary-side transmitter, based on the output signal, drives the secondary-side input of the insulating layer, and The primary-side receiver generates a return signal having a logic value corresponding to the signal generated at the primary-side output of the insulating layer. The primary-side transmitter repeats the drive of the primary-side input of the insulating layer until the logic values ​​of the input signal and the return signal are consistent. After the logic values ​​of the input signal and the return signal are consistent, the primary-side transmitter additionally drives the primary-side input of the insulating layer. The secondary-side transmitter repeats the driving of the secondary-side input of the insulating layer during periods when the current output signal is inconsistent with the previous output signal. The secondary transmitter includes: The second comparison circuit compares the previous logic value of the output signal with the current logic value of the output signal. The second oscillation circuit controls the oscillation and stops based on the comparison result of the second comparator circuit; and The second output unit drives the secondary side input of the insulating layer according to the second pulse signal generated by the second oscillation circuit during the oscillation of the second oscillation circuit.

18. The transmission circuit according to claim 17, further comprising: A spike removal circuit that removes glitch signals from the output of the secondary receiver.

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