Plastic package cavity structure and manufacturing method thereof

Abstract

The application provides a plastic package cavity structure and a manufacturing method thereof. The plastic package cavity structure comprises an embedded package frame with a first cavity and a first conducting post penetrating through an insulating layer along a height direction; a chip set arranged in the first cavity; a first circuit layer arranged on an upper surface of the embedded package frame; a first dielectric layer arranged on the first circuit layer; a second circuit layer arranged on the first dielectric layer; a through hole penetrating through the first dielectric layer and the insulating layer; a third circuit layer arranged on a lower surface of the embedded package frame; a support column fence wall arranged on the third circuit layer; and a plastic package layer formed along an outer side of the support column fence wall; wherein a second cavity communicating with the through hole is formed between the plastic package layer and the lower surface of the embedded package frame, and the chip set comprises a first chip and a second chip arranged in a back-to-back manner.

Description

Technical Field

[0001] This application relates to the field of electronic device packaging technology, and in particular to a plastic encapsulation cavity structure and its manufacturing method. Background Technology

[0002] MEMS (Micro-Electro-Mechanical Systems) sensors are widely used in the medical, automotive, communications, and computer fields. MEMS sensors include MEMS microphones, MEMS barometers, MEMS thermo-hygrometers, and MEMS gas sensors. The packaging structure mainly includes a packaging substrate, a MEMS sensor chip, an ASIC (Application-Specific Integrated Circuit) chip, a protective shell, and the channel through which the MEMS sensor chip realizes environmental sensing. Current electronic products are trending towards smaller, thinner, and lighter designs, thus creating a demand for miniaturized and high-density integrated MEMS sensor packaging structures.

[0003] Current MEMS sensor and ASIC chip packaging primarily involves mounting the MEMS sensor chip and ASIC chip onto a packaging substrate, electrically connecting them to the substrate via wire bonding, and then attaching a protective shell to protect the packaged device. Through-holes are often pre-drilled in the substrate or protective shell to allow the MEMS sensor chip to interact with the external environment. However, existing plastic cavity packaging structures suffer from several drawbacks: large package volume, failing to meet the demands for miniaturized and lightweight semiconductor packaging; the need for individual protective covers for each sensor unit, resulting in low processing efficiency and high cost; and poor precision in the application of protective covers, which cannot meet the requirements of high-density packaging. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a plastic-sealed cavity structure and its manufacturing method.

[0005] To achieve the above objectives, the method for manufacturing a plastic-sealed cavity structure provided in this application includes the following steps:

[0006] (a) Prepare an embedded encapsulation frame; the embedded encapsulation frame includes a first cavity and a first conductive post that penetrate the insulating layer along the height direction;

[0007] (b) Embedding a chip set at the bottom of the first cavity; the chip set includes a first chip and a second chip stacked together, and the back sides of the first chip and the second chip are attached to each other, such that their terminal faces are opposite to each other;

[0008] (c) An encapsulation layer is formed within the gap between the chipset and the first cavity; the encapsulation layer has blind vias that expose the terminals of the second chip;

[0009] (d) A first circuit layer and a second conductive post are formed on the upper surface of the embedded packaging frame, wherein the first circuit layer is conductively connected to the terminal of the second chip;

[0010] (e) A first dielectric layer is laminated on the upper surface of the first circuit layer; wherein the upper surface of the first dielectric layer is flush with the upper surface of the second conductive post;

[0011] (f) A second circuit layer is formed on the upper surface of the first dielectric layer, a third circuit layer is formed on the lower surface of the embedded encapsulation frame, and a support column wall surrounding the first cavity is formed on the third circuit layer.

[0012] (g) A through-hole is formed that penetrates the first dielectric layer and the insulating layer sequentially along the height direction, wherein the through-hole is surrounded by the aforementioned support column wall;

[0013] (h) A molding layer is formed below the embedded encapsulation frame along the outside of the support column enclosure, and a second cavity is formed between the molding layer and the embedded encapsulation frame.

[0014] 10. This application also provides a plastic encapsulation cavity structure, comprising an embedded encapsulation frame having a first cavity and a first conductive post penetrating an insulating layer along the height direction; a chipset disposed within the first cavity; a first circuit layer disposed on the upper surface of the embedded encapsulation frame; a first dielectric layer disposed on the first circuit layer; a second circuit layer disposed on the first dielectric layer; a through-hole penetrating the first dielectric layer and the insulating layer; a third circuit layer on the lower surface of the embedded encapsulation frame; a support post wall on the third circuit layer; and a plastic encapsulation layer formed along the outer side of the support post wall.

[0015] A second cavity communicating with the through hole is formed between the molding layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip stacked back to back.

[0016] As can be seen from the above, the plastic encapsulation cavity structure provided in this application embeds a chip group consisting of a first chip and a second chip stacked in the packaging substrate. Electrical connection with the packaging substrate is achieved through blind holes in the packaging layer. Copper pillar walls are processed on the top (i.e., the lower surface) of the embedded packaging substrate. After encapsulation, a second cavity can be formed. Sensing with the external environment is achieved through the second cavity and through holes. It can achieve high-density integrated packaging, has high precision, and has the advantages of miniaturized packaging volume and high packaging efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The diagram illustrates the mainstream packaging structure of MEMS sensors and ASIC chips in the prior art.

[0019] Figure 2 A cross-sectional view of the encapsulated cavity structure provided in an embodiment of this application is shown;

[0020] Figures 3a-3i A cross-sectional schematic diagram of the intermediate structure of each step in the manufacturing method of the encapsulated cavity structure according to an embodiment of this application is shown. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0022] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] Figure 1 The diagram shows the mainstream packaging structure of MEMS sensors and ASIC chips in the prior art.

[0024] like Figure 1 As shown, in some mainstream packaging methods for MEMS sensors and ASIC chips, for multiple units formed by the electrical connection of MEMS sensing chips and ASIC chips with the packaging substrate through bonding wires, it is necessary to apply a protective cover to each unit individually to protect it and form a cavity, thereby achieving packaging.

[0025] It is evident that the current packaging methods for MEMS sensors and ASIC chips require applying a protective shield to each unit individually, which results in low processing efficiency and high costs. Furthermore, the method of applying a protective shield suffers from poor processing precision, failing to meet the development needs of high-density packaging, and also results in large package sizes, failing to meet the development needs of small, thin, and lightweight semiconductor packaging.

[0026] Based on this, the embodiments of this application provide a method for manufacturing a plastic encapsulation cavity structure. By processing copper pillar walls on the top of the embedded packaging substrate, a plastic encapsulation cavity can be formed after encapsulation. This method can solve, to some extent, the problems of existing plastic encapsulation cavity structures, such as the need to apply a protective cover to each unit individually, resulting in low processing efficiency and high cost; poor processing precision, which cannot meet the development needs of high-density packaging; and large packaging volume, which cannot meet the development needs of small and thin semiconductor packaging.

[0027] Figure 2 A cross-sectional view of the encapsulated cavity structure provided in an embodiment of this application is shown.

[0028] like Figure 2 As shown, the plastic encapsulation cavity structure provided in this application embodiment may include an embedded encapsulation frame, a chipset embedded within the embedded encapsulation frame, and a plastic encapsulation layer 300 surrounding the lower surface of the embedded encapsulation frame. The chipset includes a first chip 210 and a second chip 220 stacked together, with the terminals of the first chip 210 and the second chip 220 arranged opposite to each other.

[0029] The encapsulated cavity structure includes a first cavity and a first conductive post 102 that penetrate the insulating layer forming the embedded package frame along the height direction. A chipset is disposed within the first cavity, and the structure also includes an encapsulation layer 400 disposed in the gap between the chipset and the first cavity; a first circuit layer 500 and a second conductive post 600 disposed on the upper surface of the embedded package frame; a first dielectric layer 700 and a second circuit layer 800 disposed on the first circuit layer 500; and a through-hole 103 that sequentially penetrates the first dielectric layer 700 and the insulating layer of the embedded package frame.

[0030] It also includes a third circuit layer disposed on the lower surface of the embedded packaging frame and a support pillar enclosure 310 disposed around the lower surface of the embedded packaging frame; wherein, the third circuit layer may include a functional circuit layer 910 and a circuit enclosure 920, and the support pillar enclosure 310 may be disposed on the circuit enclosure 920. That is, the support pillar enclosure is disposed on the third circuit layer. A passive element 250 is disposed on the lower surface of the third circuit layer; a molding compound 300 is disposed on the lower surface of the embedded packaging frame and on the outside of the third circuit layer and the support pillar enclosure 310; that is, the molding compound 300 is formed along the outside of the support pillar enclosure. The molding compound 300 and the lower surface of the embedded packaging frame have a second cavity 340 communicating with the through hole 103.

[0031] It should be understood that multiple chipsets can be configured, depending on the specific needs. Correspondingly, multiple first cavities can be configured, each used to embed multiple chipsets. The second cavity 340 formed between the molding layer 300 and the lower surface of the packaging substrate can cover all chipsets, thereby achieving a high-density integrated package.

[0032] The plastic encapsulation cavity structure provided in this application embodiment is formed by stacking and embedding a chip group consisting of a first chip 210 and a second chip 220 inside a packaging substrate. Electrical connection with the packaging substrate is achieved through blind holes in the packaging layer 400. Copper pillar walls are processed on the top (i.e., the lower surface) of the embedded packaging substrate to form a plastic encapsulation cavity after encapsulation. It can achieve high-density integrated packaging, has high precision, and has the advantages of miniaturized packaging volume and high packaging efficiency.

[0033] In some embodiments, the embedded encapsulation frame is a polymer frame. The frame may be made of a polymer used as a polymer sheet or of a glass fiber reinforced polymer used as a prepreg. It may have one or more layers.

[0034] The conductive pillars mentioned in this embodiment (e.g., the first conductive pillar 102 or the second conductive pillar 600) may include at least one copper via pillar as an I / O channel to achieve inter-layer conductivity. The size and / or shape of the multiple conductive pillars may be the same or different. The conductive pillars may be solid copper pillars or hollow pillars with copper plating on the surface; preferably, the conductive pillars include multiple copper via pillars as I / O channels, and the ends of the conductive pillars may be flush with the encapsulation layer.

[0035] In the chipset, the first chip 210 can be a sensing chip (e.g., a MEMS sensing chip), having multiple terminals 211 and a sensing component 212. The terminal surfaces of the first chip 210 are mounted on the bottom of the first cavity. The surface of the sensing component 212 is exposed, meaning it is not covered by the third wiring layer. In other words, the surface of the sensing component of the first chip is exposed to the second cavity and communicates with the outside world through the via. Thus, the sensing chip can sense external environmental loads through the second cavity 340 and the via 103, and then output an electrical signal to the second chip 220.

[0036] The second chip 220 and the first chip 210 can be connected via an adhesive material 230. The size (e.g., length) of the second chip 220 can be smaller than that of the first chip 210 and the adhesive material 230, while the size of the adhesive material 230 can be the same as that of the first chip 210. The viscosity of the adhesive material 230 can be greater than that of the encapsulation layer 400, thus avoiding damage to the chip when the encapsulation layer 400 is too rigid and is pressed against the adhesive material 230. The second chip 220 can be an ASIC chip, which can amplify and modulate the electrical signals output by the MEMS chip into the required standard output signal.

[0037] In some embodiments, a second dielectric layer 350 is further included, disposed between the molding layer 300 and the third wiring layer and the support column enclosure 310. That is, a second dielectric layer is also included between the molding layer 300 and the second cavity. The second dielectric layer 350 can be a molding film. The molding film can be a polytetrafluoroethylene (PTFE) film or a polyimide (PI) film, etc. In this way, the molding layer 300 can be better molded using the molding film, and stress can be released efficiently.

[0038] In some embodiments, the support column enclosure 310 can be a copper support column enclosure, which can provide support while also dissipating heat. Taking the surface where the embedded encapsulation frame is located as a reference surface, the orthographic projection of the support column enclosure 310 on the reference surface partially overlaps with the orthographic projection of the circuit enclosure 920 on the reference surface.

[0039] In some embodiments, a second metal seed layer may be provided between the embedded packaging frame and the first circuit layer 500, and a first metal seed layer may also be provided between the embedded packaging frame and the third circuit layer. This can improve the stability and reliability of the conductive connection between the first conductive post 102 and the first circuit layer 500, and also improve the stability and reliability of the conductive connection between the first conductive post 102 and the third circuit layer.

[0040] In some embodiments, a third metal seed layer may be provided between the first dielectric layer 700 and the second circuit layer 800. This can improve the stability and reliability of the conductive connection between the second conductive post 600 and the first circuit layer 500 and the second circuit layer 800.

[0041] Reference Figures 3a-3i This diagram shows a cross-sectional schematic of the intermediate structure of each step in the manufacturing method of the encapsulated cavity structure according to an embodiment of this application.

[0042] The manufacturing method includes the following steps: preparing an embedded packaging frame 100, wherein the embedded packaging frame 100 includes a first cavity 101 and a first conductive post 102 that penetrate the embedded packaging frame along the height direction - step (a), as shown Figure 3a .

[0043] Typically, multiple first cavities 101 can be provided for subsequent chip assembly. The dimensions of the multiple first cavities 101 can be the same or different, depending on the shape and size of the chip assembly to be embedded, and are not limited here. The embedded packaging frame 100 can be made of a polymer used as a polymer sheet or a glass fiber reinforced polymer used as a prepreg. It may have one or more layers.

[0044] Typically, the embedded packaging frame 100 can be manufactured using Zhuhai Yueya's through-hole pillar technology, involving pattern plating or panel plating followed by selective etching to create conductive pillars from the through holes. This is then laminated using dielectric materials such as polymer films or, for added stability, preforms composed of woven glass fiber bundles within a polymer matrix. In one embodiment, the dielectric material is Hitachi 705G. In another embodiment, MGC832 NXA NSFLCA is used. In a third embodiment, Sumitomo GT-K can be used. In another embodiment, Sumitomo LAZ-4785 series films are used. In yet another embodiment, Sumitomo LAZ-6785 series films are used. Alternative materials include Taiyo's HBI and Zaristo-125 or Ajinomoto's ABF GX material series.

[0045] Manufacturing through-hole pillars, rather than drill-fill techniques, offers numerous advantages. In through-hole pillars, all through-holes can be manufactured simultaneously, whereas drill-fill techniques require individual drilling. Furthermore, drilled through-holes are cylindrical, while through-hole pillars can have any shape. In practice, all drill-filled through-holes have the same dimensions (within tolerances), whereas through-hole pillars can have different shapes and sizes. Moreover, for increased strength, the polymer matrix is ​​preferably fiber-reinforced, typically using glass fiber woven bundles. When a fiber-containing preform of the polymer is laid on an upright through-hole pillar and cured, the pillar is characterized by smooth, vertical sides. However, when drilling into composite materials, drill-filled through-holes are typically angled; they typically have rough surfaces that introduce stray inductance, leading to noise.

[0046] Typically, the first conductive post 102 has a width ranging from 25 micrometers to 500 micrometers. If it is a cylindrical shape, as required by drilling and filling and as is common in conductive posts, each conductive post may have a diameter ranging from 25 micrometers to 500 micrometers.

[0047] Next, the chipset is embedded in the bottom of the first cavity 101 - step (b), as follows Figure 3b .

[0048] Typically, embedding the chip assembly at the bottom of the first cavity 101 in step (b) includes:

[0049] (b1) An adhesive layer 240 is applied to the lower surface of the embedded packaging frame 100. Typically, the adhesive layer 240 can be a single-sided tape, which is usually a commercially available transparent film that is thermally degradable or degradable under ultraviolet light; the adhesive layer 240 can provide temporary support and fixation for the chipset.

[0050] (b2) The terminal face of the second chip 220 of the chipset is attached to the adhesive layer 240 exposed within the first cavity 101 to mount the chipset at the bottom of the first cavity 101. The chipset includes a first chip 210 and a second chip 220 stacked together, with the terminal faces of the first chip 210 and the second chip 220 facing away from each other, and the terminal face of the first chip 210 is mounted at the bottom of the first cavity. Typically, the height of the chipset can be less than the height of the first cavity, allowing for the formation of an encapsulation layer 400 on the chipset through subsequent processes. This encapsulation layer can absorb the load applied to the chipset during the fabrication of other layered structures on the surface of the embedded encapsulation frame, thus preventing damage to the chipset. Typically, the back faces of the first chip 210 and the second chip 220 can be bonded together using an adhesive material 230.

[0051] Then, an encapsulation layer 400 is formed within the gap between the chipset and the first cavity 101 – step (c), as follows. Figure 3d As shown. Typically, this step may include:

[0052] (c1) An encapsulation layer 400 is formed within the gap between the chipset and the first cavity 101 and on the upper surface of the embedded support frame 100, such as... Figure 3c Typically, the encapsulation layer 400 can be selected from pure resin.

[0053] (c2) Thinning the encapsulation layer 400 exposes the upper surface of the first conductive post 102 of the embedded support frame 100 and the upper surface of the embedded encapsulation frame 100, making the upper surface of the encapsulation layer 400 flush with the upper surface of the first conductive post 102 and the upper surface of the embedded encapsulation frame 100. This ensures good flatness of the upper surface of the embedded encapsulation frame 100, avoiding difficulties in layer addition and conduction caused by device fluctuations, and facilitating subsequent fabrication of the first circuit layer 500, etc., on the upper surface of the embedded encapsulation frame 100. Typically, the encapsulation material can be thinned using methods such as grinding or plasma etching.

[0054] (c3) A window is made in the terminals of the second chip 220 to form a blind via 410 on the packaging layer 400. Typically, the blind via 410 is connected to the terminals 221 of the second chip 220 to facilitate electrical connection between the second chip 220 and subsequently fabricated first circuit layer 500, etc. This allows for high integration and stability of the electrical connection between the chipset and the packaging substrate. Typically, the blind via 410 is formed by making a window in the terminals of the second chip 220 using methods such as laser drilling.

[0055] Next, a first circuit layer 500 and a second conductive post 600 are formed on the upper surface of the embedded packaging frame 100 – step (d), as follows. Figure 3e As shown. Typically, step (d) includes:

[0056] (d1) A second metal seed layer is formed on the upper surface of the embedded packaging frame 100 and on the bottom and sidewalls of the blind via 410; typically, the second metal seed layer can be formed by a sputtering process. The material of the second metal seed layer is not specifically limited and can be determined according to actual needs, typically titanium and copper.

[0057] (d2) Apply a third photoresist layer on the second metal seed layer, and expose and develop the third photoresist layer to form a third feature pattern;

[0058] (d3) A first circuit layer 500 is formed by electroplating in the third feature pattern. Typically, the first circuit layer 500 is connected to the terminal surface of the second chip 220;

[0059] (d4) Remove the third photoresist layer, apply a fourth photoresist layer on the second metal seed layer, and expose and develop the fourth photoresist layer to form a fourth feature pattern;

[0060] (d5) A second conductive post 600 is formed by electroplating in the fourth feature pattern; typically, the second conductive post 600 is provided corresponding to the first conductive post 102;

[0061] (d6) Remove the third and fourth photoresist layers and etch the exposed second metal seed layer.

[0062] Then, a first dielectric layer 700 is laminated onto the upper surface of the first circuit layer 500 – step (e), as follows. Figure 3f Typically, step (e) includes:

[0063] A first dielectric material is laminated onto the upper surface of the first circuit layer 500. Typically, the height of the first dielectric material exceeds the height of the second conductive post 600. This allows the second conductive post 600 to be exposed through subsequent thinning, facilitating the flush alignment of the end face of the second conductive post 600 with the first dielectric layer 700 and simplifying subsequent layered structure fabrication.

[0064] Thinning the first dielectric material exposes the upper surface (end face) of the second conductive post 600, forming a first dielectric layer 700 with its upper surface flush with the upper surface of the conductive post. Typically, the first dielectric material can be thinned using methods such as grinding or plasma etching.

[0065] Next, a second circuit layer 800 is formed on the upper surface of the first dielectric layer 700, and a third circuit layer and a support column enclosure 310 surrounding the embedded encapsulation frame are formed on the lower surface of the embedded encapsulation frame – step (f), as follows. Figure 3g Typically, step (f) of forming a second circuit layer 800 on the upper surface of the first dielectric layer 700 includes:

[0066] (f1) A third metal seed layer is formed on the upper surface of the first dielectric layer 700; typically, the third metal seed layer can be formed by a sputtering process. The material of the third metal seed layer is not specifically limited and can be determined according to actual needs; it can typically be titanium or copper.

[0067] (f2) Apply a fifth photoresist layer to the third metal seed layer, and expose and develop the fifth photoresist layer to form a fifth feature pattern;

[0068] (f3) A second circuit layer 800 is formed by electroplating in the fifth feature pattern; the second circuit layer 800 is connected to the first circuit layer 500 through the second conductive post 600;

[0069] (f4) Remove the fifth photoresist layer and etch the exposed third metal seed layer.

[0070] Typically, in step (f), forming a third circuit layer on the lower surface of the embedded encapsulation frame and a support column enclosure 310 surrounding the embedded encapsulation frame includes:

[0071] (f5) Remove the adhesive layer 240 applied to the lower surface of the embedded encapsulation frame;

[0072] (f6) A first metal seed layer is formed on the lower surface of the embedded packaging frame; typically, the first metal seed layer can be formed by a sputtering process. The material of the first metal seed layer is not specifically limited and can be determined according to actual needs; it is usually titanium or copper.

[0073] (f7) Apply a first photoresist layer on the first metal seed layer, and expose and develop the first photoresist layer to form a first feature pattern;

[0074] (f8) A third circuit layer is formed by electroplating in the first feature pattern; the third circuit layer may include a functional circuit layer 910 and a circuit wall 920, and a support column wall 310 may be correspondingly disposed on the circuit wall 920; wherein, the surface of the sensing component 212 of the first chip 210 is exposed, that is, the surface of the sensing component is not covered by the third circuit layer.

[0075] (f9) Remove the first photoresist layer, apply a second photoresist layer on the first metal seed layer, and expose and develop the second photoresist layer to form a second feature pattern;

[0076] (f 10 In the second feature pattern, the supporting column wall 310 is formed by electroplating, as shown below. Figure 3h Typically, the support column enclosure 310 can be a copper support column enclosure 310, which can provide support while also dissipating heat. Taking the surface where the embedded packaging frame is located as a reference surface, the orthographic projection of the support column enclosure 310 on the reference surface partially overlaps with the orthographic projection of the circuit enclosure 920 on the reference surface.

[0077] (f 11 Remove the second photoresist layer and etch the exposed first metal seed layer.

[0078] Then, through-holes 103 are formed sequentially through the first dielectric layer 700 and the embedded packaging frame along the height direction, forming a first packaging structure with the chipset and a second packaging structure without the chipset - step (g), as follows. Figure 3iA through-hole 103 can usually be formed by mechanical drilling or other means. Through this through-hole 103, the first chip 210 (i.e., the sensor chip) can sense the external environmental load and then output an electrical signal to the second chip 220.

[0079] Next, the passive component 250 is mounted on the lower surface of the second encapsulation structure; a molding compound 300 is formed on the lower surface of the embedded encapsulation frame and on the outer side of the circuit enclosure 920 and the support post enclosure 310 – step (h), as follows. Figure 2 Typically, the passive component 250 can be mounted on the lower surface of the functional circuit layer 910 in the third circuit layer.

[0080] Typically, forming a molding compound 300 on the lower surface of the embedded encapsulation frame and on the outer side of the line enclosure 920 and the support post enclosure 310 includes:

[0081] A second dielectric layer 350 is laminated on the lower surface of the embedded packaging frame and on the outer side of the circuit enclosure 920 and the support pillar enclosure 310 to form a second cavity 340 for accommodating the passive component 250. In this way, the first chip 210 (i.e., the MEMS sensing chip) in the chipset can sense external environmental loads through the second cavity 340 and the through-hole 103, and then output an electrical signal to the second chip 220 (i.e., the ASIC chip). The ASIC chip amplifies and modulates the electrical signal output by the MEMS chip into the required standard output signal. Typically, the second dielectric layer 350 can be a molding compound. Using a molding compound provides protection and isolation, and also gives the molding compound 300 high transparency and smoothness, as well as temperature resistance, weather resistance, and antistatic properties.

[0082] A sealing layer 300 is laminated onto the surface of the second dielectric layer 350.

[0083] The plastic-encapsulated cavity structure and its fabrication method provided in this application achieve high-density integrated packaging by stacking and embedding a MEMS sensor chip and an ASIC chip inside a packaging substrate. Copper pillars are fabricated on the top of the embedded packaging substrate to form a plastic-encapsulated cavity after packaging. The sensing portion of the MEMS sensor chip is exposed, and sensing with the external environment is achieved through the plastic-encapsulated cavity structure and through-holes in the substrate. This solves the technical problems of low efficiency, high cost, poor precision, and inability to miniaturize the packaging size in existing technologies. It offers advantages such as enabling high-density integrated packaging of MEMS sensor chips and ASIC chips; improving processing efficiency and reducing costs through panel-level processing of the plastic-encapsulated cavity structure; and achieving higher processing precision compared to cavities formed by protective covers, by setting copper pillars, pressing a molding film, and encapsulating the plastic-encapsulated cavity, thus meeting the requirements of high-density integrated packaging.

[0084] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0085] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0086] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a plastic-sealed cavity structure, characterized in that, Includes the following steps: (a) Prepare an embedded encapsulation frame; the embedded encapsulation frame includes a first cavity and a first conductive post that penetrate the insulating layer along the height direction; (b) Embedding a chip set at the bottom of the first cavity; the chip set includes a first chip and a second chip stacked together, and the back sides of the first chip and the second chip are attached to each other, such that their terminal faces are opposite to each other; (c) An encapsulation layer is formed in the gap between the chipset and the first cavity; The encapsulation layer has blind vias that expose the terminals of the second chip; (d) A first circuit layer and a second conductive post are formed on the upper surface of the embedded packaging frame, wherein the first circuit layer is conductively connected to the terminal of the second chip; (e) A first dielectric layer is laminated on the upper surface of the first circuit layer; wherein the upper surface of the first dielectric layer is flush with the upper surface of the second conductive post; (f) A second circuit layer is formed on the upper surface of the first dielectric layer, a third circuit layer is formed on the lower surface of the embedded encapsulation frame, and a support column wall surrounding the first cavity is formed on the third circuit layer. (g) A through-hole is formed that penetrates the first dielectric layer and the insulating layer sequentially along the height direction, wherein the through-hole is surrounded by the aforementioned support column wall; (h) A molding layer is formed below the embedded encapsulation frame along the outside of the support column enclosure, and a second cavity is formed between the molding layer and the embedded encapsulation frame.

2. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, Step (h) also includes: A second dielectric layer is applied below the embedded encapsulation frame along the outer side of the support column enclosure to form the second cavity; The encapsulation layer is laminated on the second dielectric layer.

3. The method for manufacturing a plastic-sealed cavity structure according to claim 2, characterized in that, The second dielectric layer is a coating film.

4. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, The first chip is a sensor chip, wherein the surface of the sensing component of the first chip is exposed to the second cavity and communicates with the outside through the through hole.

5. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, The third circuit layer includes a functional circuit layer and a circuit enclosure, with the support column enclosure electroplated onto the circuit enclosure.

6. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, The supporting column wall is a copper column wall.

7. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, Step (f) also includes: A first metal seed layer is formed on the lower surface of the embedded packaging frame; A first photoresist layer is applied to the first metal seed layer, and the first photoresist layer is exposed and developed to form a first feature pattern. A third circuit layer is formed by electroplating in the first feature pattern; Remove the first photoresist layer, apply a second photoresist layer on the first metal seed layer, and expose and develop the second photoresist layer to form a second feature pattern; Electroplating is used to form a supporting column wall in the second feature pattern; Remove the second photoresist layer and etch the exposed first metal seed layer.

8. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, Step (b) includes: An adhesive layer is applied to the lower surface of the embedded encapsulation frame; The terminal face of the first chip is attached to the adhesive layer exposed inside the first cavity, and the back face of the second chip is attached to the back face of the first chip to mount the chip set at the bottom of the first cavity.

9. The method for manufacturing a plastic-sealed cavity structure according to claim 1, characterized in that, Step (c) also includes: An encapsulation layer is formed in the gap between the chipset and the first cavity and on the upper surface of the embedded support frame; Thinning the encapsulation layer exposes the conductive posts of the embedded support frame; A blind via is formed by opening a window in the encapsulation layer to expose the terminals of the second chip.

10. A plastic-sealed cavity structure, characterized in that, include: An embedded packaging frame having a first cavity and a first conductive post that respectively penetrate an insulating layer along the height direction; a chipset disposed within the first cavity; A first circuit layer disposed on the upper surface of the embedded encapsulation frame; a first dielectric layer disposed on the first circuit layer; a second circuit layer disposed on the first dielectric layer; a through-hole penetrating the first dielectric layer and the insulating layer; a third circuit layer disposed on the lower surface of the embedded encapsulation frame; a support column wall on the third circuit layer; and a molding layer formed along the outer side of the support column wall. A second cavity communicating with the through hole is formed between the molding layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip stacked back to back.

11. The encapsulated cavity structure according to claim 10, characterized in that, The first chip is a sensing chip, wherein the surface of the sensing component of the first chip is exposed in the second cavity and communicates with the outside through the through hole.

12. The encapsulated cavity structure according to claim 10, characterized in that, A second dielectric layer is also included between the molding layer and the second cavity.

13. The encapsulated cavity structure according to claim 12, characterized in that, The second dielectric layer is a coating film.

14. The encapsulated cavity structure according to claim 10, characterized in that, The first chip is selected from MEMS sensor chips, and the second chip is selected from ASIC chips.

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