A novel FPGA-based dynamically configurable scan chain circuit testing system and method

Abstract

The present invention relates to the field of integrated circuit testing technology, and more particularly to a novel FPGA-based dynamically configurable scan chain circuit testing system and method. The testing system is integrated on an FPGA chip and comprises a scan chain configuration unit, a sequence generation unit, a sequence sampling unit, a sequence decoding unit, a configurable sequence comparison unit, an error counter, a state controller, an AXI bus controller, and a configurable frequency divider. The scan chain configuration unit comprises information about the scan chain generation sequence, expected result output information, the number of scan chain channels, scan chain channel enable information, and frequency division coefficient information, all of which are input to the sequence generation unit. The present invention solves the current problem of over-specialization and singularization of integrated circuit scan chain testing equipment, and also addresses the problems of low reusability, redundant design, and incompatibility and expansion difficulties associated with other FPGA-based scan chain test designs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a novel FPGA-based dynamically configurable scan chain circuit testing system and method. Background Art

[0002] The manufacturing process of modern integrated circuits is becoming more and more advanced, but the manufacturing defects in the production process are becoming more and more difficult to control. Even a small PM2.5 may cause the chip to be scrapped. In order to effectively detect the waste chips in production, scan chain testing is required.

[0003] Scan chain testing is a testability design implementation technique that allows testers to externally control and observe the signal values ​​of triggers within the circuit by implanting shift registers.

[0004] Scan chain testing, a key method for testing digital integrated circuits, can effectively screen out defective chips and improve product quality. We chose an FPGA-based, dynamically configurable scan chain circuit testing method because FPGA-based test application platforms offer high system performance, flexibility, and low cost, making them more versatile for product development. Summary of the Invention

[0005] In response to the shortcomings of the existing technology, the present invention discloses a novel FPGA-based dynamically configurable scan chain circuit testing system and method. The present invention solves the problems of over-specialization and singleness of equipment in current integrated circuit scan chain testing. It also solves the problems of low reusability, design duplication and redundancy, and poor compatibility and expansion in other FPGA-based scan chain test designs.

[0006] The present invention is achieved through the following technical solutions:

[0007] A novel FPGA-based dynamically configurable scan chain circuit test system includes:

[0008] The scan chain configuration unit receives the configuration information of the AXI bus controller, configures and caches the enable of the scan chain channel, the sequence of the sequence generation unit, the configurable frequency divider according to the configuration information and the configuration information of the configurable sequence comparison unit;

[0009] The sequence generation unit encodes and serializes the sequence of the scan chain according to the information in the configuration unit and the enabled channel information, and outputs the matching channel;

[0010] A sequence sampling unit receives a return sequence in a scan chain test and sends the sampled sequence to a sequence decoding unit for sequence decoding;

[0011] a sequence decoding unit, receiving the sequence from the sequence sampling unit, decoding the sequence in parallel, sending the decoded sequence to the configurable sequence comparison unit, and sending the decoded sequence to the configurable sequence comparison unit;

[0012] A configurable sequence comparison unit receives sequence information of expected results from the configuration information of the scan chain of the bus, waits for the decoding sequence sent by the sequence decoding unit, compares the sequence information with the configurable expected result sequence information, and sends the comparison result to the error counter and the state controller;

[0013] The error counter receives the comparison results from the configurable sequence comparison unit, performs statistics on the comparison results, and sends the statistics of the total number of tests, the total number of errors and the error information to the state controller in real time;

[0014] The state controller receives information from the error counter and feeds back the operating status information of the configurable scan chain, and accesses various information of the configured scan chain in real time through the AXI bus;

[0015] The AXI bus controller is responsible for connecting the state controller, scan chain configuration unit and external communications, and opening access to the external interface state controller and scan chain configuration unit;

[0016] The configurable frequency divider is responsible for the pulse width of the scan chain output sequence and the configurability of the overall operating frequency, and can achieve a frequency division of 10-1000 according to the frequency of the input system clock.

[0017] Preferably, the scan chain configuration unit includes the generation sequence information of the scan chain configured by the AXI bus, the expected result output information, the number of scan chain channels, the scan chain channel enable, and the frequency division coefficient information, which are respectively used as the input of the sequence generation unit, and other modules include the enable input of each channel of the scan chain and the input of the configurable divider.

[0018] Preferably, the sequence generation unit includes the enable of the scan chain channel, the sequence parallel-serial conversion submodule, and the sequence channel output. The scan chain generation unit clock comes from the output clock of the configurable frequency divider. The enable of the scan chain channel determines which channels are enabled to output the sequence after the parallel sequence is serialized.

[0019] Preferably, the sequence sampling unit downsamples the output clock from the configurable frequency divider, samples the scan chain data input from the external interface, and sends the sampled serialized sequence to the sequence decoding unit.

[0020] Preferably, the sequence decoding unit includes a submodule for parallelizing the serial sequence, and sends the parallelized sequence data to a configurable sequence comparison unit for sequence comparison.

[0021] Preferably, the error counter includes receiving comparison results from a configurable sequence comparison unit, performing statistics on the comparison results, counting the total number of tests, the total number of errors, error information, and completion status information of a run, and sending such information to the state controller in real time.

[0022] Preferably, the state controller includes scan chain operation state information, operation completion state information, total number of scan chain tests, number of scan chain errors, and scan chain error information, and these information are externally accessed via the AXI bus.

[0023] The present invention also provides the following technical solution: a novel FPGA-based dynamic configuration scan chain circuit testing method, comprising the following steps:

[0024] S1: The original stimulus of the scan chain of the integrated circuit to be tested, the scan chain operating frequency, the expected output result of the scan chain, the number of scan chain channels, and the channel enable information are sent to the scan chain configuration unit through the AXI bus in a parallel encoding manner;

[0025] S2: The scan chain configuration unit configures the scan chain and reads the scan chain status information in the state controller through the open AXI bus interface. According to the requirements, it reads the scan chain operation status information, the operation completion status information, the total number of scan chain tests, the number of scan chain errors, and the scan chain error information;

[0026] S3: The read result does not affect the real-time operation of the scan chain. When the scan chain test needs to be stopped, the stop enable information is input to the scan chain configuration unit through the AXI bus.

[0027] The present invention has the following beneficial effects:

[0028] 1) Scan chain parameter configuration can be dynamically configured and tested in real time, with high speed and low price.

[0029] 2) Open AXI bus configuration access, simple dynamic configuration, strong operability, good compatibility and high reuse rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1This is the overall block diagram of the FPGA-based dynamically configurable scan chain circuit testing system of the present invention.

[0032] Figure 2 This is a flow chart of the FPGA-based dynamically configurable scan chain circuit testing method of the present invention. DETAILED DESCRIPTION

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] like Figure 1 As shown, a new FPGA-based dynamically configurable scan chain circuit test system is integrated on the FPGA chip and includes a scan chain configuration unit, a sequence generation unit, a sequence sampling unit, a sequence decoding unit, a configurable sequence comparison unit, an error counter, a state controller, an AXI bus controller, and a configurable frequency divider.

[0035] The scan chain configuration unit contains the scan chain generation sequence information, expected result output information, number of scan chain channels, scan chain channel enable, and frequency division coefficient information configured by the AXI bus. They are used as inputs to the sequence generation unit, and other modules contain the enable inputs of each scan chain channel and the inputs of the configurable divider.

[0036] The sequence generation unit includes the enable of the scan chain channel, the sequence parallel-serial conversion submodule, and the sequence channel output. The scan chain generation unit clock comes from the output clock of the configurable divider. The enable of the scan chain channel determines which channels are enabled to output the sequence after the parallel sequence is serialized.

[0037] The sequence sampling unit downsamples the output clock from the configurable frequency divider, samples the scan chain data input from the external interface, and sends the sampled serial sequence to the sequence decoding unit.

[0038] The sequence decoding unit includes a submodule for parallelizing the serial sequence and sends the parallelized sequence data to the configurable sequence comparison unit for sequence comparison.

[0039] The error counter receives the comparison results from the configurable sequence comparison unit, counts the comparison results, counts the total number of tests, the total number of errors, error information and the completion status information of one run, and sends such information to the state controller in real time.

[0040] The state controller includes scan chain operation status information, operation completion status information, total number of scan chain tests, number of scan chain errors, and scan chain error information. This information can be accessed externally through the AXI bus.

[0041] The configurable frequency divider is responsible for the pulse width of the scan chain output sequence and the configurability of the overall operating frequency. Depending on the frequency of the input system clock, a frequency division of 10-1000 can be achieved.

[0042] The AXI bus controller is responsible for connecting the state controller, the scan chain configuration unit and the external communication, and opening the access to the external interface state controller and the scan chain configuration unit.

[0043] like Figure 2 As shown, a novel FPGA-based dynamic configuration scan chain circuit testing method includes:

[0044] S1: The original stimulus of the scan chain of the integrated circuit to be tested, the scan chain operating frequency, the expected output result of the scan chain, the number of scan chain channels, and the channel enable information are sent to the scan chain configuration unit through the AXI bus in a parallel encoding manner.

[0045] S2: The scan chain configuration unit configures the scan chain and reads the scan chain status information in the state controller through the open AXI bus interface. It can read the scan chain operation status information, operation completion status information, total number of scan chain tests, number of scan chain errors, and scan chain error information as needed.

[0046] S3: The read result does not affect the real-time operation of the scan chain. When the scan chain test needs to be stopped, the stop enable information is input to the scan chain configuration unit through the AXI bus.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A novel FPGA-based dynamically configurable scan chain circuit test system, characterized in that: include: The scan chain configuration unit receives the configuration information of the AXI bus controller, configures and caches the enable of the scan chain channel, the sequence of the sequence generation unit, the configurable frequency divider according to the configuration information and the configuration information of the configurable sequence comparison unit; The sequence generation unit encodes and serializes the sequence of the scan chain according to the information in the configuration unit and the enabled channel information, and outputs the matching channel; A sequence sampling unit receives a return sequence in a scan chain test and sends the sampled sequence to a sequence decoding unit for sequence decoding; a sequence decoding unit, receiving the sequence from the sequence sampling unit, decoding the sequence in parallel, sending the decoded sequence to the configurable sequence comparison unit, and sending the decoded sequence to the configurable sequence comparison unit; A configurable sequence comparison unit receives sequence information of expected results from the configuration information of the scan chain of the bus, waits for the decoding sequence sent by the sequence decoding unit, compares the sequence information with the configurable expected result sequence information, and sends the comparison result to the error counter and the state controller; The error counter receives the comparison results from the configurable sequence comparison unit, performs statistics on the comparison results, and sends the statistics of the total number of tests, the total number of errors and the error information to the state controller in real time; The state controller receives information from the error counter and feeds back the operating status information of the configurable scan chain, and accesses various information of the configured scan chain in real time through the AXI bus; The AXI bus controller is responsible for connecting the state controller, scan chain configuration unit and external communications, and opening access to the external interface state controller and scan chain configuration unit; The configurable frequency divider is responsible for the pulse width of the scan chain output sequence and the configurability of the overall operating frequency, and can achieve a frequency division of 10-1000 according to the frequency of the input system clock.

2. A novel FPGA-based dynamically configurable scan chain circuit test system as claimed in claim 1, characterized in that: The scan chain configuration unit includes the generation sequence information of the scan chain configured by the AXI bus, the expected result output information, the number of scan chain channels, the scan chain channel enable, and the frequency division coefficient information, which are used as the input of the sequence generation unit, the enable input of each channel of the scan chain, and the input of the configurable divider of other modules.

3. A novel FPGA-based dynamically configurable scan chain circuit test system as claimed in claim 1, characterized in that: The sequence generation unit includes the enable of the scan chain channel, the sequence parallel-serial conversion submodule, and the sequence channel output. The scan chain generation unit clock comes from the output clock of the configurable frequency divider. The enable of the scan chain channel determines which channels are enabled to output the sequence after the parallel sequence is serialized.

4. A novel FPGA-based dynamically configurable scan chain circuit test system as claimed in claim 1, characterized in that: The sequence sampling unit downsamples the output clock from the configurable frequency divider, samples the scan chain data input from the external interface, and sends the sampled serial sequence to the sequence decoding unit.

5. The novel FPGA-based dynamically configurable scan chain circuit test system according to claim 1, characterized in that: The sequence decoding unit includes a submodule for parallelizing the serial sequence, and sends the parallelized sequence data to the configurable sequence comparison unit for sequence comparison.

6. A novel FPGA-based dynamically configurable scan chain circuit testing system as claimed in claim 1, characterized in that: The error counter receives the comparison result from the configurable sequence comparison unit, performs statistics on the comparison result, and counts the total number of tests, the total number of errors, error information and the status information of one operation completion, and sends such information to the state controller in real time.

7. A novel FPGA-based dynamically configurable scan chain circuit testing system as claimed in claim 1, characterized in that: The state controller includes scan chain operation state information, operation completion state information, total number of scan chain tests, number of scan chain errors, and scan chain error information. These information are externally accessed through the AXI bus.

8. A novel FPGA-based dynamically configurable scan chain circuit testing method, using the novel FPGA-based dynamically configurable scan chain circuit testing system according to any one of claims 1 to 7, characterized in that: The steps include: S1: The original stimulus of the scan chain of the integrated circuit to be tested, the scan chain operating frequency, the expected output result of the scan chain, the number of scan chain channels, and the channel enable information are sent to the scan chain configuration unit through the AXI bus in a parallel encoding manner; S2: The scan chain configuration unit configures the scan chain and reads the scan chain status information in the state controller through the open AXI bus interface. According to the requirements, it reads the scan chain operation status information, the operation completion status information, the total number of scan chain tests, the number of scan chain errors, and the scan chain error information; S3: The read result does not affect the real-time operation of the scan chain. When the scan chain test needs to be stopped, the stop enable information is input to the scan chain configuration unit through the AXI bus.

Images