A peci bus power switching device and method

Abstract

The application provides a PECI bus power switching device and method, the device comprising: a first power supply circuit and a second power supply circuit, the first power supply circuit and the second power supply circuit are electrically connected with an IO interface of PECI; one end of the first power supply circuit is electrically connected with a VCC power supply, and the other end is electrically connected with the IO interface of PECI; one end of the second power supply circuit is electrically connected with a power supply module of CPU, and the other end is electrically connected with the IO interface of PECI; one of the first power supply circuit and the second power supply circuit supplies power for the IO interface of PECI; when the power supply module of CPU is not powered on, the first power supply circuit is turned on, when the power supply module of CPU is powered on, the first power supply circuit is turned off, and the second power supply circuit is turned on. The application switches the power supply of the IO interface of PECI, and solves the problem that the IO interface of PECI is not powered on after the BMC is powered on, resulting in the lock of the PECI controller from the hardware.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a PECI bus power switching device and method. Background Art

[0002] Currently, the CPU and BMC (Executable Server Remote Management Controller) chip are connected through the PECI (Platform Environment Information Control Interface) bus, and the BMC obtains CPU-related information and completes relevant alarms and handling strategies. Figure 2 As shown, the BMC includes two parts: the internal controller 1 of PECI and the IO (input / output) interface 2 of PECI. Figure 2 As shown, the currently commonly used PECI bus power supply design is as follows: PECI's IO interface 2 is powered by the CPU 3's power supply module (PECIVDD), while the internal controller 1 is powered by its own core power supply VDD. This indicates that the internal controller is powered by the BMC core power supply, while the PECI's IO interface's power domain must be consistent with the CPU's and cannot be powered by the BMC core power supply. This leads to a problem: due to power-on sequence differences or during a cold reset, the CPU's power supply is not on, and the PECI's IO interface is also not powered. However, while the BMC is operating normally (since the BMC is the first to perform power sequencing in the server), the PECI's IO interface does not respond when the internal controller attempts to communicate, causing the internal controller to remain in an address negotiation state and become locked. Existing technologies simply reset the internal controller through software after a lockup, which fails to fundamentally resolve the problem and introduces a delay, making it impossible to monitor the PECI bus status during this phase.

[0003] Therefore, the technical problem that needs to be solved urgently is: how to prevent the internal controller of the BMC from being locked when the power supply module of the CPU is not powered on. Summary of the Invention

[0004] The purpose of this application is to provide a PECI bus power switching device and method, which solves the problem of PECI controller being locked due to the PECI IO interface not being powered after BMC is powered on from a hardware perspective by switching the power supply of the PECI IO interface.

[0005] To achieve the above-mentioned objectives, the present application provides a PECI bus power switching device, which includes: a first power supply circuit and a second power supply circuit, wherein the first power supply circuit and the second power supply circuit are both electrically connected to the IO interface of the PECI; one end of the first power supply circuit is electrically connected to the VCC power supply, and the other end is electrically connected to the IO interface of the PECI; one end of the second power supply circuit is electrically connected to the power supply module of the CPU, and the other end is electrically connected to the IO interface of the PECI; one of the first power supply circuit and the second power supply circuit supplies power to the IO interface of the PECI.

[0006] The PECI bus power switching device as described above, wherein, when the power supply module of the CPU is not powered on, the first power supply circuit is turned on to supply power to the IO interface of the PECI; when the power supply module of the CPU is powered on, the first power supply circuit is turned off and the second power supply circuit is turned on to supply power to the IO interface of the PECI.

[0007] As described above, the PECI bus power switching device, wherein the first power supply circuit includes a first transmission wire and a first switch, one end of the first transmission wire is electrically connected to the VCC power supply, and the other end is electrically connected to the IO interface of the PECI; the first switch is electrically connected in the circuit of the first transmission wire.

[0008] As described above, the PECI bus power switching device, wherein the second power supply circuit includes a second transmission wire and a second switch, one end of the second transmission wire is electrically connected to the power supply module of the CPU, and the other end is electrically connected to the IO interface of the PECI; the second switch is electrically connected in the circuit of the second transmission wire.

[0009] The PECI bus power switching device as described above, wherein the enable terminal of the first switch and the enable terminal of the second switch are electrically connected via an inverter;

[0010] When the power supply module of the CPU is not powered on, the enable of the second switch is turned off, the inverter turns on the enable of the first switch, the first power supply circuit is turned on, and the VCC power supply supplies power to the IO interface of the PECI.

[0011] As described above, the PECI bus power switching device, wherein, when the power supply module of the CPU is powered on, the enable of the second switch is turned on, the inverter turns off the enable of the first switch, and the power supply module of the CPU supplies power to the IO interface of the PECI.

[0012] As described above, the PECI bus power switching device, wherein the output ends of the first power supply circuit and the second power supply circuit are electrically connected to the input end of the IO interface of the PECI through the same power supply wire.

[0013] The PECI bus power switching device as described above, wherein the power supply wire is electrically connected to a capacitor, one end of the capacitor is electrically connected to the power supply wire, and the other end is grounded;

[0014] The capacitor is used to stabilize the level change of the power supply during the conduction switching process between the first power supply circuit and the second power supply circuit.

[0015] The present application also provides a PECI bus power switching method, which is applied to the PECI bus power switching device, and the method comprises the following steps:

[0016] Detecting that the power supply module of the CPU is not powered on, turning off the enabling of the second switch;

[0017] Turning on the enable of the first switch through the inverter;

[0018] Monitor the voltage of the power supply module of the CPU, compare the voltage of the power supply module of the CPU with a preset voltage, and when the voltage of the power supply module of the CPU is greater than or equal to the preset voltage, control the enabling of the second switch to be turned on, and turn off the enabling of the first switch through the inverter; otherwise, continue to monitor the voltage of the power supply module of the CPU.

[0019] As described above, the PECI bus power switching method monitors the voltage of the power supply module of the CPU through a Schmitt trigger or a comparator, and compares the voltage of the power supply module of the CPU with a preset voltage. When the voltage of the power supply module of the CPU is greater than or equal to the preset voltage, the enable of the second switch is controlled to be turned on, and the enable of the first switch is turned off through an inverter.

[0020] The beneficial effects achieved by this application are as follows:

[0021] The present application sets up a first power supply circuit and a second power supply circuit to power the IO interface of PECI. When the voltage of the second power supply circuit is insufficient, the first power supply circuit is switched to power the IO interface of PECI, thereby solving the problem in the prior art that the IO interface of PECI is not powered after the BMC is powered on, causing the PECI controller to be locked, and avoiding the delay that causes the inability to monitor the status of the PECI bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can also be obtained based on these drawings.

[0023] Figure 1 This is a structural diagram of a PECI bus power switching device according to an embodiment of the present application.

[0024] Figure 2 The figure is a schematic diagram of the connection structure between the CPU and the BMC in the prior art.

[0025] Figure 3 This is a flow chart of a PECI bus power switching method according to an embodiment of the present application.

[0026] Figure numerals: 1-internal controller; 2-IO interface of PECI; 3-CPU; 4-first switch; 5-second switch; 6-inverter; 7-capacitor; 10-first power supply circuit; 20-second power supply circuit; 30-power supply wire. DETAILED DESCRIPTION

[0027] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0028] Example 1

[0029] like Figure 1 and 2 As shown, the present application provides a PECI bus power switching device, which is connected to the PECI IO interface 2 and provides power to the PECI IO interface 2. The PECI IO interface 2 is in communication with the internal controller 1, which is the PECI controller. The PECI IO interface 2 and the internal controller 1 are components of the Baseboard Management Controller (BMC); the PECI IO interface 2 is in communication with the CPU 3.

[0030] like Figure 1As shown, a PECI bus power switching device includes: a first power supply circuit 10 and a second power supply circuit 20, both of which are electrically connected to the IO interface 2 of the PECI; one of the first power supply circuit 10 and the second power supply circuit 20 supplies power to the IO interface 2 of the PECI, one end of the first power supply circuit 10 is electrically connected to the VCC power supply, and the other end is electrically connected to the IO interface 2 of the PECI; one end of the second power supply circuit 20 is electrically connected to the power supply module of the CPU 3, and the other end is electrically connected to the IO interface 2 of the PECI; when the power supply module of the CPU 3 is not powered on, the first power supply circuit 10 is turned on to supply power to the IO interface 2 of the PECI, and when the power supply module of the CPU 3 is powered on, the first power supply circuit 10 is turned off and the second power supply circuit 20 is turned on to supply power to the IO interface 2 of the PECI, thereby solving the problem that the PECI controller is locked due to the IO interface not being powered on after the BMC is powered on. After power is supplied, the IO interface 2 of the PECI communicates with the PECI controller.

[0031] The present application discloses a PECI bus power switching device, in which, when the CPU is not powered on, the VCC power supply is used to power the PECI IO interface 2, and the PECI internal controller in the BMC will not be locked. After the CPU is powered on, the PECI IO interface power supply in the BMC will automatically switch to the CPU power supply or power supply module PECIVDD, ensuring normal communication of the PECI IO interface between the BMC and the CPU.

[0032] like Figure 1 As shown, the first power supply circuit 10 includes a first power transmission line and a first switch 4. One end of the first power transmission line is electrically connected to the VCC power supply, and the other end is electrically connected to the IO interface 2 of the PECI. The first switch 4 is electrically connected to the circuit of the first power transmission line. When the first switch 4 is enabled, the first power supply circuit 10 is turned on and supplies power to the IO interface 2 of the PECI.

[0033] like Figure 1 As shown, the second power supply circuit 20 includes a second power transmission line and a second switch 5. One end of the second power transmission line is electrically connected to the power supply module of the CPU 3, and the other end is electrically connected to the IO interface 2 of the PECI. The second switch 5 is electrically connected in the circuit of the second power transmission line. When the second switch 5 is enabled, the second power supply circuit 20 is turned on and supplies power to the IO interface 2 of the PECI.

[0034] Preferably, the VCC power supply uses a power supply with a voltage value similar to that of the CPU's power supply module PECIVDD, so that the voltage used by the VCC power supply to supply the IO interface 2 of PECI is similar to the voltage used by the CPU's power supply module PECIVDD to supply the IO interface 2 of PECI, thereby improving the power domain and CPU consistency of the IO interface of PECI, and allowing the IO interface 2 of PECI to communicate normally with the PECI controller.

[0035] like Figure 1 As shown, the enable terminal (EN) of the first switch 4 and the enable terminal (EN) of the second switch 5 are electrically connected via an inverter 6; the inverter 6 is used to control the enable of the first switch 4 when the enable of the second switch 5 is turned off. When the first switch 4 is turned on, the enable signal of the first switch 4 is valid, the first switch 4 starts to operate, the first power supply circuit 10 is turned on, and power is supplied to the IO interface 2 of the PECI. When the second switch 5 is turned off, the enable signal of the second switch 5 is invalid, the second switch 5 does not operate, the second power supply circuit 20 is not turned on, and no power is supplied to the IO interface 2 of the PECI.

[0036] As a specific embodiment of the present invention, when the power supply module of the CPU 3 is not powered on, the enable of the second switch 5 is turned off and there is no output. The inverter 6 turns on the enable of the first switch 4, the first power supply circuit 10 is turned on, and the VCC power supply supplies power to the IO interface 2 of the PECI. The PECI controller in the BMC and the IO interface of the PECI can communicate normally.

[0037] As a specific embodiment of the present invention, when the power supply module of CPU 3 is powered on, the enable of the second switch 5 is turned on, the inverter 6 turns off the enable of the first switch 4, and the power supply module (PECIVDD) of CPU 3 supplies power to the IO interface 2 of PECI, ensuring that the power supply of the IO interface of PECI and the CPU are in the same power domain.

[0038] like Figure 1 As shown, the output ends of the first power supply circuit 10 and the second power supply circuit 20 are electrically connected to the input end of the IO interface 2 of the PECI through the same power supply wire 30.

[0039] like Figure 1 As shown, a capacitor 7 is electrically connected to the power supply wire 30, one end of the capacitor 7 is electrically connected to the power supply wire 30, and the other end is grounded; the capacitor 7 is used to stabilize the level change of the power supply during the conduction switching process of the first power supply circuit 10 and the second power supply circuit 20.

[0040] Preferably, the first switch 4 and the second switch 5 need to be switches with very small on-resistance. Since the power supply current of the IO interface of the PECI is not large, there is basically no loss in the voltage after passing through the first switch 4 or the second switch 5.

[0041] Because the voltage of CPU 3's power supply module PECIVDD is typically low, a Schmitt trigger or comparator is required to enable the switch when PECIVDD reaches a certain voltage. Schmitt triggers and comparators are existing electronic components, including the 74LS14, 74LS18, CD4093, and HEF4093. Examples of comparators include the LM339 and LM393.

[0042] Example 2

[0043] like Figure 3 As shown, the present application also provides a PECI bus power switching method, which is applied to a PECI bus power switching device, and the method includes the following steps:

[0044] Step S1: It is detected that the power supply module of the CPU is not powered on, and the second switch is turned off.

[0045] As a specific embodiment of the present invention, after detecting that the power supply module of the CPU is not powered on through the Schmitt trigger, the second switch is turned off and the second switch is disconnected. After the second switch is disconnected, the second power supply circuit does not supply power.

[0046] Step S2: Turn on the enable of the first switch through the inverter.

[0047] As a specific embodiment of the present invention, the first switch is enabled by turning on the inverter, and the first switch is turned on. After the first switch is turned on, the first power supply circuit supplies power to the IO interface of the PECI.

[0048] Step S3, monitor the voltage of the CPU power supply module, compare the voltage of the CPU power supply module with the preset voltage, when the voltage of the CPU power supply module is greater than or equal to the preset voltage, control the second switch to be enabled and turn off the first switch through the inverter, otherwise, continue to monitor the voltage of the CPU power supply module.

[0049] As a specific embodiment of the present invention, the voltage of the CPU power supply module is monitored by a Schmitt trigger or a comparator, and the voltage of the CPU power supply module is compared with a preset voltage. When the voltage of the CPU power supply module is greater than or equal to the preset voltage, the second switch is enabled and turned on, and the first switch is enabled and turned off through the inverter. Otherwise, the voltage of the CPU power supply module continues to be monitored.

[0050] The beneficial effects achieved by this application are as follows:

[0051] The present application sets up a first power supply circuit and a second power supply circuit to power the IO interface of PECI. When the voltage of the second power supply circuit is insufficient, the first power supply circuit is switched to power the IO interface of PECI, thereby solving the problem in the prior art that the IO interface of PECI is not powered after the BMC is powered on, causing the PECI controller to be locked, and avoiding the delay that causes the inability to monitor the status of the PECI bus.

[0052] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0053] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0054] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0055] The foregoing is merely an embodiment of the present invention and is not intended to limit the present invention. It will be apparent to those skilled in the art that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims of the present invention.

Claims

1. A PECI bus power switching device, characterized in that: The device includes: a first power supply circuit and a second power supply circuit, wherein the first power supply circuit and the second power supply circuit are both electrically connected to the IO interface of the PECI, the first power supply circuit includes a first switch, and the second power supply circuit includes a second switch; One end of the first power supply circuit is electrically connected to the VCC power supply, and the other end is electrically connected to the IO interface of the PECI; one end of the second power supply circuit is electrically connected to the power supply module of the CPU, and the other end is electrically connected to the IO interface of the PECI; One of the first power supply circuit and the second power supply circuit supplies power to the IO interface of the PECI.

2. The PECI bus power switching device according to claim 1, characterized in that: When the power supply module of the CPU is not powered on, the first power supply circuit is turned on to supply power to the IO interface of the PECI. When the power supply module of the CPU is powered on, the first power supply circuit is turned off and the second power supply circuit is turned on to supply power to the IO interface of the PECI.

3. The PECI bus power switching device according to claim 2, characterized in that: The first power supply circuit includes a first transmission wire, one end of the first transmission wire is electrically connected to the VCC power supply, and the other end is electrically connected to the IO interface of the PECI; the first switch is electrically connected in the circuit of the first transmission wire.

4. The PECI bus power switching device according to claim 3, characterized in that: The second power supply circuit includes a second transmission wire, one end of the second transmission wire is electrically connected to the power supply module of the CPU, and the other end is electrically connected to the IO interface of the PECI; the second switch is electrically connected in the circuit of the second transmission wire.

5. The PECI bus power switching device according to claim 4, characterized in that: The enable terminal of the first switch and the enable terminal of the second switch are electrically connected through an inverter; When the power supply module of the CPU is not powered on, the enable of the second switch is turned off, the inverter turns on the enable of the first switch, the first power supply circuit is turned on, and the VCC power supply supplies power to the IO interface of the PECI.

6. The PECI bus power switching device according to claim 5, characterized in that: When the power supply module of the CPU is powered on, the enable of the second switch is turned on, the inverter turns off the enable of the first switch, and the power supply module of the CPU supplies power to the IO interface of the PECI.

7. The PECI bus power switching device according to claim 1, characterized in that: The output ends of the first power supply circuit and the second power supply circuit are electrically connected to the input end of the IO interface of the PECI through the same power supply wire.

8. The PECI bus power switching device according to claim 7, characterized in that: The power supply wire is electrically connected to a capacitor, one end of the capacitor is electrically connected to the power supply wire, and the other end is grounded; The capacitor is used to stabilize the level change of the power supply during the conduction switching process between the first power supply circuit and the second power supply circuit.

9. A PECI bus power switching method, applied to the device according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: Detecting that the power supply module of the CPU is not powered on, turning off the enabling of the second switch; Turning on the enable of the first switch through the inverter; Monitor the voltage of the power supply module of the CPU, compare the voltage of the power supply module of the CPU with a preset voltage, and when the voltage of the power supply module of the CPU is greater than or equal to the preset voltage, control the enabling of the second switch to be turned on, and turn off the enabling of the first switch through the inverter; otherwise, continue to monitor the voltage of the power supply module of the CPU.

10. The PECI bus power switching method according to claim 9, characterized in that: The voltage of the power supply module of the CPU is monitored by a Schmitt trigger or a comparator, and the voltage of the power supply module of the CPU is compared with a preset voltage.

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