An instruction control method and device, and an electronic device

Abstract

Embodiments of the present application provide an instruction control method, device and electronic equipment, the method comprising: identifying a to-be-controlled instruction in a target program, and modifying the to-be-controlled instruction into a target instruction; obtaining enable state information of a control state register; determining whether to mark an enable control bit corresponding to the target instruction according to the enable state information; if the enable control bit corresponding to the target instruction is marked, determining that the target instruction is an invalid instruction, and sequentially executing a next instruction. The target instruction satisfies at least one of the following: an operation code of the target instruction is a target operation code, the target operation code being used to indicate that the target instruction is controlled by the control state register; at least one prefix control instruction is inserted before the target instruction. Embodiments of the present application can reduce performance overhead inside a processor, and improve the running efficiency of a software program.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an instruction control method, apparatus, and electronic device. Background Technology

[0002] In existing technology, once the instructions in a software program are written, the processor executes each instruction sequentially according to the predetermined program. When one or more instructions no longer need to be executed, a jump instruction is typically added before those instructions to bypass them.

[0003] However, in practice, jump actions can lead to significant performance overhead within the processor, reducing the efficiency of software programs. Summary of the Invention

[0004] This invention provides an instruction control method, apparatus, and electronic device that can solve the problem of inefficiently invalidating certain instructions in the prior art.

[0005] To address the above problems, this invention discloses an instruction control method, the method comprising:

[0006] Identify the instructions to be controlled in the target program, and modify the instructions to be controlled into the target instructions;

[0007] Obtain the enable status information of the control status register;

[0008] Determine whether to mark the enable control bit corresponding to the target instruction based on the enable status information;

[0009] If the enable control bit corresponding to the target instruction is marked, the target instruction is determined to be an invalid instruction, and the next instruction is executed sequentially.

[0010] Wherein, the target instruction satisfies at least one of the following:

[0011] The opcode of the target instruction is a target opcode, which is used to indicate that the target instruction is controlled by the control status register.

[0012] At least one prefix control instruction is inserted before the target instruction, which is used to indicate that the target instruction is controlled by the control status register.

[0013] On the other hand, embodiments of the present invention disclose an instruction control device, the device comprising:

[0014] The instruction processing module is used to identify the instruction to be controlled in the target program and modify the instruction to be controlled into the target instruction.

[0015] The information acquisition module is used to acquire the enable status information of the control status register;

[0016] A control bit marking module is used to determine whether to mark the enable control bit corresponding to the target instruction based on the enable status information.

[0017] The first execution module is configured to determine that the target instruction is an invalid instruction if the enable control bit corresponding to the target instruction is marked, and then execute the next instruction sequentially.

[0018] Wherein, the target instruction satisfies at least one of the following:

[0019] The opcode of the target instruction is a target opcode, which is used to indicate that the target instruction is controlled by the control status register.

[0020] At least one prefix control instruction is inserted before the target instruction, which is used to indicate that the target instruction is controlled by the control status register.

[0021] In another aspect, embodiments of the present invention also disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, wherein the executable instruction causes the processor to execute the aforementioned instruction control method.

[0022] This invention also discloses a readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to execute the aforementioned instruction control method.

[0023] The embodiments of the present invention have the following advantages:

[0024] The instruction control method provided in this invention modifies the instruction to be invalidated into a target instruction. The target instruction is controlled through a control status register. Before each execution of the target instruction, the enable control bit corresponding to the target instruction is marked based on the enable status information in the control status register. If the enable control bit corresponding to the target instruction is marked, the processor determines that the target instruction is invalid, ignores it, and executes the next instruction sequentially. Compared to existing technologies that use jump instructions to prevent certain instructions from being executed, this invention reduces the generation of jump instructions or memory loading instructions, lowers the processor's internal performance overhead, and improves the running efficiency of the software program. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating the steps of an embodiment of the instruction control method of the present invention;

[0027] Figure 2 This is a schematic diagram of the instruction format of a target instruction according to the present invention;

[0028] Figure 3 This is a schematic diagram of the basic block linking for binary translation according to the present invention;

[0029] Figure 4 This is a schematic diagram of the instruction format of a prefix control instruction according to the present invention;

[0030] Figure 5 This is a schematic diagram of an enable control bit list for a control status register according to the present invention;

[0031] Figure 6 This is a schematic diagram of the instruction format of another target instruction of the present invention;

[0032] Figure 7 This is a schematic diagram of the instruction format of another target instruction of the present invention;

[0033] Figure 8 This is a structural block diagram of an embodiment of the instruction control device of the present invention;

[0034] Figure 9 This is a schematic diagram of the structure of an electronic device for instruction control provided in an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Method Implementation Examples

[0037] Reference Figure 1 The diagram illustrates a flowchart of an embodiment of the instruction control method of the present invention. The method of the embodiment may specifically include the following steps:

[0038] Step 101: Identify the instruction to be controlled in the target program and modify the instruction to be controlled into the target instruction.

[0039] Step 102: Obtain the enable status information of the control status register.

[0040] Step 103: Determine whether to mark the enable control bit corresponding to the target instruction based on the enable status information.

[0041] Step 104: If the enable control bit corresponding to the target instruction is marked, the target instruction is determined to be an invalid instruction, and the next instruction is executed sequentially.

[0042] Step 105: If the enable control bit corresponding to the target instruction is not marked, then the target instruction is determined to be a valid instruction and the target instruction is executed.

[0043] The instruction control method provided in this embodiment of the invention can modify the instruction to be controlled into a target instruction, and use the control status register to control the execution or non-execution of the target instruction, so as to invalidate one or more instructions without the need for jump operations and reduce the performance overhead of the processor.

[0044] The target program can be a program obtained by binary translating the source program into binary code using a binary translation system. The instructions to be controlled include jump instructions of basic blocks in the binary translation system, where the target jump address of the jump instruction is the starting address of the next basic block. Alternatively, the target program can be other programs that require self-modification, such as programs that require code obfuscation. The instructions to be controlled include instructions generated during the code obfuscation process of the original code of the target program.

[0045] The Control and Status Register (CSR) is an essential component of the CPU (central processing unit) used to record and control the internal state of the processor. The operating system and applications can read or modify the CSR to obtain or change the processor's operating state. Essentially, the CSR maintains a list of enable control bits, which contains multiple target instructions and their corresponding enable control bits. When the CSR indicates that it is enabled, the enable control bit corresponding to the target instruction is marked.

[0046] It should be noted that, in this embodiment of the invention, the target instruction refers to an instruction that can be controlled and invalidated by the control status register. The target instruction satisfies at least one of the following:

[0047] A1. The opcode of the target instruction is a target opcode, which is used to indicate that the target instruction is controlled by the control status register.

[0048] A2. At least one prefix control instruction is inserted before the target instruction, and the prefix control instruction is used to indicate that the target instruction is controlled by the control status register.

[0049] For item A1, the target opcode is used to indicate that the target instruction is controlled by the control status register. Unlike ordinary instructions such as general-purpose instructions, floating-point instructions, vector instructions, and privileged instructions already existing in the processor, the target instruction in this invention has a specific opcode, i.e., a target opcode. This target instruction can perform the function of ordinary instructions existing in the processor and can also be controlled by the control status register. (Refer to...) Figure 2 This diagram illustrates the instruction format of a target instruction provided by an embodiment of the present invention. The instruction format of target instruction B, controlled by the control status register, is as follows: Figure 2 As shown, C_B_OPCODE corresponds to the opcode of the target instruction B. In comparison, Figure 2 The instruction format of a normal instruction B is also shown, where B_OPCODE corresponds to the opcode of the normal instruction B. It can be seen that the instruction format of the normal instruction B uses a different opcode than the instruction format of the target instruction B controlled by the control status register. The opcode of the target instruction B controlled by the control status register carries a specific identifier (e.g., ...). Figure 2 (The C_ identifier in the opcode). It should be noted that the specific identifier carried in the opcode of the target instruction is not limited to C_, but can be any other identifier that can distinguish it from ordinary instructions.

[0050] For item A2, at least one prefix control instruction is inserted before the target instruction. This prefix control instruction indicates that the target instruction is controlled by the control status register. The target instruction can be any instruction in the processor that needs to be controlled, i.e., the instruction to be controlled. In this embodiment of the invention, in addition to converting a normal instruction into a target instruction by modifying its opcode, a prefix control instruction can be inserted before the instruction to be controlled, i.e., the target instruction, to manage the target instruction.

[0051] Optionally, the target instruction and the prefix control instruction satisfy the following conditions: the storage address of the prefix control instruction is consecutively adjacent to the storage address of the target instruction, and the storage address of the prefix control instruction precedes the storage address of the target instruction. In this embodiment of the invention, the prefix control instruction needs to be executed before the target instruction so that the target instruction can be marked by the prefix control instruction, making the execution process of the target instruction controlled by the control status register. It is understood that existing processor execution methods are divided into two types: sequential execution and out-of-order execution. Sequential execution refers to executing instructions one by one according to the PC's fetch order. Out-of-order execution refers to the CPU allowing multiple instructions to be sent separately to the corresponding circuit units for processing, not in the order specified by the program. In this embodiment of the invention, the storage address of the prefix control instruction is consecutively adjacent to the storage address of the target instruction, and the storage address of the prefix control instruction precedes the storage address of the target instruction. Therefore, regardless of whether the execution method is sequential or out-of-order, it can be guaranteed that the prefix control instruction is executed before the target instruction.

[0052] In this embodiment of the invention, before executing the target instruction, the processor first obtains the enable status information of the control status register. The enable status information indicates whether the control status register is in an enabled state or a disabled state.

[0053] Based on the enable status information of the control status register, it can be determined whether to mark the enable control bit corresponding to the target instruction. Specifically, if the enable status information is the first status information, it indicates that the control status register is in the enabled state. In this case, the target instruction needs to be invalidated, and the enable control bit corresponding to the target instruction is marked. If the enable status information is the second status information, it indicates that the control status register is in the disabled state. In this case, the target instruction does not need to be invalidated, and therefore the enable status control bit corresponding to the target instruction is not marked.

[0054] If the enable bit corresponding to the target instruction is marked, it means the control status register needs to invalidate the target instruction, i.e., ignore the target instruction and execute the next instruction sequentially. If the enable bit corresponding to the target instruction is not marked, it means the control status register does not invalidate the target instruction, and in this case, the target instruction can be executed normally.

[0055] The instruction control method provided in this invention modifies the instruction to be invalidated into a target instruction. The target instruction is controlled through a control status register. Before each execution of the target instruction, the enable control bit corresponding to the target instruction is marked based on the enable status information in the control status register. If the enable control bit corresponding to the target instruction is marked, the processor determines that the target instruction is invalid, ignores it, and executes the next instruction sequentially. Compared to existing technologies that use jump instructions to prevent certain instructions from being executed, this invention reduces the generation of jump instructions or memory loading instructions, lowers the processor's internal performance overhead, and improves the running efficiency of the software program.

[0056] As an example, the instruction control method provided in this embodiment of the invention can be used to overcome the inefficiency of executing certain instructions in existing instruction sets, especially for code block linking and unlinking actions during binary translation, and reducing the generation of self-modifying code in code obfuscation, so as to reduce software-level overhead and accelerate the overall software running efficiency.

[0057] In one possible application scenario of this invention, the instruction to be controlled can be a jump instruction of a basic block in a binary translation system, and the jump instruction is used to link two basic blocks, that is, the target jump address of the jump instruction is the starting address of the next basic block. Here, the basic block is the basic working unit of the binary translation system.

[0058] Binary translation refers to the process of running an application based on a specific Instruction Set Architecture (ISA) (such as x86) on another ISA (such as a non-x86 instruction set) using binary translation technology, thus achieving cross-architecture and cross-instruction set program compatibility. However, cross-architecture binary translation incurs significant performance penalties. To address this issue, binary translation incorporates several optimization techniques, the most important of which is basic block linking. Basic block linking involves inserting linker code containing branch instructions that jump to the next basic block at the end of each basic block. These ordinary branch instructions unconditionally jump to the target, i.e., the next basic block. However, if the binary-translated program needs to exit for some reason, such as self-modified code, a disconnection operation is required. Disconnection operations typically introduce significant overhead.

[0059] Reference Figure 3 This diagram illustrates a basic block linking diagram for binary translation provided by an embodiment of the present invention. Figure 3As shown, the instructions for translating basic block 1 indicate that basic block 1 will be translated. After basic block 1 is translated, the program can jump to basic block 2 to translate it. Basic blocks 1 and 2 are not necessarily consecutive. At the end of each basic block, there is some code used to find the next basic block. This code is mainly divided into two parts. The first part is used for linking basic blocks, reserving a jump instruction for directly jumping to the next basic block. During the first execution, the reserved jump instruction is not yet filled, so it is essentially a no-op and has no effect. After this basic block is completed, the second part is entered. The second part is used to exit to the translator, allowing the translator to find and jump to the next basic block. After running to the next basic block, the translator will actively fill the reserved jump address part with the entry address of the next basic block. When this basic block is run a second time, it is no longer necessary to enter the second part; instead, it jumps directly to the next basic block.

[0060] from Figure 3 As can be seen, to achieve the requirement of breaking the link, the jump instructions used for linking in the first part need to be invalidated. In existing technologies, to achieve breaking the link of a basic block, it is common practice to add some jump instructions to directly jump to the next basic block, without executing the jump instructions used to link the basic blocks in the first part. This approach introduces significant overhead and affects the program's execution efficiency.

[0061] To reduce the overhead of basic block linking operations during binary translation and improve program efficiency, embodiments of this invention can modify the jump instructions used to link basic blocks in the binary translation system into target instructions, and use a control status register to control these jump instructions. Specifically, the opcode of the jump instructions used to link basic blocks in the binary translation system can be modified into a target opcode, which indicates that the target instruction is controlled by the control status register. Alternatively, a prefix control instruction can be inserted before the jump instructions used to link basic blocks in the binary translation system to manage the invalidation of the target instruction.

[0062] In the process of unlinking basic blocks during binary translation, this invention invalidates the original jump instructions by controlling the invalidation of the status register, thereby reducing the overhead of the unlinking operation.

[0063] In another possible application scenario of the present invention, the instruction to be controlled may be an instruction generated during the code obfuscation process of the original code. For example, the opcode of the instructions generated during the code obfuscation process can be modified to a target opcode, thereby modifying these instructions into target instructions; alternatively, a prefix control instruction can be inserted before each instruction that needs to be controlled, modifying these instructions that need to be controlled into target instructions.

[0064] In practical applications, code obfuscation techniques are commonly used to prevent external parties from stealing internal algorithms and other information from programs. Code obfuscation often employs self-modification techniques to obfuscate the program. Self-modification typically involves dynamically generating instructions during program execution and then skipping these instructions during program execution, executing the original code's instructions according to the program's original processing logic. If the instructions generated during code obfuscation are used as target instructions in this embodiment of the invention, and these instructions are invalidated using the instruction control method provided in this embodiment, the frequency of self-modification can be effectively reduced, improving program execution efficiency.

[0065] In an optional embodiment of the present invention, the opcode of the target instruction is a target opcode, and step 102, which determines whether to mark the enable control bit corresponding to the target instruction based on the enable state information, includes:

[0066] Step S11: If the enable status information is the first status information, then the enable control bit corresponding to the target instruction is marked; the first status information is used to indicate that the control status register is in the enabled state.

[0067] Step S12: If the enable status information is the second status information, then the enable control bit corresponding to the target instruction is not marked; the second status information is used to indicate that the control status register is in a disabled state.

[0068] The opcode of the target instruction is called the target opcode, which indicates that the target instruction is controlled by the control status register. For the target instruction, the enable status information of the control status register can be used to determine whether the control status register is enabled. If the enable status information is the first status information, indicating that the control status register is enabled, the target instruction needs to be invalidated. In this case, the enable control bit corresponding to the target instruction is marked. If the enable status information is the second status information, indicating that the control status register is disabled, then the target instruction does not need to be invalidated, and therefore the enable control bit corresponding to the target instruction is not marked.

[0069] In an optional embodiment of the present invention, a prefix control instruction is inserted before the target instruction. The prefix control instruction includes a first operand, which is determined according to the scope of the prefix control instruction. The scope is used to indicate the storage area corresponding to the target instruction controlled by the prefix control instruction. Step 102, determining whether to mark the enable control bit corresponding to the target instruction based on the enable state information, includes:

[0070] Step S21: If the enable status information is the first status information, then execute the prefix control instruction to mark the enable control bit corresponding to the target instruction stored in the scope according to the first operand; the first status information is used to indicate that the control status register is in the enabled state.

[0071] Step S22: If the enable status information is the second status information, then the enable control bit corresponding to the target instruction stored in the scope is not marked; the second status information is used to indicate that the control status register is in a disabled state.

[0072] The preceding instruction to the target instruction is a prefix control instruction, which indicates that the target instruction is controlled by the control status register. The prefix control instruction includes a first operand, which is determined based on the scope of the prefix control instruction. The scope indicates the memory region corresponding to the target instruction controlled by the prefix control instruction.

[0073] In this embodiment of the invention, for a target instruction, after obtaining the enable status information of the control status register, it is first determined whether the control status register is in an enabled state based on the enable status information. If the enable status information is the first status information, it indicates that the control status register is in an enabled state. At this time, the target instruction needs to be invalidated. Therefore, a prefix control instruction is executed to mark the enable control bit corresponding to the target instruction stored in the scope of the prefix control instruction according to the operand. The scope of the prefix control instruction is determined by the storage address of one or more target instructions controlled by the prefix control instruction. For example, assuming the prefix control instruction is used to control one target instruction A, whose storage address is 211-214, then the scope of the prefix control instruction is 211-214. If the prefix control instruction is used to control three target instructions, namely instructions A, B, and C, where the storage address of instruction A is 211-214, the storage address of instruction B is 215-218, and the storage address of instruction C is 219-221, then the scope of the prefix control instruction is 211-221. It should be noted that the scope of a prefix control instruction can be a single contiguous memory region or several non-contiguous memory regions. For example, if a prefix control instruction is used to control instructions A, B, and D, where instruction A is stored at addresses 211-214, instruction B at addresses 215-218, and instruction D at addresses 223-226, then the scope of this prefix control instruction is 211-218 and 223-226.

[0074] If the enable status information is the second status information, it means that the control status register is in the disabled state. In this case, it is not necessary to invalidate the target instruction. In this case, the enable control bit corresponding to the target instruction stored in the scope of the prefix control instruction is not marked.

[0075] Optionally, the prefix control instruction includes a second operand, which is determined based on the grouping information of the prefix control instruction. The grouping information indicates the group to which the prefix control instruction belongs. Prefix control instructions with the same grouping information store target instructions in their scope that correspond to the same enable control bit. For example, suppose the target instructions stored in the scope A1 of the prefix control instruction include target instructions B1 and B2, and the target instructions stored in the scope A2 of the prefix control instruction include target instruction B3. Since the second operand of both prefix control instructions A1 and A2 is G1, indicating that prefix control instructions A1 and A2 belong to the same group, then target instructions B1, B2, and B3 correspond to the same enable control bit. (Refer to...) Figure 4The diagram illustrates the instruction format of a prefix control instruction provided in an embodiment of the present invention. In this diagram, SET_CSR_COND_OPCODE is the opcode of the prefix control instruction, and GROUP is the second operand of the prefix control instruction, indicating the group number of the prefix control instruction.

[0076] It is understood that each target instruction has its corresponding enable control bit. Furthermore, in this embodiment of the invention, target instructions stored in the scope of prefix control instructions with the same grouping information can correspond to the same enable control bit. Once a prefix control instruction in a group marks the enable control bit corresponding to the target instruction in its scope, the target instructions stored in the scope of each prefix control instruction in that group can be simultaneously invalidated, improving processing efficiency.

[0077] It should be noted that for any prefix control instruction, its operands can include a first operand and / or a second operand. When prefix control instructions contain different operands, their opcodes are the same. For example, prefix control instruction C1 has a first operand as its operand, prefix control instruction C2 has a second operand as its operand, and prefix control instruction C3 has both a first and a second operand. These three prefix control instructions all have the same opcode, indicating that instructions C1 to C3 are prefix control instructions. If the prefix control instruction only contains the first operand, it means that the prefix control instruction is not grouped and does not belong to any prefix control instruction group. This prefix control instruction is used to control the target instruction stored in the scope indicated by the first operand. It can be understood that the scope indicated by the first operand can be the storage address of the instruction following the prefix control instruction. If the prefix control instruction only contains the second operand, then by default, the scope of the prefix control instruction is the storage address of its next instruction, that is, the prefix control instruction is used to control its next instruction.

[0078] In an optional embodiment of the present invention, the prefix control instruction includes a second operand, and the method further includes: if the enable control bit corresponding to the target instruction stored in the scope of the prefix control instruction is marked, then according to the second operand, the enable control bit corresponding to the target instruction stored in the scope of other prefix control instructions in the group to which the prefix control instruction belongs is marked.

[0079] In this embodiment of the invention, in addition to setting the same enable control bit for target instructions stored in the scope of prefix control instructions with the same grouping information, a separate enable control bit can also be set for each target instruction. As long as the enable control bit corresponding to the target instruction stored in the scope of a certain prefix control instruction in the group is marked, the enable control bits corresponding to the target instructions stored in the scope of other prefix control instructions in the group are also marked according to the second operand, that is, the grouping information of the prefix control instructions. In this way, it is not necessary to set the same enable control bit for the target instructions stored in the scope of prefix control instructions with the same grouping information, and it is also possible to realize the synchronous invalidation of target instructions controlled by each prefix control instruction in the same group, thereby improving the instruction control efficiency and program processing efficiency.

[0080] As an example, there are currently five target instructions, denoted as instruction A, instruction B, instruction C, instruction D, and instruction E. Prefix control instructions are inserted before each target instruction. These five prefix control instructions have the same opcode and are grouped sequentially as 2, 4, 3, 2, and 2. It can be seen that the group number of the prefix control instructions corresponding to instructions A, D, and E is 2. Therefore, if the enable control bit of any one of instructions A, D, or E is marked, the enable control bits of the other two instructions will also be marked. Consequently, during processor execution, the invalidation of instructions A, D, and E will be synchronized.

[0081] Understandably, the control status register maintains a list of enable control bits, which contains multiple target instructions and their corresponding enable control bits. When the enable status information in the control status register indicates that the control status register is enabled, the enable control bit corresponding to the target instruction is marked.

[0082] Reference Figure 5 The diagram illustrates a list of enable control bits for a control status register according to an embodiment of the present invention. The enable control bits in the control status register can include, but are not limited to, any of the following: 1) general arithmetic instruction control; 2) control flow instruction control; 3) floating-point and vector instruction control; 4) memory access instruction control; 5) atomic instruction control; and 6) instruction group control. Each type of instruction (1) to 5) can contain multiple sub-items, each sub-item corresponding to a target instruction. A corresponding enable control bit can be set for each sub-item. Figure 4 Only a few examples are shown in the text.

[0083] like Figure 5 As shown, the general arithmetic instruction control is used to enable the corresponding arithmetic instructions, where OR represents the OR operation instruction, AND represents the AND operation instruction, and ADD represents the summation operation instruction.

[0084] Control flow instructions control the enable control corresponding to transfer instructions, where BEQ represents an equal jump, BNE represents an unequal jump, and B represents an unconditional jump.

[0085] Floating-point and vector instruction control is used to enable floating-point arithmetic instructions, vector arithmetic instructions, and other instructions. FDIV represents floating-point division instruction, FMUL represents floating-point multiplication instruction, and FADD represents floating-point addition instruction.

[0086] The memory access instruction control controls the enable control of the instructions used to access memory or access data. Among them, FST represents the floating-point store instruction, LD represents the fetch instruction, and ST represents the store instruction.

[0087] Atomic instruction control is used to enable atomic instructions. An atomic instruction is an indivisible instruction that cannot be interrupted by any other task or event before execution is complete. Specifically, AMADD represents an atomic addition instruction, SC represents an atomic store instruction, and LL represents an atomic fetch instruction.

[0088] Instruction group control is used to control the enabling status of target instructions within the scope of prefix control instructions in each group. Figure 5 The example only shows four grouping configurations, where G3 represents group number 3, G2 represents group number 2, G1 represents group number 1, and G0 represents group number 0. In this embodiment of the invention, the number of groups can be expanded as needed.

[0089] In this embodiment of the invention, a prefix control instruction can be added before the target instruction whose opcode is the target opcode, so as to utilize the grouping information of the prefix control instruction to simultaneously invalidate multiple target instructions. (See also...) Figure 6 This illustrates a schematic diagram of the instruction format of another target instruction provided in an embodiment of the present invention. For example... Figure 6 As shown, a prefix control instruction can be inserted before the target instruction with opcode C_B_OPCODE. In this instruction, the SET_CSR_COND_OPCODE field is the opcode of the prefix control instruction, AREA is the first operand of the prefix control instruction, which indicates the scope of the prefix control instruction, and GROUP is the second operand of the prefix control instruction, which indicates the grouping information of the prefix control instruction. For example, the second operand can be the grouping number of the prefix control instruction.

[0090] In this embodiment of the invention, a prefix control instruction can also be used as the target instruction. That is, a prefix control instruction is inserted before the prefix control instruction, and the prefix control instruction is used to mark the enable control bit of another prefix control instruction to set the priority of the target instruction controlled by the prefix control instruction. For example, if the target instruction stored in the scope of prefix control instruction A1 is instruction B1, and the target instruction stored in the scope of prefix control instruction A2 is instruction A1, then when the processor invalidates instruction B1 and prefix control instruction A1, it will process instruction A1 first, and then process instruction B1. (Refer to...) Figure 7 This illustrates a schematic diagram of the instruction format of another target instruction according to an embodiment of the present invention, namely, adding a prefix control instruction before the prefix control instruction. For example... Figure 7 As shown, a prefix control instruction 2 is inserted before the ordinary instruction, i.e., the target instruction in this invention, and a prefix control instruction 1 is inserted before prefix control instruction 2. In invalidation processing, Figure 7 In this context, prefix control instruction 1 has a higher priority than prefix control instruction 2. If prefix control instruction 2 is invalidated, then... Figure 7 Ordinary instructions in the code are no longer controlled by prefix control instruction 2; if prefix control instruction 2 is not invalidated, prefix control instruction 2 is executed normally, and ordinary instructions are still controlled by prefix control instruction 2.

[0091] It should be noted that if the scope of a prefix control instruction contains multiple target instructions, and each target instruction contains a prefix control instruction, then in the instruction sequence, the invalidation priority of the preceding prefix control instruction is higher than that of the following prefix control instruction. For example, in the instruction sequence [A3, A4, A5, B1], where the scope of prefix control instruction A3 stores target instructions A4, A5, and B1, and prefix control instructions A4 and A5 both invalidate their next instruction, then during the invalidation process, the invalidation priority of each instruction is: A3 > A4 > A5 > B1.

[0092] certainly, Figure 7 Ordinary instructions in the code can also be target instructions in this invention; this case belongs to... Figure 6 and Figure 7 The nesting of target instructions is shown.

[0093] In summary, the instruction control method provided by this invention modifies the instruction to be invalidated into a target instruction. The target instruction is controlled through a control status register. Before each execution of the target instruction, the enable control bit corresponding to the target instruction is marked based on the enable status information in the control status register. If the enable control bit corresponding to the target instruction is marked, the processor determines that the target instruction is invalid, ignores it, and executes the next instruction sequentially. Compared to existing technologies that use jump instructions to prevent certain instructions from being executed, this invention reduces the generation of jump instructions or memory loading instructions, lowers the processor's internal performance overhead, and improves the running efficiency of the software program.

[0094] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0095] Device Examples

[0096] Reference Figure 8 The diagram illustrates a structural block diagram of an embodiment of the command control device of the present invention, wherein the device may specifically include:

[0097] The instruction processing module 801 is used to identify the instruction to be controlled in the target program and modify the instruction to be controlled into the target instruction.

[0098] The information acquisition module 802 is used to acquire the enable status information of the control status register;

[0099] The control bit marking module 803 is used to determine whether to mark the enable control bit corresponding to the target instruction based on the enable status information;

[0100] The first execution module 804 is used to determine that the target instruction is an invalid instruction if the enable control bit corresponding to the target instruction is marked, and to execute the next instruction sequentially.

[0101] Wherein, the target instruction satisfies at least one of the following:

[0102] The opcode of the target instruction is a target opcode, which is used to indicate that the target instruction is controlled by the control status register.

[0103] At least one prefix control instruction is inserted before the target instruction, which is used to indicate that the target instruction is controlled by the control status register.

[0104] Optionally, the device further includes:

[0105] The second execution module is used to determine that the target instruction is a valid instruction and execute the target instruction if the enable control bit corresponding to the target instruction is not marked.

[0106] Optionally, the opcode of the target instruction is a target opcode, and the control bit marking module includes:

[0107] The first processing submodule is used to mark the enable control bit corresponding to the target instruction if the enable status information is the first status information; the first status information is used to indicate that the control status register is in the enabled state.

[0108] The second processing submodule is configured to not mark the enable control bit corresponding to the target instruction if the enable status information is the second status information; the second status information is used to indicate that the control status register is in a disabled state.

[0109] Optionally, a prefix control instruction is inserted before the target instruction. The prefix control instruction includes a first operand, which is determined according to the scope of the prefix control instruction. The scope is used to indicate the storage area corresponding to the target instruction controlled by the prefix control instruction. The control bit marking module includes:

[0110] The third processing submodule is used to execute the prefix control instruction if the enable status information is the first status information, so as to mark the enable control bit corresponding to the target instruction stored in the scope according to the first operand; the first status information is used to indicate that the control status register is in the enabled state.

[0111] The fourth processing submodule is configured to not mark the enable control bit corresponding to the target instruction stored in the scope if the enable status information is the second status information; the second status information is used to indicate that the control status register is in a disabled state.

[0112] Optionally, the scope of the prefix control instruction is determined by the storage address of one or more target instructions controlled by the prefix control instruction.

[0113] Optionally, the prefix control instruction includes a second operand, which is determined based on the grouping information of the prefix control instruction. The target instructions stored in the scope of prefix control instructions with the same grouping information correspond to the same enable control bit.

[0114] Optionally, the control bit marker module further includes:

[0115] The control bit marking submodule is used to mark the enable control bits corresponding to the target instructions stored in the scope of other prefix control instructions in the group to which the prefix control instruction belongs, according to the second operand, if the enable control bit corresponding to the target instruction stored in the scope of the prefix control instruction is marked.

[0116] Optionally, a prefix control instruction is inserted before the target instruction, and the target instruction and the prefix control instruction satisfy the following conditions:

[0117] The storage address of the prefix control instruction is consecutively adjacent to the storage address of the target instruction, and the storage address of the prefix control instruction is before the storage address of the target instruction.

[0118] Optionally, the instruction to be controlled includes a jump instruction of a basic block in a binary translation system, wherein the target jump address of the jump instruction is the starting address of the next basic block; or, the instruction to be controlled includes instructions generated during the code obfuscation process of the original code.

[0119] Optionally, the control status register maintains an enable control bit list, which contains the enable control bits corresponding to each target instruction.

[0120] In summary, the instruction control device provided in this embodiment of the invention modifies the instruction to be invalidated into a target instruction, controls the target instruction through a control status register, and thus, before each execution of the target instruction, determines whether to mark the enable control bit corresponding to the target instruction based on the enable status information of the control status register. If the enable control bit corresponding to the target instruction is marked, the processor determines the target instruction as an invalid instruction, ignores the target instruction, and sequentially executes the next instruction. Compared with the prior art that adds jump instructions to prevent the program from executing certain instructions, this embodiment of the invention can reduce the generation of jump instructions or memory loading instructions, reduce the performance overhead inside the processor, and improve the running efficiency of the software program.

[0121] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0122] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0123] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0124] Reference Figure 9 This is a schematic diagram of the structure of an electronic device for command control provided in an embodiment of the present invention. Figure 9 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to execute the instruction control method of the aforementioned embodiment.

[0125] This invention provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by a terminal's program or processor, enables the terminal to execute the instruction control method described in the foregoing embodiments.

[0126] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0127] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0129] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0130] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0131] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0132] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0133] The above provides a detailed description of the instruction control method, apparatus, and electronic device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An instruction control method characterized by comprising: The method comprises: identifying a to-be-controlled instruction in a target program, and modifying the to-be-controlled instruction into a target instruction; obtaining enable state information of a control state register; determining whether to mark an enable control bit corresponding to the target instruction according to the enable state information; if the enable control bit corresponding to the target instruction is marked, determining that the target instruction is an invalid instruction, and sequentially executing a next instruction; wherein the target instruction satisfies at least one of the following conditions: an operation code of the target instruction is a target operation code, and the target operation code is used to indicate that the target instruction is controlled by the control state register; at least one prefix control instruction is inserted before the target instruction, and the prefix control instruction is used to indicate that the target instruction is controlled by the control state register.

2. The method of claim 1, wherein, The method further comprises: if the enable control bit corresponding to the target instruction is not marked, determining that the target instruction is a valid instruction, and executing the target instruction.

3. The method of claim 1, wherein, The operation code of the target instruction is a target operation code, and the determining whether to mark the enable control bit corresponding to the target instruction according to the enable state information comprises: if the enable state information is first state information, marking the enable control bit corresponding to the target instruction; the first state information is used to indicate that the control state register is in an enabled state; if the enable state information is second state information, not marking the enable control bit corresponding to the target instruction; the second state information is used to indicate that the control state register is in a disabled state.

4. The method of claim 1, wherein, The prefix control instruction before the target instruction comprises a first operand, and the first operand is determined according to a scope of the prefix control instruction; the scope is used to indicate a storage interval of a target instruction controlled by the prefix control instruction; The determining whether to mark the enable control bit corresponding to the target instruction according to the enable state information comprises: if the enable state information is first state information, executing the prefix control instruction to mark the enable control bit corresponding to the target instruction stored in the scope according to the first operand; the first state information is used to indicate that the control state register is in an enabled state; if the enable state information is second state information, not marking the enable control bit corresponding to the target instruction stored in the scope; the second state information is used to indicate that the control state register is in a disabled state.

5. The method of claim 4, wherein, The scope of the prefix control instruction is determined by storage addresses of one or more target instructions controlled by the prefix control instruction.

6. The method of claim 4, wherein, The prefix control instruction comprises a second operand, and the second operand is determined according to grouping information of the prefix control instruction; the grouping information is used to indicate a grouping to which the prefix control instruction belongs; target instructions stored in the scope of prefix control instructions with same grouping information correspond to a same enable control bit.

7. The method of claim 6, wherein, The method further comprises: If an enable control bit corresponding to a target instruction stored in a scope of the prefix control instruction is marked, mark an enable control bit corresponding to a target instruction stored in a scope of another prefix control instruction in a group to which the prefix control instruction belongs according to the second operand.

8. The method of claim 1, wherein, The target instruction is inserted with a prefix control instruction before the target instruction, and the target instruction and the prefix control instruction satisfy the following conditions: The storage address of the prefix control instruction is continuously adjacent to the storage address of the target instruction, and the storage address of the prefix control instruction is before the storage address of the target instruction.

9. The method according to any one of claims 1 to 8, characterized in that, The to-be-controlled instruction includes a jump instruction of a basic block in a binary translation system, and a target jump address of the jump instruction is a start address of a next basic block; or the to-be-controlled instruction includes an instruction generated in a code obfuscation process of original code.

10. The method according to any one of claims 1 to 8, characterized in that, The control state register maintains an enable control bit list, and the enable control bit list includes an enable control bit corresponding to each target instruction.

11. An instruction control device characterized by comprising: The apparatus comprises: An instruction processing module, configured to identify a to-be-controlled instruction in a target program, and modify the to-be-controlled instruction into a target instruction; An information acquisition module, configured to acquire enable state information of a control state register; An control bit marking module, configured to determine whether to mark an enable control bit corresponding to the target instruction according to the enable state information; A first execution module, configured to, if the enable control bit corresponding to the target instruction is marked, determine that the target instruction is an invalid instruction, and sequentially execute a next instruction. The target instruction satisfies at least one of the following conditions: An operation code of the target instruction is a target operation code, and the target operation code is used to indicate that the target instruction is controlled by the control state register; At least one prefix control instruction is inserted before the target instruction, and the prefix control instruction is used to indicate that the target instruction is controlled by the control state register.

12. The apparatus of claim 11, wherein, The apparatus further comprises: A second execution module, configured to, if the enable control bit corresponding to the target instruction is not marked, determine that the target instruction is a valid instruction, and execute the target instruction.

13. The apparatus of claim 11, wherein, The operation code of the target instruction is a target operation code, and the control bit marking module comprises: A first processing submodule, configured to, if the enable state information is first state information, mark the enable control bit corresponding to the target instruction; the first state information is used to indicate that the control state register is in an enabled state; A second processing submodule, configured to, if the enable state information is second state information, not mark the enable control bit corresponding to the target instruction; the second state information is used to indicate that the control state register is in a disabled state.

14. The apparatus of claim 11, wherein, The target instruction is inserted with a prefix control instruction before the target instruction, and the prefix control instruction includes a first operand, the first operand is determined according to a scope of the prefix control instruction, and the scope is used to indicate a storage interval corresponding to a target instruction controlled by the prefix control instruction. The control bit marking module comprises: The third processing submodule is configured to execute the prefix control instruction to mark the corresponding enable control bit of the target instruction stored in the scope according to the first operand if the enable state information is first state information; the first state information is used to indicate that the control state register is in an enabled state. The fourth processing submodule is configured to not mark the corresponding enable control bit of the target instruction stored in the scope if the enable state information is second state information; the second state information is used to indicate that the control state register is in a disabled state.

15. The apparatus of claim 14, wherein, The scope of the prefix control instruction is determined by the storage address of one or more target instructions controlled by the prefix control instruction.

16. The apparatus of claim 14, wherein, The prefix control instruction comprises a second operand, and the second operand is determined according to grouping information of the prefix control instruction; the grouping information is used to indicate a grouping to which the prefix control instruction belongs; the target instructions stored in the scopes of prefix control instructions with same grouping information correspond to a same enable control bit.

17. The apparatus of claim 16, wherein, The control bit marking module further comprises: The control bit marking submodule is configured to mark the corresponding enable control bit of the target instruction stored in the scope of the prefix control instruction if the corresponding enable control bit of the target instruction stored in the scope of the prefix control instruction is marked; and mark the corresponding enable control bit of the target instruction stored in the scope of other prefix control instructions in the grouping to which the prefix control instruction belongs according to the second operand.

18. The apparatus of claim 11, wherein, The target instruction is inserted with the prefix control instruction in front, and the target instruction and the prefix control instruction satisfy the following conditions: The storage address of the prefix control instruction is continuously adjacent to the storage address of the target instruction, and the storage address of the prefix control instruction is before the storage address of the target instruction.

19. The apparatus of any one of claims 11 to 18, wherein, The target instruction comprises a jump instruction of a basic block in a binary translation system, and a target jump address of the jump instruction is a start address of a next basic block; or the target instruction comprises an instruction generated in a code obfuscation process on original code.

20. The apparatus of any one of claims 11 to 18, wherein, The control state register maintains an enable control bit list, and the enable control bit list comprises the corresponding enable control bit of each target instruction.

21. An electronic device, comprising: Comprise: A processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction control method in any one of claims 1 to 10.

22. A readable storage medium, characterized by, When the instructions in the storage medium are executed by the processor of the electronic device, the processor can execute the instruction control method in any one of claims 1 to 10.

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