A system and method for verifying on-chip high-speed bus data

Abstract

The application provides a system and method for checking data of an on-chip high-speed bus, comprising a host device, a slave device and an on-chip high-speed bus for transmitting data between the host device and the slave device, further comprising an error detection and correction module mounted on the on-chip high-speed bus through a bus interface, when the host device reads and writes data to the slave device through the on-chip high-speed bus, the error detection and correction module acquires write data and read data of the on-chip high-speed bus, and checks the write data and the read data with the same access address. According to the technical scheme of the embodiment, the error detection and correction module can acquire read and write data of each device and check the data, simplifying the checking system of the on-chip high-speed bus data, without configuring checking logic in each device, saving design resources, improving the reliability and efficiency of bus data transmission, facilitating the portability of data checking design, and reducing project design cost and development cycle.

Description

Technical Field

[0001] This invention belongs to the field of data verification technology, and in particular relates to a verification system and method for on-chip high-speed bus data. Background Technology

[0002] The on-chip high-speed bus is located within the chip and is used for high-speed interconnection between various devices on the chip. In high-reliability space applications, chips often operate in environments with strong electricity and radiation, which can easily cause data flipping errors on the on-chip high-speed bus. This necessitates comparison and verification of the read and write data of slave devices.

[0003] In related technologies, verification logic is typically configured in the controller of each device to compare and verify the target write data and target read data of that controller. However, this requires embedding verification logic in each controller, which not only consumes a lot of time for configuration and debugging, but also has poor portability, consumes a lot of design logic resources, and increases project design costs. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This invention provides a verification system and method for on-chip high-speed bus data, which simplifies the verification system for on-chip high-speed bus data, saves debugging time, and improves the portability of the verification system.

[0006] In a first aspect, embodiments of the present invention provide a verification system for on-chip high-speed bus data, including a host device, a slave device, and an on-chip high-speed bus, wherein the host device and the slave device are connected to the on-chip high-speed bus, and the on-chip high-speed bus is used for data transmission between the host device and the slave device, and further includes:

[0007] An error detection and correction module is connected to the on-chip high-speed bus via a bus interface. When the host device reads or writes data to the slave device via the on-chip high-speed bus, the error detection and correction module is used to obtain the write data and read data of the on-chip high-speed bus, and to perform data verification on the write data and read data with the same access address, wherein the access address is used to indicate the storage location of the slave device.

[0008] In some embodiments, the error detection and correction module includes:

[0009] A checksum generator is connected to the bus interface. When the on-chip high-speed bus is in write mode, the checksum generator obtains the write data of the on-chip high-speed bus through the bus interface and generates a write checksum. When the on-chip high-speed bus is in read mode, the checksum generator obtains the read data of the on-chip high-speed bus through the bus interface and generates a read checksum.

[0010] A verification code storage device is connected to the verification code generator, and the verification code storage device is used to store the write verification code;

[0011] A verifier is connected to both the checksum generator and the checksum memory. The verifier is used to perform data verification on the read checksum and the write checksum that have the same access address.

[0012] In some embodiments, the check code memory is connected to the bus interface. The check code memory is also used to acquire and record the access address of the write data, and to acquire the access address of the read data and send the write check code corresponding to the same access address as the read data to the verifier.

[0013] In some embodiments, the verifier is further configured to: when the result of data verification indicates that the verification fails, correct the read data according to the write data, or send an error report to the host device, the error report including the read data that failed verification and the address information of the corresponding access address.

[0014] In some embodiments, the check code memory is an on-chip random access memory.

[0015] Secondly, embodiments of the present invention provide a method for verifying on-chip high-speed bus data, applied to the on-chip high-speed bus data verification system described in the first aspect, the method for verifying on-chip high-speed bus data comprising:

[0016] When the host device reads and writes data with the slave device through the on-chip high-speed bus, the write data and read data of the on-chip high-speed bus are obtained through the error detection and correction module.

[0017] Data verification is performed on the write data and the read data that have the same access address, wherein the access address is used to indicate the storage location of the slave device.

[0018] In some embodiments, the error detection and correction module further includes a checksum memory, a checksum generator, and a verifier. The checksum generator is connected to the bus interface and the checksum memory, respectively. The verifier is connected to the checksum generator and the checksum memory, respectively. The checksum memory is also connected to the bus interface. The method further includes:

[0019] When the on-chip high-speed bus is in write mode, the check code generator obtains the write data of the on-chip high-speed bus, generates a write check code based on the write data and sends it to the check code memory for storage, and records the access address of the write data through the check code memory, and associates and saves the write check code and the access address of the write data.

[0020] When the on-chip high-speed bus is in read mode, the check code generator obtains the read data of the on-chip high-speed bus, generates a read check code based on the read data and sends it to the checker. The check code memory obtains the access address of the read data and sends the write check code corresponding to the same access address as the read data to the checker. The checker performs data verification on the obtained read check code and write check code.

[0021] In some embodiments, the step of performing data verification on the obtained read verification code and write verification code through the verifier includes:

[0022] Perform an XOR operation on the obtained read verification code and write verification code;

[0023] When the result of the XOR operation indicates that the obtained read check code and the write check code are the same, the result of the data verification is determined to be that the verification is successful.

[0024] In some embodiments, when the result of the XOR operation indicates that the obtained read check code and the write check code are not the same, the method further includes:

[0025] The obtained read check code and write check code are decoded to obtain decoded read data and decoded write data;

[0026] The error data bits in the decoded read data are determined based on the result of the XOR operation.

[0027] When the number of erroneous data bits is less than or equal to a preset threshold, the decoded read data is corrected according to the decoded write data, and the corrected decoded read data is updated to the slave device through the on-chip high-speed bus.

[0028] or,

[0029] When the number of error data bits exceeds a preset threshold, an error report is sent to the host device via the on-chip high-speed bus. The error report includes the decoded read data and the address information of the corresponding access address.

[0030] In some embodiments, the checksum generator generates the write checksum or the read checksum using the BCH encoding / decoding algorithm.

[0031] This invention includes a host device, slave devices, and an on-chip high-speed bus. The host device and the slave devices are connected to the on-chip high-speed bus, which is used for data transmission between the host device and the slave devices. It also includes an error detection and correction module connected to the on-chip high-speed bus via a bus interface. When the host device reads or writes data to the slave device via the on-chip high-speed bus, the error detection and correction module acquires the write and read data from the on-chip high-speed bus and performs data verification on the write and read data with the same access address. The access address indicates the storage location of the slave device. According to this embodiment, because the error detection and correction module is connected to the on-chip high-speed bus, it can acquire and verify the read and write data of each device, simplifying the on-chip high-speed bus data verification system. It eliminates the need to configure verification logic on each slave device, saving debugging time and effectively improving the portability of the on-chip high-speed bus data verification system, thus reducing the design cost of the on-chip high-speed bus data verification system.

[0032] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0033] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0034] Figure 1 This is a schematic diagram of the framework of the on-chip high-speed bus data verification system provided in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of the specific structure of an error detection and correction module provided in another embodiment of the present invention;

[0036] Figure 3 This is a flowchart of a method for verifying on-chip high-speed bus data provided in another embodiment of the present invention;

[0037] Figure 4 This is a flowchart of a method for verifying on-chip high-speed bus data provided in another embodiment of the present invention;

[0038] Figure 5 yes Figure 4 The detailed flowchart of step 420;

[0039] Figure 6 yes Figure 4 The detailed flowchart of step 420. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0041] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. Terms such as "first," "objective," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0042] This invention provides a verification system and method for on-chip high-speed bus data. The verification system includes a host device, a slave device, and an on-chip high-speed bus. The host device and the slave device are connected to the on-chip high-speed bus, which is used for data transmission between the host device and the slave device. The system also includes an error detection and correction module connected to the on-chip high-speed bus via a bus interface. When the host device reads or writes data to the slave device via the on-chip high-speed bus, the error detection and correction module acquires the write and read data from the on-chip high-speed bus and verifies the write and read data with the same access address. The access address indicates the storage location of the slave device. According to the technical solution of this embodiment, since the error detection and correction module is mounted on the on-chip high-speed bus, it can acquire the read and write data of each device and perform data verification, which simplifies the on-chip high-speed bus data verification system. It does not require configuring verification logic on each slave device, saving debugging time, and effectively improving the portability of the on-chip high-speed bus data verification system, thereby reducing the design cost of the on-chip high-speed bus data verification system.

[0043] Reference Figure 1 , Figure 1This application provides an on-chip high-speed bus data verification system, including a host device 110, a slave device 120, and an on-chip high-speed bus 130. The host device 110 and the slave device 120 are connected to the on-chip high-speed bus 130, which is used for data transmission between the host device 110 and the slave device 120. The system also includes:

[0044] Error detection and correction module 200 is connected to the on-chip high-speed bus 130 via bus interface 140. When the host device 110 reads and writes data to the slave device 120 via the on-chip high-speed bus 130, the error detection and correction module 200 is used to obtain the write data and read data of the on-chip high-speed bus 130, and to perform data verification on the write data and read data with the same access address. The access address is used to indicate the storage location of the slave device 120.

[0045] It should be noted that the on-chip high-speed bus data verification system of this application may include any number of host devices 110 and slave devices 120. The host device 110 may be a processor or a controller of a device module, and the slave device 120 may be a memory module. This embodiment does not limit the specific hardware type, as long as the host device 110 and the slave device 120 can transmit data through the on-chip high-speed bus 130.

[0046] It is worth noting that when the chip has multiple master devices 110 and multiple slave devices 120, the data between each master device 110 and any slave device 120 is transmitted through the on-chip high-speed bus 130. Therefore, the error detection and correction module 200 of this application is connected to the on-chip high-speed bus 130 through the bus interface 140, and can obtain the data transmitted between any master device 110 and any slave device 120 from the on-chip high-speed bus 130, for example... Figure 1As shown, when host device 1 wants to write data A to slave device 1, host device 1 sends data A to slave device 1 through the on-chip high-speed bus 130. During the transmission of data A, data A can also be transmitted to the error detection and correction module 200 through the bus interface 140. Similarly, when host device 1 wants to write data B to slave device 2, host device 1 sends data B to slave device 2 through the on-chip high-speed bus 130. During the transmission of data B, data B can also be transmitted to the error detection and correction module 200 through the bus interface 140. Furthermore, when host device 1 reads data A from slave device 1 through the on-chip high-speed bus 130, slave device 1 transmits data A to host device 1 through the on-chip high-speed bus 130. During the transmission, data A can be transmitted to the error detection and correction module 200 through the bus interface 140 for subsequent data verification. This embodiment, by mounting the error detection and correction module 200 to the on-chip high-speed bus 130, enables the data verification logic to be deployed within the error detection and correction module 200. This eliminates the need to design verification logic in the controller of each slave device 120. By directly mounting the error detection and correction module 200 on the existing chip structure, the data of the slave devices 120 on the on-chip high-speed bus 130 can be protected, improving the stability and anti-interference capability of the entire on-chip high-speed bus data verification system and simplifying the design of the entire system.

[0047] It should be noted that, to ensure that the read data and write data used for data verification are the same data, this embodiment uses the access address as the matching basis, so that the read data and write data both correspond to the same storage location of the slave device 120. For example, after writing write data A to location 1 of slave device 1, and then reading read data A from location 1 of slave device 1 and reading read data B from location 1 of slave device 2, the location 1 of slave device 1 is used as the matching basis to verify the write data A and read data A. The specific form of the access address can be selected according to actual needs, and this embodiment does not impose any limitations on it.

[0048] It should be noted that this embodiment uses the access address as the basis to match the corresponding read and write data for data verification, which can effectively distinguish the data stored in different slave devices 120, ensuring accurate matching of read and write data that can be verified. Thus, the number of master devices 110 and slave devices 120 can be arbitrarily adjusted in the chip, and the error detection and correction module 200 can be directly ported to other chips for use, as long as the verification logic is consistent. This effectively improves the portability of the on-chip high-speed bus data verification system, and also effectively simplifies the configuration process and debugging time of the verification logic, reducing development costs.

[0049] It should be noted that since write data and read data are usually transmitted in bytes on the on-chip high-speed bus 130, write data and read data can be one byte of data. Of course, if there is a need for actual data verification, the technical solution of this embodiment can also be implemented for the dataset, such as performing data verification on the write dataset and read dataset of a certain storage area. Those skilled in the art know that the technical solution disclosed in this embodiment can be extended, and the amount and scale of read data and write data are not limited here.

[0050] Additionally, in one embodiment, reference is made to Figure 1 and Figure 2 The error detection and correction module 200 includes:

[0051] The check code generator 210 is connected to the bus interface 140. When the on-chip high-speed bus 130 is in write mode, the check code generator 210 obtains the write data of the on-chip high-speed bus 130 through the bus interface 140 and generates a write check code. When the on-chip high-speed bus 130 is in read mode, the check code generator 210 obtains the read data of the on-chip high-speed bus 130 through the bus interface 140 and generates a read check code.

[0052] The verification code memory 220 is connected to the verification code generator 210 and is used to store the write verification code.

[0053] Verifier 230 is connected to check code generator 210 and check code memory 220 respectively. Verifier 230 is used to perform data verification on read check codes and write check codes with the same access address.

[0054] It should be noted that the checksum generator 210 can be connected to the on-chip high-speed bus 130 through the bus interface 140, thereby acquiring data when the on-chip high-speed bus 130 is in write or read state. For example, when the on-chip high-speed bus 130 is in write state, the write data in the on-chip high-speed bus 130 is simultaneously transmitted to the slave device 120 and the checksum generator 210, and the checksum generator 210 generates a write checksum based on the acquired write data; the same applies when the on-chip high-speed bus 130 is in read state, which will not be repeated here.

[0055] It should be noted that, in order to improve the accuracy of data verification, the write check code can be generated for each byte of written data, and the read check code can be generated for each byte of read data. Of course, it can also be adjusted according to the precision requirements of data verification. For example, a write check code can be generated for a write dataset described in the above embodiment. This embodiment does not impose any limitations on this.

[0056] It should be noted that the data transmitted by the on-chip high-speed bus 130 is usually a multi-byte data stream, and data writing must be completed before data reading can be performed. Based on this, during the process of writing data through the on-chip high-speed bus 130, the check code generator 210 generates a corresponding write check code for each byte of written data it obtains, and then saves it to the check code memory 220. During the process of reading data through the on-chip high-speed bus 130, the check code generator 210 generates a corresponding read check code for each byte of read data it obtains, and then matches the corresponding write check code from the check code memory 220 according to the access address, and performs data verification through the checker 230.

[0057] It is understood that the checksum memory 220 only needs to store write checksums and does not need to store read checksums. In this embodiment, the read state of the on-chip high-speed bus 130 is used as the trigger for data verification. When the on-chip high-speed bus 130 is in the write state, a write checksum is generated based on the write data and stored in the checksum memory 220. When the on-chip high-speed bus 130 switches to the read state, the checksum generator 210 can directly send each read checksum generated to the verifier 230. The checksum memory 220 simultaneously obtains the corresponding write checksum and sends it to the verifier 230. After obtaining the read checksum and write checksum of the same access address, the verifier 230 performs data verification, thereby realizing dynamic data verification and improving the efficiency of data verification.

[0058] It should be noted that since both the write checksum and the read checksum are generated by the checksum generator 210, and given that the checksum generation algorithm of the checksum generator 210 is the same, the read checksum and the write checksum corresponding to the same data will be identical. Therefore, the verifier 230 can perform data verification by checking whether the write checksum and the read checksum are the same. For example, for a byte of data, which typically includes multiple numerical values, the verifier 230 can perform data verification by comparing the values ​​bit by bit, or it can perform data verification through logical operations, such as performing an XOR operation. If the result of each bit is 0, it means that the two sets of data are the same. Those skilled in the art will have the motivation to choose the data verification algorithm according to actual needs, and this embodiment does not impose any limitations on this.

[0059] Additionally, in one embodiment, reference is made to Figure 1 and Figure 2 The check code memory 220 is connected to the bus interface 140. The check code memory 220 is also used to obtain and record the access address of write data, and to obtain the access address of read data and send the write check code corresponding to the same access address as the read data to the checker 230.

[0060] It should be noted that in this embodiment, the write checksum and read checksum for data verification correspond to the same access address. To facilitate matching, the checksum memory 220 can be connected to the bus interface 140. Whenever the checksum generator 210 obtains write data and generates a write checksum, the checksum memory 220 obtains the access address corresponding to the current write data from the on-chip high-speed bus 130 through the bus interface 140, and associates and saves the access address with the corresponding write checksum. That is, each set of stored data stored in the checksum memory 220 is [write checksum, access address]. When the checksum generator 210 generates a read checksum based on the current read data, the checksum memory 220 obtains the current access address from the on-chip high-speed bus 130 through the bus interface 140, matches the corresponding write checksum in the stored data according to the current access address, and sends it to the verifier 230 for data verification.

[0061] Additionally, in one embodiment, reference is made to Figure 1 and Figure 2 The verifier 230 is also used to: correct the read data according to the write data when the result of the data verification indicates that the verification fails, or send an error report to the host device 110, the error report including the read data that failed the verification and the address information of the corresponding access address.

[0062] It should be noted that when the read check code and the write check code are different, the data verification result will be a failure, which may be due to a data toggle error on the on-chip high-speed bus 130. Since the write data is obtained before being written to the on-chip high-speed bus 130, it can be ensured that the write data is correct. In this case, the write data can be used as a reference to identify the data bits with different values ​​in the read data as erroneous data bits. If the number of erroneous data bits is small, the read data can be corrected based on the write data. For example, the values ​​of the erroneous data bits in the read data can be modified to the values ​​of the corresponding data bits in the write data, and the corrected decoded read data can be updated to the corresponding slave device to improve the error correction capability of the on-chip high-speed bus data verification system.

[0063] It should be noted that when the number of erroneous data bits is large, the reliability of correction based on the written data is not high. An error report can be sent to the host device 110, sending the erroneous read data and the corresponding access address information to the host device 110. The host device 110 processes the erroneous read data and refreshes the status register, thereby correcting the read data. Through the technical solution of this embodiment, error correction can be achieved for read data with a small number of erroneous data bits, and reporting processing can be performed for read data with a large number of erroneous data bits, improving the reliability and error correction capability of the on-chip high-speed bus data verification system.

[0064] In some embodiments, the check code memory 220 is an on-chip random access memory.

[0065] It should be noted that the check code memory is an on-chip random access memory that can read and write data at any time, and the read and write speed is relatively fast. It can switch the read and write state at any time on the on-chip high-speed bus to ensure the efficiency of writing check codes and storing and reading memory addresses.

[0066] based on Figure 1 and Figure 2 The on-chip high-speed bus data verification system shown below will be explained in detail below, along with the principle of the on-chip high-speed bus data verification method provided in the embodiments of this application. (Refer to...) Figure 3 , Figure 3 The flowchart of the on-chip high-speed bus data verification method provided in the embodiments of this application includes, but is not limited to, the following steps 310 to 320.

[0067] Step 310: When the host device reads and writes data with the slave device through the on-chip high-speed bus, the write data and read data of the on-chip high-speed bus are obtained through the error detection and correction module.

[0068] Step 320: Perform data verification on write data and read data with the same access address, where the access address is used to indicate the storage location of the slave device.

[0069] It should be noted that when a chip has multiple master devices and multiple slave devices, data between each master device and any slave device is transmitted via the on-chip high-speed bus. Therefore, the error detection and correction module of this application is connected to the on-chip high-speed bus via the bus interface, enabling it to obtain data transmitted between any master device and any slave device from the on-chip high-speed bus. This embodiment, by connecting the error detection and correction module to the on-chip high-speed bus, allows the data verification logic to be deployed within the error detection and correction module. This eliminates the need to design verification logic in the controller of each device. By directly connecting the error detection and correction module to the chip's existing structure, data protection for slave devices on the on-chip high-speed bus can be achieved, improving the stability and anti-interference capability of the entire on-chip high-speed bus data verification system and simplifying the overall system design.

[0070] It should be noted that, to ensure that the read data and write data used for data verification are the same data, this embodiment uses the access address as the matching basis, so that the read data and write data both correspond to the same storage location of the slave device 120. For example, after writing write data A to location 1 of slave device 1, and then reading read data A from location 1 of slave device 1 and reading read data B from location 1 of slave device 2, the location 1 of slave device 1 is used as the matching basis to verify the write data A and read data A. The specific form of the access address can be selected according to actual needs, and this embodiment does not impose any limitations on it.

[0071] It should be noted that this embodiment uses the access address as the basis to match the corresponding read and write data for data verification. This can effectively distinguish the data stored in different slave devices, ensuring accurate matching of read and write data that can be verified. As a result, the number of master and slave devices can be arbitrarily adjusted in the chip, and the error detection and correction module can be directly ported to other chips for use, as long as the verification logic is consistent. This effectively improves the portability of the on-chip high-speed bus data verification system, and also simplifies the configuration process and debugging time of the verification logic, reducing development costs.

[0072] It should be noted that since write data and read data are usually transmitted in bytes on the on-chip high-speed bus, write data and read data can be one byte of data. Of course, if there is a need for actual data verification, the technical solution of this embodiment can also be implemented for the dataset, such as performing data verification on the write dataset and read dataset of a certain storage area. Those skilled in the art know that the technical solution disclosed in this embodiment can be extended, and the amount and scale of read data and write data are not limited here.

[0073] In another embodiment, the error detection and correction module further includes a checksum memory, a checksum generator, and a verifier. The checksum generator is connected to both the bus interface and the checksum memory, and the verifier is connected to both the checksum generator and the checksum memory. The checksum memory is also connected to the bus interface. (Refer to...) Figure 4 The method in this embodiment also includes, but is not limited to, the following steps:

[0074] Step 410: When the on-chip high-speed bus is in write state, the check code generator obtains the write data of the on-chip high-speed bus, generates a write check code based on the write data and sends it to the check code memory for storage, and records the access address of the write data through the check code memory, and associates and saves the access address of the write check code and the write data.

[0075] Step 420: When the on-chip high-speed bus is in read mode, the check code generator obtains the read data of the on-chip high-speed bus, generates a read check code based on the read data and sends it to the checker. The check code memory obtains the access address of the read data and sends a write check code corresponding to the same access address as the read data to the checker. The checker performs data verification on the obtained read check code and write check code.

[0076] It should be noted that the checksum generator can be connected to the on-chip high-speed bus via the bus interface, thereby acquiring data when the on-chip high-speed bus is in write or read state. For example, when the on-chip high-speed bus is in write state, the write data in the on-chip high-speed bus is simultaneously transmitted to the slave device and the checksum generator, and the checksum generator generates a write checksum based on the acquired write data; the same applies when the on-chip high-speed bus is in read state, which will not be repeated here.

[0077] It should be noted that, in order to improve the accuracy of data verification, the write check code can be generated for each byte of written data, and the read check code can be generated for each byte of read data. Of course, it can also be adjusted according to the precision requirements of data verification. For example, a write check code can be generated for a write dataset described in the above embodiment. This embodiment does not impose any limitations on this.

[0078] It should be noted that the data transmitted via the on-chip high-speed bus is usually a multi-byte data stream, and data writing must be completed before data reading can be performed. Based on this, during the process of writing data through the on-chip high-speed bus, the checksum generator generates a corresponding write checksum for each byte of written data and saves it to the checksum memory. During the process of reading data through the on-chip high-speed bus, the checksum generator generates a corresponding read checksum for each byte of read data, matches the corresponding write checksum from the checksum memory according to the access address, and performs data verification through the checksum reader.

[0079] It is understandable that the checksum memory only needs to store write checksums and does not need to store read checksums. In this embodiment, the read state of the on-chip high-speed bus is used as the trigger for data verification. When the on-chip high-speed bus is in write state, a write checksum is generated based on the write data and stored in the checksum memory. When the on-chip high-speed bus switches to read state, the checksum generator can directly send each read checksum generated to the checker. The checksum memory simultaneously obtains the corresponding write checksum and sends it to the checker. After the checker obtains the read checksum and write checksum of the same access address, it performs data verification, thereby realizing dynamic data verification and improving the efficiency of data verification.

[0080] It should be noted that since both the write checksum and the read checksum are generated by the checksum generator, and the checksum generation algorithm of the checksum generator is the same, the read checksum and the write checksum corresponding to the same data will be the same. Therefore, the verifier can verify the data by checking whether the write checksum and the read checksum are the same. For example, for a byte of data, which usually includes multiple numerical values, the verifier can compare the values ​​bit by bit for data verification, or it can perform data verification through logical operations, such as XOR operations. If the result of each bit is 0, it means that the two sets of data are the same. Those skilled in the art will have the motivation to choose the data verification algorithm according to actual needs, and this embodiment will not limit it in this way.

[0081] It should be noted that in this embodiment, the write checksum and read checksum for data verification correspond to the same access address. To facilitate matching, the checksum memory can be connected to the bus interface. Whenever the checksum generator obtains write data and generates a write checksum, the checksum memory obtains the access address corresponding to the current write data from the on-chip high-speed bus through the bus interface, and associates and saves the access address with the corresponding write checksum. That is, each set of stored data stored in the checksum memory is [write checksum, access address]. When the checksum generator generates a read checksum based on the current read data, the checksum memory obtains the current access address from the on-chip high-speed bus through the bus interface, matches the corresponding write checksum in the stored data according to the current access address, and sends it to the verifier for data verification.

[0082] Additionally, in one embodiment, reference is made to Figure 5 , Figure 4 Step 420 shown also includes, but is not limited to, the following steps:

[0083] Step 510: Perform an XOR operation on the obtained read check code and write check code;

[0084] Step 520: When the result of the XOR operation indicates that the obtained read check code and write check code are the same, the result of the data verification is determined to be that the verification is successful.

[0085] It's important to note that data verification determines whether the read and write data are identical. Since both the read and write check codes are generated by a check code generator, if they are the same, the read and write data are confirmed to be identical, and the data verification passes. To verify the similarity of longer check codes, a bitwise XOR operation can be performed on them. The result is 0 if the two check codes are the same, and 1 if they are different. For example, if both the read and write check codes consist of 7 bits, the XOR operation will also result in 7 bits, all of which are 0. If this results in a pass, the verification passes. If the 7 bits include the value 1, the data verification fails.

[0086] In another embodiment, when the result of the XOR operation indicates that the obtained read check code and write check code are different, refer to Figure 6 , Figure 4 Step 420 shown also includes, but is not limited to, the following steps:

[0087] Step 610: Decode the obtained read check code and write check code to obtain decoded read data and decoded write data;

[0088] Step 620: Determine the erroneous data bits of the decoded data based on the result of the XOR operation;

[0089] Step 630: When the number of erroneous data bits is less than or equal to a preset threshold, correct the decoded read data according to the decoded write data, and update the corrected decoded read data to the slave device through the on-chip high-speed bus;

[0090] Step 640: When the number of erroneous data bits exceeds a preset threshold, an error report is sent to the host device via the on-chip high-speed bus. The error report includes the decoded read data and the address information of the corresponding access address.

[0091] It should be noted that when the read check code and the write check code are different, the data verification result is a failure, which may be due to a data flip error on the on-chip high-speed bus. Since the write data is obtained before being written to the on-chip high-speed bus, it can be ensured that the write data is correct. In this case, the read check code and the write check code can be decoded to obtain the corresponding decoded read data and decoded write data. Based on the data verification through XOR operation, the data bits with the result of XOR operation being 1 can be identified as erroneous data bits.

[0092] It should be noted that when the number of erroneous data bits is small, the decoded read data can be corrected based on the decoded write data. For example, the value of the erroneous data bit in the decoded read data can be modified to the value of the corresponding data bit in the decoded write data, and the corrected decoded read data can be updated to the corresponding slave device, thereby improving the error correction capability of the on-chip high-speed bus data verification system.

[0093] It should be noted that when the number of erroneous data bits is large, the reliability of correction based on decoded write data is not high. An error report can be sent to the host device, sending the erroneous decoded read data and the corresponding access address information to the host device. The host device processes the erroneous decoded read data and refreshes the status register, thereby correcting the read data. Through the technical solution of this embodiment, error correction can be achieved for read data with a small number of erroneous data bits, and reporting processing can be performed for read data with a large number of erroneous data bits, improving the reliability and error correction capability of the on-chip high-speed bus data verification system.

[0094] In another embodiment, the checksum generator generates a write checksum or a read checksum using the BCH encoding / decoding algorithm.

[0095] It should be noted that the write check code and read check code obtained through the BCH encoding and decoding algorithm can be used to correct multi-level, cyclic, error-correcting, and variable-length digital codes with multiple random error modes, with high accuracy. At the same time, the BCH encoding and decoding algorithm is also easy to decode, allowing the write check code and read check code to be decoded separately to obtain decoded write data and decoded read data, thus improving the efficiency of error detection and correction in the on-chip high-speed bus data verification system.

[0096] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the system electronic device, can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0097] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0098] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0100] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0102] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0103] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing electronic device (such as a personal computer, server, touch terminal, or network electronic device, etc.) to execute the method according to the embodiments of this application.

[0104] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0105] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0106] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A data verification system for an on-chip high-speed bus, comprising a host device, a slave device, an on-chip high-speed bus, and a bus interface, wherein the host device and the slave device are connected to the on-chip high-speed bus, and the on-chip high-speed bus is used for data transmission between the host device and the slave device, characterized in that, Also includes: An error detection and correction module is connected to the on-chip high-speed bus via a bus interface. When the host device reads or writes data to the slave device via the on-chip high-speed bus, the error detection and correction module is used to obtain the write data and read data of the on-chip high-speed bus, and to perform data verification on the write data and read data with the same access address, wherein the access address is used to indicate the storage location of the slave device. The error detection and correction module includes: A checksum generator is provided, which is connected to the bus interface. When the on-chip high-speed bus is in write mode, the checksum generator obtains the write data of the on-chip high-speed bus through the bus interface and generates a write checksum. When the on-chip high-speed bus is in read mode, the checksum generator obtains the read data of the on-chip high-speed bus through the bus interface and generates a read checksum. The checksum generator can generate the write checksum or the read checksum using the BCH encoding and decoding algorithm. A verification code storage device is connected to the verification code generator, and the verification code storage device is used to store the write verification code; A verifier is connected to the checksum generator and the checksum memory, and the verifier is used to perform data verification on the read checksum and the write checksum that have the same access address. The check code memory is connected to the bus interface. The check code memory is also used to acquire and record the access address of the write data, acquire the access address of the read data, and send the write check code corresponding to the same access address as the read data to the checker.

2. The on-chip high-speed bus data verification system according to claim 1, characterized in that, The verifier is also used to: when the result of data verification indicates that the verification fails, correct the read data according to the write data, or send an error report to the host device, the error report including the read data that failed verification and the address information of the corresponding access address.

3. The on-chip high-speed bus data verification system according to claim 1, characterized in that, The checksum memory is an on-chip random access memory.

4. A method for verifying on-chip high-speed bus data, applied to the on-chip high-speed bus data verification system according to any one of claims 1 to 3, wherein the error detection and correction module further includes a checksum memory, a checksum generator, and a verifier, wherein the checksum generator is connected to the bus interface and the checksum memory respectively, the verifier is connected to the checksum generator and the checksum memory respectively, and the checksum memory is also connected to the bus interface, wherein the method for verifying on-chip high-speed bus data includes: When the host device reads and writes data with the slave device through the on-chip high-speed bus, the write data and read data of the on-chip high-speed bus are obtained through the error detection and correction module. Data verification is performed on the write data and the read data that have the same access address, wherein the access address is used to indicate the storage location of the slave device; When the on-chip high-speed bus is in write mode, the check code generator obtains the write data of the on-chip high-speed bus, generates a write check code based on the write data and sends it to the check code memory for storage, and records the access address of the write data through the check code memory, and associates and saves the write check code and the access address of the write data. When the on-chip high-speed bus is in read mode, the check code generator obtains the read data of the on-chip high-speed bus, generates a read check code based on the read data and sends it to the checker. The check code memory obtains the access address of the read data and sends the write check code corresponding to the same access address as the read data to the checker. The checker performs data verification on the obtained read check code and the write check code. The checksum generator generates the write checksum or the read checksum using the BCH encoding / decoding algorithm.

5. The method for verifying on-chip high-speed bus data according to claim 4, characterized in that, The step of verifying the data using the verifier on the obtained read verification code and write verification code includes: Perform an XOR operation on the obtained read check code and write check code; When the result of the XOR operation indicates that the obtained read check code and the write check code are the same, the result of the data verification is determined to be that the verification is successful.

6. The method for verifying on-chip high-speed bus data according to claim 4, characterized in that, When the result of the XOR operation indicates that the obtained read check code and the write check code are different, the method further includes: The obtained read check code and write check code are decoded to obtain decoded read data and decoded write data; The error data bits of the decoded read data are determined based on the result of the XOR operation; When the number of erroneous data bits is less than or equal to a preset threshold, the decoded read data is corrected according to the decoded write data, and the corrected decoded read data is updated to the slave device through the on-chip high-speed bus. or, When the number of error data bits exceeds a preset threshold, an error report is sent to the host device via the on-chip high-speed bus. The error report includes the decoded read data and the address information of the corresponding access address.

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