A method for splitting a high-fanout netlist, an electronic device, and a storage medium

Abstract

The application discloses a method for splitting a high-fanout netlist, an electronic device and a storage medium, comprising the following steps: dividing the netlist into several levels according to the receiver coordinates and the distance of the source node; clustering each level from far to near according to a preset constraint; connecting the buffer generated by the clustering of the level closest to the source node directly to the source node, and adding the buffer generated by the clustering of each other level to the clustering of the adjacent next level, and creating a topology tree to guide the wiring of the netlist of the several levels on a 2D grid. The application can increase the parallel degree of the algorithm, reduce the running time of the algorithm, reduce the subsequent optimization time, reduce the difficulty of subsequent Detail Place, and reduce the running time of the algorithm.

Description

Technical Field

[0001] This application relates to the field of EDA technology, and more specifically to a method for splitting a high fanout netlist, an electronic device, and a storage medium. Background Technology

[0002] Currently, the main methods for solving high fan-out netlists involve dividing the process into several stages. The first stage uses delay models (such as liner delay models, continuous delay models, and Elmore delay models) to divide the nets to be processed into different levels based on their delay values. The second stage uses dynamic programming algorithms and pruning strategies to optimize the generated tree structure. This stage also considers the influence of polarity to ensure correct polarity during the process, thereby guaranteeing the correctness of the circuit function. The third stage uses coarse-grained sizing operations, selecting up-sizing or down-sizing of inserted buffers or logic units already present in the circuit from a specified cell list. This aims to achieve smaller delay, area, and power consumption performance metrics.

[0003] The above algorithms aim to optimize delay, buffer size, area, and some design violations. Current algorithms have the following problems:

[0004] (1) Currently, the processing of high fanout nets is still only in logic synthesis, without considering the application of coordinates in the place phase, which greatly increases the burden on the place tool.

[0005] (2) Large nets take a long time to build. Large nets with large bounding boxes also have a large search space, which makes the tree building algorithm run relatively slowly.

[0006] (3) The parallelism of the algorithm is insufficient. When considering coordinates, when dealing with such high fanout nets, if the bounding boxes of two nets do not overlap and their logical relationships do not intersect, they can be processed simultaneously on different threads. The current algorithm does not take this into account.

[0007] (4) Consideration of insufficient constraints. Constraints in practical applications are more stringent. In addition to considering the delay relationship, timing constraints such as cap and slew, as well as design constraints such as area, density, and power, need to be considered in the actual algorithm execution.

[0008] The background description is provided for the purpose of understanding the relevant technologies in this field and is not intended as an admission of prior art. Summary of the Invention

[0009] Therefore, embodiments of the present invention aim to provide a method, electronic device, and storage medium for splitting a high fanout netlist.

[0010] In a first aspect, embodiments of the present invention provide a method for splitting a high fanout netlist, comprising:

[0011] The netlist is divided into several levels based on the distance between the receiver coordinates and the source node;

[0012] Clustering is performed on each level from farthest to nearest according to preset constraints;

[0013] The buffer generated by the clustering level closest to the source node is directly connected to the source node, while the buffer generated by each other clustering level is added to the clustering level of the next adjacent level. A topology tree is created to guide the routing of the netlists of the several levels on a 2D mesh.

[0014] In one embodiment, the step of dividing the netlist into several levels based on the distance between the receiver coordinates and the source node includes:

[0015] Disconnect the netlist receiver coordinates from the source node;

[0016] Each pin is layered based on its location on the netlist.

[0017] In one embodiment, the netlist is divided into several levels based on the distance between the receiver coordinates and the source node, and the formula for calculating the distance between the receiver coordinates and the source node is as follows:

[0018] Distance i =anhattan(source) x -sink i .)+anhattan(source y -sink i .)

[0019] Among them, Distance i Manhattan(source) is the distance between the receiver coordinates and the source node. x -sink i The x-coordinate of the source node is represented by .x, which is the Manhattan distance from the x-coordinate of the current receiver. y -sink i .y) represents the Manhattan distance from the ordinate of the source node to the ordinate of the current receiver.

[0020] In one embodiment, after clustering each level sequentially from farthest to nearest according to preset constraints, the method further includes:

[0021] Topology optimization is performed on each level after clustering based on temporal constraints and B-box constraints.

[0022] In one embodiment, the topology optimization of each level after clustering based on temporal constraints and B-box constraints includes:

[0023] Based on the relationship between the hierarchy and the source node, each hierarchy is clustered from farthest to nearest;

[0024] Based on the clustering results, a new netlist is generated for the sink coordinates of each cluster. Typically, one Level-sink will generate multiple Sinks-nets.

[0025] For each cluster, a driving cell is given as the current source node, and the source node will be added to the next level under certain constraints.

[0026] In one embodiment, a new netlist is generated for each cluster of receiver coordinates, and the number of clusters generated by the clustering algorithm is equal to the number of new netlists.

[0027] In one embodiment, directly connecting the buffer generated by the hierarchical clustering closest to the source node to the source node includes:

[0028] The distance between the source node and the hierarchical cluster is obtained according to the distance calculation formula;

[0029] The buffer generated by selecting the hierarchical cluster closest to the source node is directly connected to the source node.

[0030] In one embodiment, after guiding the routing of the netlists at several levels on a 2D mesh by creating the topology tree, the method further includes:

[0031] Disconnect each level from the original connection to the topology tree, and establish new connections according to the routing guidelines.

[0032] In a second aspect of this invention, an embodiment of the invention provides a storage medium storing a computer program thereon, wherein the program, when run by a processor, implements the method for splitting a high fanout netlist according to any embodiment of the invention.

[0033] In a third aspect, embodiments of the present invention provide an electronic device, including: a processor and a memory storing a computer program, the processor being configured to execute, when running the computer program, a method for splitting a high fanout netlist according to any embodiment of the present invention.

[0034] In the method of splitting high fan-out netlists used in this embodiment of the invention, the chance of bounding box overlap between small netlists is reduced, the probability of parallel operation between them is increased, and the parallelism of the algorithm is increased; the layout optimization speed of small netlists is faster, reducing the running time of the algorithm; the driving capability of the driving unit in each netlist is strengthened, the timing constraint violation behavior is reduced, and the subsequent optimization time is reduced; the difficulty of subsequent Detail Place is reduced, and the running time of the algorithm is reduced.

[0035] Other optional features and technical effects of the embodiments of the present invention are partly described below and partly apparent from reading this document. Attached Figure Description

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The elements shown are not limited to the scale shown in the drawings, and the same or similar reference numerals in the drawings denote the same or similar elements, wherein:

[0037] Figure 1 An example flowchart of a method for splitting a high fanout netlist according to an embodiment of the present invention is shown;

[0038] Figure 2 A flowchart illustrating a specific implementation example of a method for splitting a high fanout netlist according to an embodiment of the present invention is shown;

[0039] Figure 3 An application topology diagram of a method for splitting a high fanout netlist according to an embodiment of the present invention is shown;

[0040] Figure 4 An exemplary structural schematic diagram of an electronic device capable of implementing the method according to an embodiment of the present invention is shown. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0042] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0043] In logic synthesis, existing methods for solving high-fanout nets divide the process into several stages. The first stage uses delay models (such as liner delay models, continuous delay models, and Elmore delay models) to divide the net into different levels based on its delay value. The second stage uses dynamic programming algorithms and pruning strategies to optimize the generated tree structure. This stage also considers the influence of polarity to ensure correct polarity during the process, thereby guaranteeing the correctness of the circuit function. The third stage uses coarse-grained sizing to select up-sizing or down-sizing of inserted buffers or logic units already present in the circuit from a specified cell list. This aims to achieve smaller delay, area, and power consumption performance metrics.

[0044] The above algorithms aim to optimize delay, buffer size, area, and some design violations. Current algorithms have the following problems:

[0045] 1. Currently, the handling of high fanout nets is still limited to logic synthesis, without considering coordinate application in the place phase, which greatly increases the burden on the place tool.

[0046] 2. Large nets take a long time to build. Nets with large bounding boxes also have large search spaces, resulting in slower tree-building algorithms.

[0047] 3. The algorithm lacks parallelism. When considering coordinates, when processing high fanout nets, if two nets have non-overlapping bounding boxes and no intersecting logical relationships, they can be processed simultaneously on different threads. The current algorithm does not take this into account.

[0048] Insufficient constraints need to be considered. In practical applications, our constraints are more stringent. We need to consider not only the delay relationship, but also timing constraints such as cap and slew, as well as design constraints such as area, density, and power during the actual algorithm execution.

[0049] In this application, "net" refers to the netlist and "source" refers to the source node.

[0050] The technical solution of this application can be summarized as follows: A large net is divided into many smaller nets using a clustering algorithm. Based on coordinates and design constraints, these smaller nets are gradually merged together, thus rationalizing the topology, optimizing the number of buffers, and improving area, thereby solving the aforementioned technical problems.

[0051] In embodiments of the present invention, such as Figure 1 As shown, a method for splitting a high fanout netlist is provided.

[0052] like Figure 1 As shown, in step S101, the netlist is divided into several levels based on the distance between the receiver coordinates and the source node. Next, proceed to step S102.

[0053] In step S102, clustering is performed on each level sequentially from farthest to nearest according to preset constraints. Next, proceed to step S103.

[0054] In step S103, the buffer generated by the clustering of the level closest to the source node is directly connected to the source node, while the buffer generated by each other clustering level is added to the cluster of the next adjacent level, creating a topology tree to guide the routing of the netlists of the several levels on the 2D grid.

[0055] In this embodiment, step S101, which divides the netlist into several levels based on the distance between the receiver coordinates and the source node, may specifically include: disconnecting the connection between the netlist receiver coordinates and the source node; and layering each pin according to the pin positions connected on the netlist.

[0056] It should be noted that the nets split in this application are selected from those with larger fanouts (the specific value can be adjusted as an algorithm parameter, or a suitable value can be calculated based on the characteristics of high-fanout nets in the input netlist). In the actual implementation process, it is possible that most or even all sinks are located very close to the source. To deal with this extreme case, a buffer can be added or some sinks can be directly connected to the source node, depending on the actual driving performance, in order to reduce the buffer and reduce area consumption.

[0057] The clustering algorithm in step S102 can be other clustering algorithms, including k-means clustering, K-centroids, DIANA, EM, etc., and those skilled in the art can choose according to actual needs.

[0058] In this embodiment, directly connecting the buffer generated by the hierarchical cluster closest to the source node to the source node includes: obtaining the distance between the source node and the hierarchical cluster according to the distance calculation formula; and directly connecting the buffer generated by the hierarchical cluster closest to the source node to the source node. For example, the levels closer to the source node are called high-level levels, and the levels farther from the source node are called low-level levels. After the algorithm reaches the high-level level, it will switch to creating a straight Steiner tree to guide the routing of all high-level levels on the 2D mesh, and then add a buffer at the appropriate branching point according to the routing result.

[0059] Furthermore, in step S101, the netlist is divided into several levels based on the distance between the receiver coordinates and the source node. The formula for calculating the distance between the receiver coordinates and the source node is as follows:

[0060] Distance i =anhattan(source) x -sink i .)+anhattan(source y -sink i .)

[0061] Among them, Distance i Manhattan(source) is the distance between the receiver coordinates and the source node. x -sink i The x-coordinate of the source node is represented by .x, which is the Manhattan distance from the x-coordinate of the current receiver. y -sink i .y) represents the Manhattan distance from the ordinate of the source node to the ordinate of the current receiver.

[0062] In step S101, the specific method is as follows: First, a relatively large netlist (Super-net) is selected. Then, for each selected high fanout net, the connection between the source and the pin is disconnected. Based on the position of the pins connected in the netlist, a layering method is used to perform layering operations on each pin. The size of the layer is determined according to the actual design, process dimensions, and given buffer. After this step, each level sink is called a Level-sink.

[0063] Optionally, after clustering each level according to preset constraints as described in this embodiment, the method further includes: performing topology optimization on each clustered level according to temporal constraints and B-box constraints. Specifically, performing topology optimization on each clustered level according to temporal constraints and B-box constraints includes: clustering each level from farthest to nearest based on the relationship between the level and the source node; generating a new netlist for the receiver coordinates of each cluster based on the clustering results (typically, one level-sink will generate multiple sinks-nets); assigning a driving cell as the current source node for each cluster, and the source node will be added to the next level under certain constraints.

[0064] Specifically, in this embodiment, a new netlist is generated for each clustered receiver coordinate, and the number of clusters generated by the clustering algorithm is equal to the number of new netlists.

[0065] In this embodiment, the specific steps involve performing a clustering algorithm on the Level-sinks from farthest to nearest, based on the relationship between the level and the source node. According to the clustering results, a new net is generated for each clustered sink (receiver coordinates). The number of new netlists (Sinks-nets) generated corresponds to the number of clusters generated by the clustering algorithm. Typically, one Level-sink will generate multiple Sinks-nets. For each cluster, a driving cell is given as the current source node (usually the driving cell is a buffer), and the source node will be added to the next level (the level closest to the source) under certain constraints. Furthermore, each cluster has temporal constraints such as cap slew.

[0066] For each cluster, the following constraints apply:

[0067]

[0068] Where C buffer `cap` is the maximum output cap for a given driver unit, and `ratio` is a given scaling factor (we set it to 0.8 based on experiments). `RSMT(sinks)` is the estimated trace length of the wiring obtained by creating a straight Steiner tree, and `cap` is the given cell capacitance value. cap It is the input cap of the sink in the current cluster.

[0069] In the aforementioned steps, the connection relationship of Sinks-net in Level-sinks has been determined from far to near. At the same time, each Sink-net will have a driving cell moving towards the upper level. Based on the performance in experiments and actual processes, the boundary box constraints are set, and the distance between each driving cell and the boundary box cannot exceed or be too much greater than the distance between the two levels.

[0070] For the defined driving cell, the following constraints apply:

[0071]

[0072]

[0073] X+Y=MIN(Manhattan(source x -X)+MIN(Manhattan(source Y -Y))

[0074] Where X is the x-coordinate of the driving cell and Y is the y-coordinate of the driving cell. x This represents the x-coordinate of the sink in the current cluster. y This represents the ordinate of the sink in the current cluster.

[0075] Finally, the topology results from the preceding steps are integrated to form a final Sinks-net into a final topology tree. Furthermore, after creating the topology tree and guiding the routing of the netlists at several levels on a 2D mesh, the process further includes: disconnecting the original connections between each level and the topology tree, and establishing new connections based on the guided routing.

[0076] After clustering and splitting, each net becomes smaller (with a smaller bounding box), which has the following advantages compared to existing algorithms:

[0077] 1. The chance of overlapping bounding boxes between small nets is reduced, the probability of parallel operation between them is increased, and the parallelism of the algorithm is increased.

[0078] 2. Smaller net layouts are optimized faster, reducing the algorithm's runtime.

[0079] 3. The driving capability of the driving unit in each net is enhanced, timing constraint violations are reduced, and subsequent optimization time is decreased.

[0080] 4. By considering the coordinates of the place, the difficulty of subsequent Detail Place calculations is reduced, thus decreasing the algorithm's runtime.

[0081] 5. In traditional logic synthesis processing of high fan-out nets, the topology results are often difficult to apply to the place results, which ultimately leads to a deterioration of the overall topology structure, with larger area, power, and drv values, thereby reducing the performance of the design.

[0082] like Figure 2 As shown, in step S201, the layers are divided according to the distance between the source and the sink. Next, proceed to step S202.

[0083] In step S202, each level is clustered according to the constraints. Next, proceed to step S203.

[0084] In step S203, each cluster at the lower level creates a driver cell to be added to the next level. Next, proceed to step S204.

[0085] In step S204, the topology is optimized using timing constraints and B-box constraints. Next, proceed to step S205.

[0086] In step S205, the high-level clustering method is adjusted, and the Flute algorithm is run to guide the topology results. Specifically:

[0087] The application topology diagram of this embodiment is as follows: Figure 3As shown in the diagram. First, during the layout phase, a Super-net with a fanout greater than the specified value is selected. The network is first divided into four levels: L1, L2, L3, and L4, based on the distance from the sink to the source. Then, sinks in each level are processed from farthest to closest. A clustering algorithm is performed starting from L4, generating clusters such as L4sinks d1 and L4sinks d2. A driving node is generated for each cluster, and buffer a is placed there. If the current buffer is too far from the previous level, a buffer b connecting buffer a is added, and the network is moved to the next level (3), repeating this process. Later, as the network moves upwards, when a generated buffer or an existing sink gets close to the source, the clustering operation stops. Through steps such as creating a straight-line Steiner tree and dynamic programming, the connection relationships between nodes close to the source are determined (i.e., the dashed lines), and appropriate buffers are added. Finally, the original connections between each level and the determined topology are broken, and new connections are generated (i.e., the dashed lines in the diagram). In this case, for areas that cannot be laid out, buffer units will be avoided as much as possible during the layout process.

[0088] In this embodiment of the invention, a storage medium is provided on which a computer program is stored, wherein the program is executed by a processor to implement the method of splitting a high fanout netlist according to any embodiment of the invention.

[0089] This invention provides an electronic device, including: a processor and a memory storing a computer program, wherein the processor is configured to execute a method for splitting a high fanout netlist according to any embodiment of this invention when running the computer program.

[0090] In the method of splitting high fan-out netlists used in this embodiment of the invention, the chance of bounding box overlap between small netlists is reduced, the probability of parallel operation between them is increased, and the parallelism of the algorithm is increased; the layout optimization speed of small netlists is faster, reducing the running time of the algorithm; the driving capability of the driving unit in each netlist is strengthened, the timing constraint violation behavior is reduced, and the subsequent optimization time is reduced; the difficulty of subsequent Detail Place is reduced, and the running time of the algorithm is reduced.

[0091] In some embodiments, the electronic device may incorporate a method feature of splitting a high fanout netlist according to any embodiment, and vice versa, which will not be elaborated here.

[0092] In an embodiment of the present invention, an electronic device is provided, comprising: a processor and a memory storing a computer program, wherein the processor is configured to execute a method for splitting a high fanout netlist according to any embodiment of the present invention when running the computer program.

[0093] Figure 4 The diagram illustrates a method for implementing embodiments of the present invention or an electronic device for implementing embodiments of the present invention. In some embodiments, more or fewer electronic devices may be included than illustrated. In some embodiments, implementation may be carried out using a single or multiple electronic devices. In some embodiments, implementation may be carried out using cloud-based or distributed electronic devices.

[0094] like Figure 4 As shown, the electronic device includes a processor 401, which can perform various appropriate operations and processes based on programs and / or data stored in read-only memory (ROM) 402 or programs and / or data loaded from storage portion 408 into random access memory (RAM) 403. The processor 401 may be a multi-core processor or may contain multiple processors. In some embodiments, the processor 401 may include a general-purpose main processor and one or more special coprocessors, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), digital signal processor (DSP), etc. Various programs and data required for the operation of the electronic device are also stored in RAM 403. The processor 401, ROM 402, and RAM 403 are interconnected via bus 404. An input / output (I / O) interface 405 is also connected to bus 404.

[0095] The processor and memory described above are used together to execute a program stored in the memory. When the program is executed by a computer, it can implement the methods, steps, or functions described in the above embodiments.

[0096] The following components are connected to I / O interface 405: an input section 406 including a keyboard, mouse, touchscreen, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. Drive 410 is also connected to I / O interface 405 as needed. Removable media 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 410 as needed so that computer programs read from them can be installed into storage section 408 as needed. Figure 4 The diagram only shows a portion of the components and does not imply that the computer system includes only these components. Figure 4 The components shown.

[0097] The systems, devices, modules, or units described in the above embodiments can be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, smartphone, personal computer, laptop computer, in-vehicle human-machine interface device, personal digital assistant, media player, navigation device, game console, tablet computer, wearable device, smart TV, Internet of Things system, smart home, industrial computer, server, or a combination thereof.

[0098] Although not shown, in this embodiment of the invention, a storage medium is provided storing a computer program configured to execute, when run, any file-difference-based compilation method of this embodiment of the invention.

[0099] Storage media in embodiments of the present invention include articles that are permanent and non-permanent, removable and non-removable, capable of storing information by any method or technology. Examples of storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0100] The methods, programs, systems, apparatuses, etc., in embodiments of the present invention can be executed or implemented in one or more networked computers, or practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected via a communication network.

[0101] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.

[0102] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of the present invention do not necessarily have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0103] This document describes several embodiments of the present invention; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to embodiments applicable to at least one, but not all, of the present invention. The above terms do not necessarily refer to the same embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples.

[0104] The exemplary systems and methods of the present invention have been specifically shown and described with reference to the above embodiments, which are merely examples of the best mode for implementing the systems and methods. Those skilled in the art will understand that various changes can be made to the embodiments of the systems and methods described herein without departing from the spirit and scope of the invention as defined in the appended claims when implementing the systems and / or methods.

Claims

1. A method for splitting a high fanout netlist, characterized in that, include: The netlist is divided into several levels based on the distance between the receiver coordinates and the source node; Clustering is performed on each level from farthest to nearest according to preset constraints; The buffer generated by the clustering level closest to the source node is directly connected to the source node, while the buffer generated by each other clustering level is added to the clustering level of the next adjacent level. A topology tree is created to guide the routing of the netlists of the several levels on a 2D mesh.

2. The method for splitting a high fanout netlist according to claim 1, characterized in that, The netlist is divided into several levels based on the distance between the receiver coordinates and the source node, including: Disconnect the netlist receiver coordinates from the source node; Each pin is layered based on its location on the netlist.

3. The method for splitting a high-fanout netlist according to claim 1, characterized in that, The netlist is divided into several levels based on the distance between the receiver coordinates and the source node. The formula for calculating the distance between the receiver coordinates and the source node is as follows: in, The distance between the receiver coordinates and the source node. This represents the Manhattan distance from the x-coordinate of the source node to the x-coordinate of the current receiver. This represents the Manhattan distance from the ordinate of the source node to the ordinate of the current receiver.

4. The method for splitting a high-fanout netlist according to claim 1, characterized in that, After clustering each level sequentially from farthest to nearest according to preset constraints, the method further includes: Topology optimization is performed on each level after clustering based on temporal constraints and B-box constraints.

5. The method for splitting a high fanout netlist according to claim 4, characterized in that, The topology optimization of each level after clustering based on temporal constraints and B-box constraints includes: Based on the relationship between the hierarchy and the source node, each hierarchy is clustered from farthest to nearest; Based on the clustering results, a new netlist is generated for the sink coordinates of each cluster. One Level-sinks will generate multiple Sinks-nets. For each cluster, a driving cell is given as the current source node, and the source node will be added to the next level under certain constraints.

6. The method for splitting a high fanout netlist according to claim 5, characterized in that, A new netlist is generated for each cluster of receiver coordinates, and the number of clusters generated by the clustering algorithm is equal to the number of new netlists.

7. The method for splitting a high fanout netlist according to claim 1, characterized in that, The step of directly connecting the buffer generated by the hierarchical clustering closest to the source node to the source node includes: The distance between the source node and the hierarchical cluster is obtained according to the distance calculation formula; The buffer generated by selecting the hierarchical cluster closest to the source node is directly connected to the source node.

8. The method for splitting a high-fanout netlist according to claim 1, characterized in that, After creating the topology tree and guiding the routing of the netlists at several levels on a 2D mesh, the method further includes: Disconnect each level from the original connection to the topology tree, and establish new connections according to the routing guidelines.

9. A storage medium having a computer program stored thereon, wherein, The program is executed by the processor to implement the method as described in any one of claims 1-8.

10. An electronic device, characterized in that, include: A processor and a memory storing a computer program, the processor being configured to implement the method of any one of claims 1-8 when the computer program is executed.

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