Interconnect short circuit location methods, system and layout design methods in chip design

Abstract

This invention discloses a method, system, and layout design method for locating short circuits in interconnects during chip design, relating to the field of semiconductor technology. The method includes performing an LVS (Low-Level Screen) check on the chip layout to determine if there are any short-circuited interconnects; if so, extracting layout data files of all short-circuited interconnects; and performing a design rule check on the layout data files according to customized DRC (Design Rule Check) rules to determine the location of the fault in the short-circuited interconnect. This invention efficiently solves the problem of locating short circuits in interconnects during chip design and is applicable to various chip design scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology. In particular, it relates to a method, system, and layout design method for locating short circuits in interconnects during chip design. Background Technology

[0002] In deep submicron process chip design, as the process technology shrinks and device density increases, the number of transistors in a System-on-a-Chip (SoC) grows exponentially. The interconnections between transistors become increasingly complex, making short-circuit issues on interconnects more prominent in SoC design. Therefore, quickly locating short circuits on interconnects is crucial for accelerating the design process, shortening the design cycle, and speeding up time-to-market.

[0003] However, the inventors of this application discovered in the process of realizing this invention that: in related technologies, such as Figure 1 As shown, the solution for locating short circuits in interconnects mainly involves adding markers to the interconnects. Specifically, markers are added to different layers and segments of the interconnects to help pinpoint the exact location of the short circuit. In practice, there are generally two marker schemes: one is to mark every interconnect, and the other is to mark only the short-circuited interconnect. However, both schemes have significant limitations and cannot truly and efficiently solve the problem of locating short circuits in interconnects during SOC design. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method, system, and layout design method for locating short circuits in interconnects during chip design, which can efficiently solve the problem of locating short circuits in interconnects during chip design.

[0005] This invention provides a method for locating short circuits in interconnects during chip design, comprising:

[0006] Perform an LVS check on the chip layout to determine whether there are any short-circuited interconnects in the chip layout;

[0007] If so, extract the layout data files of all interconnects with short circuits;

[0008] Based on the customized DRC rules, a design rule check is performed on the layout data file to determine the location of the fault in the interconnect with the short circuit.

[0009] According to a specific implementation of this application, the step of performing design rule checks on the layout data file according to customized DRC rules to determine the location of the faulty interconnect with short circuits includes: performing design rule checks on the graphics data system according to customized DRC rules to find locations where adjacent interconnects overlap in the same layer; determining the locations where adjacent interconnects overlap as the locations where the interconnects fail; obtaining all interconnects with short circuits and extracting the target graphics data system with short circuits from the SOC's graphics database; and customizing DRC rules for checking overlapping interconnects in the same layer.

[0010] According to a specific implementation of an embodiment of this application, performing an LVS check on the chip layout to determine whether there are short-circuited interconnects in the chip layout includes: extracting the netlist file of the chip layout; comparing the netlist file with the schematic netlist; if the comparison matches, there are no short circuits in the chip layout; if the comparison does not match, there are short circuits in the chip layout.

[0011] According to a specific implementation of this application, the step of extracting the layout data file of all interconnects with short circuits further includes: obtaining all interconnects with short circuits based on the LVS report obtained from the LVS inspection, and extracting the layout data file of the interconnects with short circuits from the graphics database.

[0012] According to a specific implementation of this application, before performing design rule checks on the graphics data system according to customized DRC rules, the method further includes: customizing DRC rules for checking for overlapping interconnects in the same layer.

[0013] According to a specific implementation of this application, the customized DRC rules for checking for overlapping interconnects in the same layer include: customized DRC rules for checking for partial inclusion, full inclusion, small corner positions, and / or changes in the line width of a single interconnect in adjacent interconnects in the same layer.

[0014] Secondly, embodiments of the present invention also provide an interconnect short-circuit location system in chip design, comprising: an LVS check program unit, used to perform an LVS check on the chip layout to determine whether there are short-circuited interconnects in the chip layout; an extraction program unit, used to extract layout data files of all short-circuited interconnects if any; and a fault location program unit, used to perform a design rule check on the layout data files according to customized DRC rules to determine the location where the short-circuited interconnect has failed.

[0015] Thirdly, the present invention also provides a chip layout design method, the method comprising: after the chip layout is initially designed, performing the interconnect short-circuit location method described in any of the first aspects during the LVS and DRC verification process. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the interconnection positioning method in the chip layout design process of related technologies.

[0018] Figure 2 A schematic flowchart of an interconnect short-circuit location method in chip design provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram illustrating a scenario where interconnects in a SOC system are short-circuited.

[0020] Figure 4 This is a schematic diagram illustrating another scenario of short circuits in interconnects within a SOC system.

[0021] Figure 5 A schematic flowchart of an interconnect short-circuit location method in chip design provided in another embodiment of this application;

[0022] Figure 6 A schematic flowchart of an interconnect short-circuit location method in chip design provided in another embodiment of this application;

[0023] Figure 7 A schematic diagram of an interconnect short-circuit location system architecture in a chip design provided in an embodiment of this application;

[0024] Figure 8 This is a schematic diagram of an electronic device structure according to an embodiment of this application. Detailed Implementation

[0025] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0026] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0027] To address the technical problem of low efficiency in locating short circuits in existing SOC designs, this invention provides a specific method for locating short circuits in chip design. This method quickly locates the short circuit in the interconnect, thereby accelerating the progress of LVS (layout versus schematic, used to check whether the layout and circuit diagram are consistent) inspection and shortening the SOC design time.

[0028] To aid in understanding the technical solutions provided by the embodiments of the present invention, a brief introduction to the technical terms involved in the various embodiments of the present invention is provided below before proceeding with a detailed description:

[0029] GDS stands for Graphical Data System. In integrated circuit layout design, GDS-II (stream format) is primarily used. GDS-II is a database file format used for data conversion in integrated circuit layouts and has become a de facto industry standard. Alternatively, it can also represent a binary file containing the geometry of planes within the integrated circuit layout, text, etc.

[0030] Tags, along with other relevant information, and potentially composed of hierarchical structures, are the design data upon which a mask fabrication plant (Foundry) relies to form the physical layout. Currently, GDS-II is the most commonly used graphical data description language file format in integrated circuit layout design. The completed layout... Figure 1 Generally, the circuit schematic is transmitted to the mask manufacturing plant via GDS-II format files (which graphically represent the circuit schematic) to achieve mask fabrication.

[0031] LVS: layout versus schematic, used to check whether the layout diagram (also known as the layout) and the circuit diagram (sometimes called the logic diagram) are consistent.

[0032] 0DRC: Design Rule Check, verifies the relationships between geometric figures in the layout drawing (such as line width, line spacing, etc.).

[0033] SOC: system-on-a-chip, generally known as a system-on-a-chip, also called a system-on-a-chip, means that it is a product, an integrated circuit with a specific purpose, which contains a complete system and all the embedded software.

[0034] 5. It is understandable that, due to their powerful functions, numerous integrated electronic components, and complex interconnections, System-on-a-Chip (SoC) designs, especially during the physical verification phase, using the manual marking method mentioned earlier to locate interconnects with circuit faults, such as short circuits, is a time-consuming task.

[0035] Figure 2 This is a schematic flowchart of an interconnect short-circuit location method in chip design according to an embodiment of this application. It can be applied to chip layout design physical verification scenarios. The chip is not limited to the aforementioned SOC system-on-a-chip, but can also be some small-scale chips, such as controller chips, memory chips, inverters, and semiconductor electronic component chips (e.g., MOSFETs, diodes, thyristors). Of course, considering that the wiring of small-scale chip circuits is generally not very complex, interconnection can usually be achieved through manual marking.

[0036] For short circuit location, the method described in this application can also be used, or a combination of methods from this application can be employed. (See also: 5) Figure 2 As shown, the interconnect short-circuit location method in the chip design includes the following steps:

[0037] S110. Perform an LVS check on the chip layout to determine whether there are any short-circuited interconnects in the chip layout;

[0038] In this embodiment, it can be achieved using some layout design verification tools, such as Cadence IC, Virtuoso LE, etc.

[0039] Before performing LVS inspection, the method further includes configuring an LVS inspection rule file, wherein the LVS inspection rule file contains definitions of the LVS operating environment, layer information of the layout, and inter-layer connection relationships. These inspection rules are generally provided by the foundry and are primarily intended to ensure circuit performance, facilitate implementation in the manufacturing process, and improve yield.

[0040] If so, proceed to step S120 to extract the layout data files for all interconnects with short circuits. This layout data file, commonly known as a GDS file, is a binary file containing the geometry of the planes in the integrated circuit layout.

[0041] In this embodiment, as an optional implementation, performing an LVS check on the chip layout to determine whether there are short-circuited interconnects in the chip layout includes: extracting the netlist file (net lists, here referring to the device netlist file in the layout) of the chip layout. This netlist file can characterize the circuit layout in the chip layout. The netlist file is contained in the GDS library and can exist in .GDS format or other graphic data formats, such as .oas file format; comparing the netlist file with the schematic netlist; if the comparison is consistent, there are no short circuits in the chip layout; if the comparison is inconsistent, there are short circuits in the chip layout.

[0042] In this embodiment, by comparing the device netlist file extracted from the layout with the schematic netlist, a specific technical solution is provided to determine whether there is a short circuit in the chip layout, which facilitates the rapid determination of whether there is a short circuit fault in the current design layout.

[0043] S130. According to the customized DRC rules, perform design rule checks on the layout data file to determine the location of the fault in the interconnect with the short circuit.

[0044] In this embodiment, DRC rules specifically designed for locating short-circuit faults in interconnects can be pre-defined, which facilitates the efficient and rapid determination of the location of short-circuit faults in interconnects.

[0045] Therefore, in some embodiments, before performing a design rule check on the graphics data system according to the customized DRC rules (step S130), the method further includes: customizing DRC rules for checking for overlapping interconnects on the same layer.

[0046] Generally, in SOC design, short circuits in interconnects fall into two categories: the first is as follows Figure 3 As shown, the two interconnects overlap but do not completely encompass each other; that is, they partially encompass each other. The second type is as follows... Figure 4 As shown, the two interconnects not only overlap, but one is completely contained within the other. Both of these situations can be identified using interconnect overlap checks. By customizing a DRC rule to check interconnect overlap, and running the DRC rule check, the physical location of the short circuit can be easily pinpointed.

[0047] For example, an instance of a custom DRC rule for checking metal 5 overlap is: the rule for checking metal 5 overlap is "m5 polygon overlap and m5>1". This DRC rule for checking interconnect overlap is relatively simple. Therefore, the entire DRC check does not take long to run. It can efficiently help users quickly find the location of short-circuited interconnects so as to modify the layout design and improve the efficiency of the layout design.

[0048] This embodiment describes an example of locating a short circuit in one of the interconnect lines. It should be understood that for the problem of short circuits in through-holes during SOC manufacturing, this invention can also first solve the short circuit problem of the interconnect lines. In this way, once the short circuit problem of the interconnect lines is solved, the short circuit problem of the through-holes will not occur, thereby helping users to quickly complete the layout design. The through-holes on the SOC substrate serve to connect the interlayer interconnects and link lines; they are essentially a form of interconnect line, and conductive layers, such as silver, copper, or other metallic conductive layers, can be plated on their inner walls.

[0049] Understandably, for chips with complex circuits, performing DRC rule checks directly based on the graphical data of the entire SOC chip layout would result in low execution efficiency.

[0050] Therefore, please refer to Figure 5 As shown, in some embodiments, the step of extracting the layout data file of all interconnects with short circuits (step S110) includes:

[0051] S115. Based on the LVS report obtained from the LVS check, obtain all interconnects with short circuits, and extract the layout data files of the short-circuited interconnects from the graphics database. A traversal algorithm can be used to search through the LVS report to obtain all short-circuited interconnects, improving the efficiency of target interconnect location. Correspondingly, step S130 specifically involves: performing a design rule check on the layout netlist file according to customized DRC rules to determine the location of the fault in the short-circuited interconnect. Thus, when performing the DRC rule check, only the layout netlist file with short-circuited interconnects is checked, reducing the processing workload and improving the efficiency of interconnect short-circuit location.

[0052] for Figure 3 Short circuits caused by partial overlap can also be addressed by customizing DRC rules for checking small corners. Based on whether the location violates the preset position in the DRC rules for small corners, the location of the short circuit in the interconnect can be determined.

[0053] To verify the accuracy of the judgment, in some embodiments, the DRC rules used to check for overlap can also be checked together with other DRC rules to improve the accuracy of the positioning, thereby helping users to repair the layout design and improve the layout design efficiency.

[0054] In addition, for Figure 3 The example shown illustrates a short circuit problem caused by overlap. Because of automated placement and routing, almost all lines are drawn using the minimum rules. Therefore, it is also possible to check whether there is a short circuit location by defining a threshold for sudden changes in line width on the same layer.

[0055] In some embodiments, for the various situations described above, the customized DRC rules for checking for overlapping interconnects on the same layer include: customized DRC rules for checking for partial inclusion, full inclusion, small corner positions, and / or single interconnect linewidth variations of adjacent interconnects on the same layer.

[0056] Please refer to Figure 6As shown, in order to help understand the technical solutions provided by the embodiments of the present invention, the following detailed description of the technical solutions and their technical effects is provided in conjunction with a specific example of implementing the embodiments of the present invention in a certain software:

[0057] Before running, configure the LVS rule file. After configuration,

[0058] 201: Run the SOC's LVS inspection module, read the LVS rule file and the current layout layers, and determine whether there are any short-circuited interconnects.

[0059] 202: Based on the LVS report in 201, obtain all interconnects with short circuits and extract the GDS of these short-circuited interconnects from the GDS of the SOC.

[0060] 203: Customize the DRC rules for checking overlapping interconnects on the same layer.

[0061] 204: Run a custom DRC rule check to locate the location of the short-circuited interconnect problem.

[0062] The main purpose of step 202 is to reduce the execution time of the DRC check in step 204. For chip designs that are not very complex, this step can also be omitted, as in this embodiment. Figure 1 The scheme is shown below. If step 202 is omitted and has little impact on the overall runtime, then in step 204, the GDS for which the custom DRC check is performed is the GDS of the entire SOC, which can also achieve the expected location of interconnect short-circuit problems. Conversely, if step 202 is omitted, then the custom DRC check is performed on the GDS of the short-circuited interconnect extracted in Figure 202.

[0063] As disclosed above, this invention addresses the challenge of locating interconnects in SOC design due to the large chip size. The present invention provides a method for locating short-circuit interconnects in chip design by applying LVS (Low-Level Screen) and DRC (Digital Currency Control) checks to detect and locate short circuits in chip layout interconnects. During layout design, an LVS check is performed on the chip layout to determine if any short-circuited interconnects exist. If so, layout data files for all short-circuited interconnects are extracted. Based on customized DRC rules, design rule checks are performed on the layout data files to determine the location of the fault in the short-circuited interconnect. Therefore, compared to solutions that add line markers to interconnects to locate short circuits, this method efficiently solves the problem of locating short circuits in SOC design.

[0064] Furthermore, the DRC check and location scheme for interconnect short circuits based on interconnect overlap provided in this embodiment of the invention can help designers quickly locate the location of interconnect short circuits so as to modify the design, which is beneficial to reducing the chip design cycle and has important significance for accelerating chip time-to-market at the technical level.

[0065] Figure 7 This is a schematic block diagram of the interconnect short-circuit location system architecture in a chip design according to an embodiment of this application. Please refer to [link / reference]. Figure 7 As shown, based on the same technical concept as the embodiments in the aforementioned Embodiment 1, this application also provides an interconnect short circuit location system in chip design, including: an LVS check program unit 210, used to perform an LVS check on the chip layout to determine whether there are short-circuited interconnects in the chip layout;

[0066] Extraction program unit 220 is used to extract the layout data files of all interconnects with short circuits if any exist;

[0067] The fault location program unit 230 is used to perform design rule checks on the layout data file according to the customized DRC rules to determine the location of the fault in the interconnect with short circuit.

[0068] The system in this embodiment can be used to execute Figure 1 The technical solution of the method embodiment shown is similar in principle and technical effect to that of Embodiment 1, and will not be described in detail here. They can be referred to each other.

[0069] In addition, it is understandable that Figure 7 The system shown is also applicable to the execution steps of other embodiments in Embodiment 1. For details, please refer to the relevant description in Embodiment 1, which will not be repeated here.

[0070] It should be noted that the program modules in the embodiments of the present invention can also be combined or named in other ways according to the tasks to be executed by the program, but the overall program steps and flow are basically the same. For details, please refer to Embodiment 1 or the above description, which will not be repeated here.

[0071] In some embodiments, the fault location program unit 230 includes: a search program module, used to perform design rule checks on the graphic data system according to customized DRC rules, and search for locations where adjacent interconnect lines overlap on the same layer;

[0072] The determination module is used to identify the location where adjacent interconnect lines overlap as the location where the interconnect line has a fault.

[0073] In some other embodiments, the LVS inspection unit 210 includes: an extraction module for extracting the netlist file of the chip layout;

[0074] The comparison unit is used to compare the netlist file with the schematic netlist;

[0075] If the comparison matches, there are no short circuits in the chip layout;

[0076] If the comparison is inconsistent, there is a short circuit in the chip layout.

[0077] The extraction program unit 120 is specifically used to obtain all interconnects with short circuits based on the LVS report obtained from the LVS inspection, and to extract the layout data file of the interconnects with short circuits from the graphics database.

[0078] In some other embodiments, the system further includes: a DRC rule customization program unit, used to customize DRC rules for checking for overlapping interconnects on the same layer; wherein the DRC rules for checking for overlapping interconnects on the same layer include: DRC rules for checking for partial inclusion, full inclusion, small corner positions and / or changes in line width of adjacent interconnects on the same layer.

[0079] The interconnect short-circuit location system provided in this invention addresses the low efficiency of existing SOC design methods that rely on marking for interconnect short-circuit location. Through the coordinated and interconnected operation of its various program modules, during the layout design process, an LVS check is performed on the chip layout to determine the presence of short-circuited interconnects. If short-circuited interconnects are found, layout data files for all short-circuited interconnects are extracted. Based on customized DRC rules, design rule checks are performed on the layout data files to determine the location of the fault in the short-circuited interconnect. Therefore, compared to solutions that add markers to interconnects to locate short circuits, this system efficiently solves the interconnect short-circuit location problem in SOC design.

[0080] Furthermore, this invention also provides a chip layout design method, the method comprising: after the initial chip layout design is completed, during the LVS and DRC verification process, at least one of the interconnect short-circuit location methods described in Embodiment 1 is executed.

[0081] Another embodiment of the present invention provides an electronic device, including: one or more processors; a memory; the memory storing one or more executable programs, wherein the one or more processors read the executable program code stored in the memory and run the executable program code to execute the interconnect short-circuit location method and the chip layout design method described in any of the foregoing embodiments.

[0082] Figure 8This is a schematic diagram of the structure of an embodiment of the electronic device of the present invention, which can implement the interconnect short-circuit location method in chip design described in any of the foregoing embodiments of the present invention, such as... Figure 8 As shown, as an optional embodiment, the above-mentioned electronic device may include: a housing 41, a processor 42, a memory 43, a circuit board 44, and a power supply circuit 45, wherein the circuit board 44 is disposed inside the space enclosed by the housing 41, and the processor 42 and the memory 43 are disposed on the circuit board 44; the power supply circuit 45 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 43 is used to store executable program code; the processor 42 runs the interconnect short circuit location system in the chip design corresponding to the executable program code by reading the executable program code stored in the memory 43, and is used to execute the interconnect short circuit location method in the chip design described in any of the foregoing embodiments.

[0083] For details on the specific execution process of the above steps by the processor 42 and the steps further executed by the processor 42 by running executable program code, please refer to the description of Embodiment 1 of the present invention, which will not be repeated here.

[0084] The electronic device exists in various forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by having mobile communication functions and are primarily designed to provide voice and data communication. These terminals include: smartphones, multimedia phones, feature phones, and low-end phones. (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, have computing and processing functions, and generally also have mobile internet access capabilities. These terminals include: PDAs, MIDs, and UMPCs, such as iPads. (3) Portable entertainment devices: These devices can display and play multimedia content. These devices include: audio and video playback modules (e.g., iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices. (4) Servers: Devices that provide computing services. Servers consist of processors, hard drives, memory, system buses, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability. (5) Other electronic devices with data interaction functions.

[0085] Another embodiment of the present invention provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the interconnect short-circuit location method in any of the chip designs described in Embodiment 1 above.

[0086] In summary, as described in the above embodiments, compared to the low efficiency of interconnect positioning based on marking methods in SOC design, the interconnect short-circuit positioning method and system disclosed in this invention can efficiently solve the problem of interconnect short-circuit positioning in chip design, help users quickly repair the layout, and thus improve the efficiency of layout design.

[0087] It should be noted that the embodiments described in this document have different focuses, but they are also related in some way. When understanding the present invention, the embodiments can be referred to one another. Furthermore, relational terms such as "first" and "second" are only used to refer to a single embodiment.

[0088] A term "comprising" or "including" distinguishes one entity or operation from another without necessarily requiring or implying any actual relationship or order between those entities or operations. Furthermore, the terms "comprising" and "including" are used to distinguish one entity or operation from another.

[0089] Or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the absence of

[0090] In more restrictive contexts, an element defined by the phrase "including one..." does not preclude the presence of other identical elements in the process, method, article, or apparatus that includes the stated element.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for locating short circuits in interconnects during chip design, characterized in that, The method includes: Perform an LVS check on the chip layout to determine whether there are any short-circuited interconnects in the chip layout; If so, extract the layout data files of all interconnects with short circuits; According to the customized DRC rules, a design rule check is performed on the layout data file to determine the location of the fault in the interconnect with the short circuit. The step of performing design rule checks on the layout data file according to customized DRC rules to determine the location of the fault in the short-circuited interconnect includes: According to the customized DRC rules, a design rule check is performed on the layout data file to find locations where adjacent interconnects overlap on the same layer; The location where adjacent interconnect lines overlap is determined as the location where the interconnect line fails.

2. The interconnect short-circuit location method in chip design according to claim 1, characterized in that, The step of performing an LVS check on the chip layout to determine whether there are short-circuited interconnects in the chip layout includes: Extract the netlist file of the chip layout; Compare the netlist file with the schematic netlist; If the comparison matches, there are no short circuits in the chip layout; If the comparison is inconsistent, there is a short circuit in the chip layout.

3. The interconnect short-circuit location method in chip design according to claim 2, characterized in that, The extraction of layout data files containing all short-circuited interconnects includes: Based on the LVS report obtained from the LVS inspection, obtain all interconnects with short circuits and extract the layout data files of the interconnects with short circuits from the graphics database.

4. The interconnect short-circuit location method in chip design according to claim 1, characterized in that, Before performing design rule checks on the layout data file according to the customized DRC rules, the method further includes: Customize DRC rules for checking for overlapping interconnects on the same layer.

5. The interconnect short-circuit location method in chip design according to claim 1, characterized in that, The customized DRC rules for checking for overlapping interconnects on the same layer include: Customize DRC rules to check for at least one of the following: partial containment, full containment, small corner position, and single interconnect line width variation among adjacent interconnects on the same layer.

6. A short-circuit location system for interconnects in chip design, characterized in that, include: The LVS check program unit is used to perform an LVS check on the chip layout to determine whether there are any short-circuited interconnects in the chip layout. Extract program unit, used to extract layout data files of all interconnects with short circuits, if applicable; The fault location program unit is used to perform design rule checks on the layout data file according to the customized DRC rules to determine the location of the fault in the interconnect with short circuit; The fault location program unit includes: a search program module, used to perform design rule checks on the layout data file according to customized DRC rules, and to find locations where adjacent interconnects overlap in the same layer; The determination module is used to identify the location where adjacent interconnect lines overlap as the location where the interconnect line has a fault.

7. The interconnect short-circuit positioning system in chip design according to claim 6, characterized in that, The LVS inspection program unit includes: an extraction program module, used to extract the netlist file of the chip layout; The comparison unit is used to compare the netlist file with the schematic netlist; If the comparison matches, there are no short circuits in the chip layout; If the comparison is inconsistent, there is a short circuit in the chip layout.

8. The interconnect short-circuit positioning system in chip design according to claim 7, characterized in that, The extraction program unit is specifically used to obtain all interconnects with short circuits based on the LVS report obtained from the LVS inspection, and to extract the layout data file of the interconnects with short circuits from the graphics database.

9. The interconnect short-circuit positioning system in chip design according to claim 8, characterized in that, The system further includes: a DRC rule customization program unit, used to customize DRC rules for checking for overlapping interconnects on the same layer; wherein, the DRC rules for checking for overlapping interconnects on the same layer include: DRC rules for checking for partial inclusion, full inclusion, small corner positions and / or changes in line width of adjacent interconnects on the same layer.

10. A chip layout design method, characterized in that, The method includes: after the initial chip layout design is completed, during the LVS and DRC verification process, performing the interconnect short-circuit location method as described in any one of claims 1 to 6.

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