A reinforced memory design method, system, device and storage medium
By adopting surface-mount memory chips and serial signal connections on the 6U board, the problems of loose memory modules and signal splitting were solved, realizing a high-frequency, high-bandwidth memory system that meets the needs of outdoor environments and high performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 西安超越申泰信息科技有限公司
- Filing Date
- 2022-12-16
- Publication Date
- 2026-05-12
AI Technical Summary
In the wild, ordinary memory modules are prone to loosening or contamination, leading to system failure. At the same time, traditional memory designs cannot meet the requirements of high clock speed and high bandwidth, resulting in limited memory system performance.
It uses surface-mount memory chips, utilizes the CPU's 8 channels, with one rank per channel and 8 memory chips per rank. The signal is directly connected to the CPU in serial mode to ensure no signal splitting. Combined with the 6U board design, signal integrity is optimized.
Maximize the use of memory capacity and bandwidth within the same space, increase memory frequency and total bandwidth to meet high performance requirements and ensure signal quality.
Smart Images
Figure CN115828838B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory system design technology, specifically to a ruggedized memory design method, system, device, and storage medium. Background Technology
[0002] In dealing with outdoor environments such as high mountains, mines, oil fields, and battlefields, as well as special fields such as petroleum and geological exploration, especially in long-distance, long-term vehicle-mounted anti-vibration scenarios, ordinary DIMM slot memory modules are prone to loosening or contamination, which can lead to system failure.
[0003] Furthermore, over the past decade, the unprecedented development of programs and applications, big data sets, 3D model rendering, cloud platforms, and other fields has led to increasingly higher demands on system memory. With the continuous increase in the number of CPU cores, memory technology also needs further expansion to cope with these massive demands. Higher clock speeds and higher bandwidth memory are the best solutions to achieve the current performance requirements. Therefore, the memory system must be designed to ensure that the memory operates at its maximum design speed to meet the processor's highest memory access requirements for data processing. Summary of the Invention
[0004] The technical objective of this invention is to address the above-mentioned shortcomings by providing a ruggedized memory design method, system, device, and storage medium that optimizes signal integrity, thereby increasing memory frequency and total memory bandwidth.
[0005] The technical solution adopted by this invention to solve its technical problem is:
[0006] A ruggedized memory design method includes a 6U board and an FT2000+ / 64 main chip and other components mounted on the 6U board. The memory is arranged using surface-mount memory chips, utilizing the CPU's 8 channels, with each channel having one rank; each rank has 8 memory chips, consisting of 4 memory chips on the front and 4 memory chips on the back.
[0007] For each Rank, the data signal is directly connected from each chip pin of the CPU to the eight memory chips. The signal is emitted by the CPU in a serial mode, passing through each memory chip to ensure that there is no signal splitting.
[0008] This method proposes a ruggedized high-frequency, high-bandwidth, and extremely space-saving memory system design based on surface-mount memory chips. Based on the Phytium platform FT2000+ / 64 main chip 6U (233.35*160mm) board design, combined with the current data center product application requirements and localization requirements, a ruggedized high-performance and extremely space-saving memory storage system is designed.
[0009] Furthermore, the 6U board size is fixed at 233.35*160mm, and the installation space for the memory area does not exceed 145*74mm. The CPU occupies 61*61mm of space, and the remaining space is used to place memory chips on both sides of the CPU.
[0010] Because the memory installation space is limited to 145*74mm, with the CPU occupying 61*61mm, the remaining space only allows for two rows of memory chips to be placed on one side of the CPU. Traditionally, two rows of memory chips are placed on each side of the CPU, utilizing only four memory channels. The FT2000+ / 64 supports eight memory channels, each requiring at least eight memory chips, each with 8 bits. However, the traditional design, calculating eight chips per rank, only accommodates 32 memory chips (64 bits total), resulting in a 256-bit bandwidth across four channels. This leads to wasted memory, low overall bandwidth, and failure to fully utilize CPU performance. While a dual-rank design (memory chips mounted face-up, one-to-two signal mode) can accommodate 64 chips and maximize memory capacity, dual-rank mode only selects one rank at a time based on the CS signal, still not guaranteeing simultaneous operation of all memory chips. The total bandwidth remains 256 bits, limiting overall memory bandwidth. Meanwhile, traditional designs require at least eight memory chips to be arranged on the same side and in the same rank. Furthermore, due to signal bifurcation, the chips at the closest end are more severely affected by signal reflection, which impacts signal quality, reduces DDR clock speed, and affects the total bandwidth of the memory system.
[0011] Furthermore, the eight Ranks are symmetrically and evenly distributed on the left and right sides of the CPU. The four Ranks on one side are arranged in two rows and two columns. Each Rank consists of four memory chips arranged vertically on the front and four memory chips arranged vertically on the back corresponding to the front.
[0012] Furthermore, the signal path of each Rank's eight memory chips sequentially passes from the first memory chip through adjacent memory chips to the last memory chip. That is, the signal path sequentially goes from the first memory chip in front to the fourth memory chip in front, then to the memory chip behind the fourth memory chip in front, and then sequentially to the memory chip behind the first memory chip in front, forming a complete serial signal path.
[0013] Furthermore, the other components include a BMC management module, an X100 bridge chip, a 10 Gigabit Ethernet chip, a power supply module, and an FPGA chip.
[0014] Preferably, the signals issued by the CPU include address signals, control signals, and command signals.
[0015] Preferably, each memory chip has 11 signal connection pins.
[0016] This invention also claims protection for a ruggedized memory system, including a 6U board and an FT2000+ / 64 main chip mounted on the 6U board, other components, and surface-mount memory chips;
[0017] The CPU uses 8 channels, each channel has one Rank; each Rank has 8 memory chips, 4 memory chips on the front and 4 memory chips on the back.
[0018] For each Rank, the data signal is directly connected from each chip pin of the CPU to the eight memory chips. The signal is emitted by the CPU in serial mode and passes through each memory chip.
[0019] The memory system is deployed using the aforementioned ruggedized memory design method.
[0020] This invention also claims protection for an electronic device comprising:
[0021] processor;
[0022] The DDR memory system is the ruggedized memory system described above, and the DDR memory system is electrically connected to the processor.
[0023] This invention also claims protection for a DDR storage medium, comprising:
[0024] PCB substrate;
[0025] The memory system power supply module is mounted on the PCB substrate;
[0026] Multiple DDR memory chips are regularly arranged on the front and back of the PCB substrate;
[0027] All DDR memory chips and the processor side employ the aforementioned ruggedized memory design method for circuit routing.
[0028] Compared with the prior art, the ruggedized memory design method, system, device, and storage medium of the present invention have the following advantages:
[0029] This method is based on the Phytium platform FT2000+ / 64 main chip 6U (233.35*160mm) board design. Combining the current data center product application requirements and localization requirements, it realizes ruggedized high-performance memory storage with extreme space. It can make full use of the main chip's 8 memory channels and optimize signal integrity, thereby improving memory frequency and increasing total memory bandwidth. Attached Figure Description
[0030] Figure 1 This is an architectural diagram of a ruggedized memory design method provided in an embodiment of the present invention;
[0031] Figure 2 This is an architectural diagram of a conventional memory design method provided in an embodiment of the present invention;
[0032] Figure 3 This is a schematic diagram of a traditional dual-rank memory design layout provided in an embodiment of the present invention;
[0033] Figure 4 This is a schematic diagram of a conventional memory dual-rank signal connection provided in an embodiment of the present invention;
[0034] Figure 5 This is a schematic diagram of the Rank signal connection in a ruggedized memory design method provided by an embodiment of the present invention;
[0035] Figure 6 This is a comparative example diagram of the eye diagram of the 3200Mbps address signal under single-rank and dual-rank modes provided in the embodiments of the present invention;
[0036] Figure 7 This is a comparative example diagram of the eye diagram of the 2666Mbps address signal under single-rank and dual-rank modes provided in the embodiments of the present invention. Detailed Implementation
[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0038] This invention provides a ruggedized memory design method, including a 6U board and other components such as an FT2000+ / 64 main chip and BMC management module, X100 bridge chip, 10 Gigabit chip, power module, and FPGA chip mounted on the 6U board. The memory is arranged using surface-mount memory chips, utilizing the CPU's eight channels, with each channel having one rank; each rank has eight memory chips, four on the front and four on the back.
[0039] For each Rank, data signals are directly connected from each chip pin of the CPU to the eight memory chips, each memory chip having 11 signal connection pins. Address, control, and command signals are issued by the CPU, pass through each memory chip, and are transmitted serially to ensure no signal branching.
[0040] This method proposes a ruggedized high-frequency, high-bandwidth, and extremely space-saving memory system design based on surface-mount memory chips. Based on the Phytium platform FT2000+ / 64 main chip 6U (233.35*160mm) board design, combined with the current data center product application requirements and localization requirements, a ruggedized high-performance and extremely space-saving memory storage system is designed.
[0041] The 6U board has a fixed size of 233.35*160mm, and the installation space for the memory area does not exceed 145*74mm. The CPU occupies 61*61mm of space, and the remaining space is used to place memory chips on both sides of the CPU.
[0042] Because the installation space for the memory area is limited to 145*74mm, with the CPU occupying 61*61mm, the remaining space only allows for two rows of memory chips to be placed on one side of the CPU. Following traditional design methods, two rows of memory chips are placed on each side of the CPU, thus utilizing only the CPU's four memory channels. Figure 2 As shown. The FT2000+ / 64 supports 8 memory channels, each requiring at least 8 memory chips, each chip being 8 bits. However, traditional designs calculate based on 8 chips per rank, resulting in a total bit width of 64 bits, which can only accommodate 32 memory chips. With four channels, the bit width is 256 bits, inevitably leading to waste, low memory capacity, and insufficient overall bandwidth, thus failing to fully utilize the CPU's performance. Figure 2 As shown, traditional design methods can only utilize the CPU's four memory channels, failing to maximize performance. If a dual-rank design is used, such as... Figure 3 As shown, the memory chips are mounted on both sides, and the signal mode is one-to-two. While this allows for 64 chips and maximizes memory capacity, dual-rank mode only selects one rank at a time based on the CS signal, meaning it cannot guarantee all chips are working simultaneously. The total bit width at any given time remains 256 bits, limiting the overall memory bandwidth. Furthermore, traditional designs require at least eight chips on the same side of the same rank. Because of signal splitting, the closest chips experience more signal reflection, impacting signal quality and causing a decrease in DDR frequency, thus affecting the overall memory system bandwidth. Figure 4 The diagram shows the existing dual-rank signal connection for memory.
[0043] This method breaks away from the traditional single-rank design, placing memory chips of the same rank on both sides of the motherboard. For each rank, four chips are placed on the front and four on the back. This allows for the utilization of all eight CPU channels within the same 64-chip space, achieving a 512-bit memory bus width and doubling the bandwidth. Furthermore, with only four chips of the same rank on the same side, signal splitting is eliminated, optimizing signal integrity. This ensures both capacity and DDR frequency and maximum bandwidth.
[0044] like Figure 1 As shown, in this method, the 8 Ranks are symmetrically and evenly distributed on the left and right sides of the CPU. The 4 Ranks on one side are arranged in two rows and two columns. Each Rank consists of 4 memory chips arranged vertically on the front and 4 memory chips arranged vertically on the back corresponding to the front.
[0045] The signal path for each of the eight memory chips in each Rank sequentially passes from the first memory chip through adjacent memory chips to the last memory chip. That is, the signal path goes sequentially from the first memory chip (front-facing) to the fourth memory chip (front-facing), then to the memory chip behind the fourth memory chip (front-facing), and then sequentially to the memory chip behind the first memory chip (front-facing), forming a complete serial signal path. Figure 5 As shown.
[0046] Memory is one of the most important components of a computer, serving as a bridge for communication with the CPU. All programs run within memory, therefore, memory performance has a significant impact on the computer's overall performance. The main chip's memory controller determines crucial parameters such as the maximum supported memory capacity, the number of memory banks, memory type, speed, and data width of the memory chips. Efficiently utilizing the effective data bandwidth of the memory system is key to determining the computer system's memory performance and is a significant factor affecting the overall performance of the computer system.
[0047] The formula for calculating memory bandwidth is: Bandwidth = Memory core frequency × Multiplier × (Memory bus width / 8), which can be further simplified to Bandwidth = Frequency * Bit width / 8.
[0048] However, in many designs, DDR4 memory often employs a downclocking design, typically operating at 2133 / 2400 / 2666MHz, not reaching the maximum speed of DDR4 3200MHz. Clearly, a lower memory clock speed leads to a corresponding decrease in bandwidth. Based on bandwidth calculation methods, a reduction in bit width also results in a corresponding decrease in bandwidth.
[0049] The increase in signal rate leads to a series of signal integrity issues, such as signal reflection, attenuation, distortion, crosstalk, ISI, signal delay, and timing errors. Addressing these signal integrity issues effectively through memory system design directly impacts memory performance and reliability. Current DDR4 technology, particularly in server platforms, often uses RDIMM memory modules or surface-mount chips. To meet capacity requirements, dual-rank memory is necessary, which not only struggles to meet transient bandwidth demands but also compromises signal integrity and hinders the achievement of maximum clock speeds. Therefore, an effective design solution to this problem is urgently needed.
[0050] The ruggedized memory design method provided in this embodiment of the invention uses eight CPU channels, each with one Rank, within the same layout space. This ensures that all Ranks can work simultaneously at the same time and that there is no signal splitting. Even in high-speed mode, it can still guarantee the highest speed of DDR signals, meet the high bandwidth requirements of the memory system, and maximize memory performance.
[0051] like Figure 6 The image shows a comparison of the eye diagrams of the address signals using this method with a single rank and the traditional dual rank at a rate of 3200Mbps. Figure 7 The image shows a comparison of the eye diagrams of the address signals for a single-rank and a traditional dual-rank method at a speed of 2666Mbps.
[0052] This invention also provides a ruggedized memory system, including a 6U board and an FT2000+ / 64 main chip, a BMC management module, an X100 bridge chip, a 10 Gigabit chip, a power module, an FPGA chip, and other components mounted on the 6U board, as well as surface-mount memory chips.
[0053] The CPU uses 8 channels, each channel has one Rank; each Rank has 8 memory chips, 4 memory chips on the front and 4 memory chips on the back.
[0054] For each Rank, data signals are directly connected from each chip pin of the CPU to the eight memory chips, each memory chip having 11 signal connection pins. Address, control, and command signals are issued by the CPU, pass through each memory chip, and are transmitted serially to ensure no signal branching.
[0055] The memory system is deployed using the aforementioned ruggedized memory design method.
[0056] The 6U board has a fixed size of 233.35*160mm, and the installation space for the memory area does not exceed 145*74mm. The CPU occupies 61*61mm of space, and the remaining space is used to place memory chips on both sides of the CPU.
[0057] Eight ranks are symmetrically and evenly distributed on the left and right sides of the CPU. The four ranks on one side are arranged in two rows and two columns. Each rank consists of four vertically arranged memory chips on the front and four corresponding vertically arranged memory chips on the back. Figure 1 As shown,
[0058] The signal path for each of the eight memory chips in each Rank sequentially passes from the first memory chip through adjacent memory chips to the last memory chip. That is, the signal path goes sequentially from the first memory chip (front-facing) to the fourth memory chip (front-facing), then to the memory chip behind the fourth memory chip (front-facing), and then sequentially to the memory chip behind the first memory chip (front-facing), forming a complete serial signal path. Figure 5 As shown.
[0059] This invention also provides an electronic device, comprising:
[0060] processor;
[0061] The DDR memory system is the ruggedized memory system described in the above embodiments, and the DDR memory system is electrically connected to the processor.
[0062] This invention also provides a DDR storage medium, comprising:
[0063] PCB substrate;
[0064] The memory system power supply module is mounted on the PCB substrate;
[0065] Multiple DDR memory chips are regularly arranged on the front and back of the PCB substrate;
[0066] All DDR memory chips and the processor side are wired using the ruggedized memory design method described in the above embodiments.
[0067] Through the specific embodiments described above, those skilled in the art can easily implement the present invention. However, it should be understood that the present invention is not limited to the specific embodiments described above. Based on the disclosed embodiments, those skilled in the art can arbitrarily combine different technical features to achieve different technical solutions.
[0068] Except for the technical features described in the specification, all other technologies are known to those skilled in the art.
Claims
1. A ruggedized memory design method, characterized in that, It includes a 6U board and the FT2000+ / 64 main chip and other components mounted on the 6U board. It uses surface-mount memory chips for memory arrangement, uses 8 channels of the CPU, and each channel has one rank; each rank has 8 memory chips, namely 4 memory chips on the front and 4 memory chips on the back. For each Rank, the data signal is directly connected from each chip pin of the CPU to the eight memory chips. The signal is emitted by the CPU in serial mode and passes through each memory chip. Eight Ranks are symmetrically and evenly distributed on the left and right sides of the CPU. The four Ranks on one side are arranged in two rows and two columns. Each Rank consists of four memory chips arranged vertically on the front and four memory chips arranged vertically on the back. Each Rank has 8 memory chips, and its signal path goes from the first memory chip through the adjacent memory chips in sequence until the last memory chip.
2. The ruggedized memory design method according to claim 1, characterized in that, The 6U board has a fixed size of 233.35*160mm, and the installation space for the memory area does not exceed 145*74mm. The CPU occupies 61*61mm of space, and the remaining space is used to place memory chips on both sides of the CPU.
3. A ruggedized memory design method according to claim 1 or 2, characterized in that, The other components include a BMC management module, an X100 bridge chip, a 10 Gigabit chip, a power module, and an FPGA chip.
4. The ruggedized memory design method according to claim 3, characterized in that, The signals sent by the CPU include address signals, control signals, and command signals.
5. The ruggedized memory design method according to claim 1, characterized in that, Each memory chip has 11 signal connection pins.
6. A ruggedized memory system, characterized in that, This includes a 6U board and the FT2000+ / 64 main chip mounted on the 6U board, other components, and surface-mount memory chips; The CPU uses 8 channels, each channel has one Rank; each Rank has 8 memory chips, 4 memory chips on the front and 4 memory chips on the back. For each Rank, the data signal is directly connected from each chip pin of the CPU to the eight memory chips. The signal is emitted by the CPU in serial mode and passes through each memory chip. Eight Ranks are symmetrically and evenly distributed on the left and right sides of the CPU. The four Ranks on one side are arranged in two rows and two columns. Each Rank consists of four memory chips arranged vertically on the front and four memory chips arranged vertically on the back. Each Rank has 8 memory chips, and its signal path goes from the first memory chip through the adjacent memory chips in sequence until the last memory chip. The memory system is arranged using the ruggedized memory design method described in any one of claims 1 to 5.
7. An electronic device, characterized in that, include: processor; The DDR memory system is a ruggedized memory system as described in claim 6, and the DDR memory system is electrically connected to the processor.
8. A DDR storage medium, characterized in that, include: PCB substrate; The memory system power supply module is mounted on the PCB substrate; Multiple DDR memory chips are regularly arranged on the front and back of the PCB substrate; All of the DDR memory chips and the processor side are wired using the ruggedized memory design method described in any one of claims 1 to 5.