Master-slave architecture multi-core parallel target recognition system and method based on embedded platform

Abstract

The application discloses a kind of master-slave architecture multicore parallel target identification system based on embedded platform, including embedded platform for target identification of built-in neural network, embedded platform includes multicore processor and shared memory, one of multicore processor is main processor, the rest is slave processor;Neural network includes several convolution layers;Each convolution layer includes several neural network units A for extracting image features;Neural network unit A is arranged in slave processor;Other neural network components except neural network unit A are arranged in main processor, and the task of neural network unit A of slave processor is distributed by main processor;Main processor is stored in shared memory after size transformation to image;Neural network unit A reads image from shared memory, and outputs image feature to shared memory;Main processor simultaneously reads multiple image features from shared memory and identifies target image.

Description

Technical Field

[0001] This invention relates to a target recognition system and method, and more particularly to a master-slave architecture multi-core parallel target recognition system and method based on an embedded platform. Background Technology

[0002] Since the beginning of the 21st century, computer and network technologies have advanced rapidly, and today's computer equipment boasts powerful computing capabilities that continue to rise steadily. Deep learning, fueled by massive amounts of big data, has driven the third wave of artificial intelligence and, with the help of powerful computing devices, is beginning to solve practical problems. Applying deep learning methods to the field of target recognition has become a research hotspot with broad application prospects. The principle of target recognition is to enable machines to "recognize" images through feature extraction and analysis, thereby labeling and classifying them. In the field of target recognition, with the needs of practical activities, the content to be recognized is becoming increasingly rich, and the categories to be recognized are becoming increasingly complex. Especially in maritime identification and detection systems, not only are there natural weather effects, but also human interference, such as changes in lighting, cloudy or rainy weather, and noise. Relying on past methods to manually extract image features for image detection is not only time-consuming and labor-intensive, but also suffers from various drawbacks such as difficulty in feature extraction. Therefore, applying deep learning to image detection is imperative.

[0003] Convolutional Neural Networks (CNNs) are representative networks for applying deep learning to object detection. While increasing the number and depth of network layers effectively improves the accuracy of large-scale image and video recognition, it also increases the number of weight parameters, placing higher demands on hardware computing performance, storage space, and memory bandwidth. Personal computers or servers can handle object recognition tasks under normal circumstances. However, when the working environment is harsh and subject to various adverse conditions, using existing computer equipment for object recognition will be limited in the following ways:

[0004] (1) Computer equipment consumes more energy (usually more than 200W) and requires a sufficient power supply. However, it is difficult to provide sufficient power for such high-power equipment in mobile vehicles such as drones and unmanned vehicles or in the field environment.

[0005] (2) The size and weight of computer equipment cannot be ignored. In actual working conditions, it is difficult to reserve a large space, especially for mobile drones, unmanned vehicles and other vehicles.

[0006] (3) Computer equipment is relatively expensive. It accounts for a large proportion of the cost of actual product development, and large-scale purchases will put a strain on research and development funds. Summary of the Invention

[0007] This invention provides a low-power, highly flexible, and low-cost master-slave architecture multi-core parallel target recognition system and method based on an embedded platform to solve the technical problems existing in the prior art.

[0008] The technical solution adopted by this invention to solve the technical problems existing in the prior art is as follows: a master-slave architecture multi-core parallel target recognition system based on an embedded platform, including an embedded platform, which includes a multi-core processor and shared memory, one of which is a master processor and the rest are slave processors; the embedded platform is equipped with a neural network for target recognition; the neural network includes several residual network components; each residual network component includes several neural network units A for extracting image features; neural network units A are located in the slave processors; other neural network components besides neural network units A are located in the master processor, and the master processor schedules and allocates tasks for the neural network units A of the slave processors; the master processor reads the image to be recognized and performs a size transformation on the image to be recognized to match the input parameters of the i-th neural network unit A, which then processes the size-transformed image A. i Stored in shared memory; the i-th neural network unit A reads image A from shared memory. i Output image features B i The image is loaded into shared memory; the main processor simultaneously reads multiple image features from shared memory, further processes the image features, and identifies the target image.

[0009] Furthermore, the main processor schedules and allocates the work of neural network unit A from the slave processor through inter-core communication (IPC).

[0010] Furthermore, each neural network unit A includes a convolutional layer, a batch normalization layer, and an activation function layer.

[0011] Furthermore, the shared memory is DDR memory.

[0012] Furthermore, the neural network also includes a neural network unit B for changing the image size, which is located within the main processor.

[0013] This invention also provides a master-slave architecture multi-core parallel target recognition method based on an embedded platform, utilizing the aforementioned master-slave architecture multi-core parallel target recognition system. A trained neural network for target recognition is deployed on the embedded platform, and the weight parameters of the neural network are stored in a shared memory space. The master processor schedules and allocates tasks to the neural network units A of the slave processors, allowing multiple slave processors' neural network units A to work in parallel. Finally, the master processor recognizes the target image and outputs it.

[0014] Furthermore, the neural network used is the YOLOv3 neural network.

[0015] Furthermore, the method includes the following steps:

[0016] Step 1: The embedded platform reads the YOLOv3 network structure and weight parameters into shared memory;

[0017] Step 2: The image is read into the embedded platform and stored in shared memory;

[0018] Step 3: The main processor executes the target recognition algorithm; when it reaches the convolution operation in the residual network component, it executes step 4;

[0019] Step 4: The main processor schedules and allocates convolution kernels to multiple slave processor neural network units A; and sequentially activates multiple slave processor neural network units A to perform convolution operations.

[0020] Step 5: Read the image to be calculated from the shared memory from the neural network unit A of the processor and perform convolution operation. After the convolution operation is completed, store the results into the shared memory in sequence and send an interrupt request to the main processor.

[0021] Step 6: After the main processor receives the convolution operation completion flags from multiple slave processors' neural network units A, it reads the image features stored in neural network units A from shared memory and continues to execute the target recognition algorithm; when the convolution operation is performed at the convolution layer, it returns to step 4 until the target recognition is completed.

[0022] Furthermore, in step 4, when the main processor schedules and allocates resources, it ensures that the convolution kernels in the convolution operation are evenly distributed to the neural network units A of multiple slave processors; if they cannot be evenly distributed, the number of convolution kernels allocated to each slave processor is inconsistent to ensure optimal parallel execution speed.

[0023] Furthermore, the final feature map result calculated by neural network unit A is stored in shared memory, and the data generated during the intermediate calculation process is not stored.

[0024] The advantages and positive effects of this invention are:

[0025] (1) Improved target recognition speed

[0026] The main computational load of target recognition algorithms based on convolutional neural networks is concentrated in convolution operations. This invention makes full use of the parallel capabilities of multi-core embedded platforms, fully leverages the computing power of embedded platforms, effectively improves the speed of convolution operations, and reasonably enhances the accuracy of target recognition.

[0027] (2) Low storage resource consumption:

[0028] This invention fully utilizes the architectural features of multi-core embedded platforms and makes reasonable use of shared memory. Through the shared memory mechanism, it realizes multi-core reuse of image data, avoids the large amount of buffered data generated during the intermediate calculation process of traditional target detection methods, and improves the utilization rate of storage resources.

[0029] (3) Easy to implement in engineering:

[0030] The embedded platform used in this algorithm is small in size and light in weight, and has the characteristics of flexible deployment. It effectively solves the problems of real-time speed in embedded target detection, is easy to implement in engineering, and has good results in both single-target and multi-target detection. Attached Figure Description

[0031] Figure 1 This is a flowchart of a master-slave architecture multi-core parallel target recognition method based on an embedded platform according to the present invention.

[0032] Figure 2 This is a schematic diagram of a master-slave architecture multi-core parallel target recognition system based on an embedded platform according to the present invention.

[0033] Figure 3 This is a schematic diagram of a task scheduling strategy for the master processor to schedule and allocate tasks to the slave processor according to the present invention.

[0034] Figure 4 This is a timing diagram of parallel operation from a processor according to the present invention.

[0035] Figure 5 This is a schematic diagram of a multi-core parallel processing method for master-slave architecture target recognition based on an embedded platform according to the present invention.

[0036] In the diagram: core0, main processor; core1 to N, first slave processor to Nth slave processor; CBL, minimum component of a multilayer neural network; conv, convolutional layer; Batch Normalization layer; Leakly ReLU, activation function layer; add layer adds tensors of the same dimension; concat, concatenation operation; Darknet-53, backbone network of YOLOv3 neural network; ResUnit, residual network component.

[0037] Res_N consists of one convolutional block and N residual network components. For example, Res_4 consists of one convolutional block and four residual network components.

[0038] `concat` is a feature map concatenation operation. It involves keeping the feature map size unchanged while increasing its dimensionality. For example, performing a `concat` operation on two 256×256×3 feature maps will result in a 256×256×6 feature map, with no increase in information within each dimension. Detailed Implementation

[0039] To further understand the invention's content, features, and effects, the following embodiments are provided, along with detailed descriptions in conjunction with the accompanying drawings:

[0040] Please see Figures 1 to 5 A master-slave architecture multi-core parallel target recognition system based on an embedded platform includes an embedded platform, which comprises a multi-core processor and shared memory. One of the multi-core processors is the master processor, and the rest are slave processors. The embedded platform contains a neural network for target recognition. The neural network includes several residual network components. Each residual network component includes several neural network units A for extracting image features. Neural network units A are located within the slave processors. The other neural network components besides neural network units A are located within the master processor, which schedules and allocates tasks to the neural network units A of the slave processors. The master processor reads the image to be recognized and performs a size transformation on the image to match the input parameters of the i-th neural network unit A. The master processor then processes the size-transformed image A. i Stored in shared memory; the i-th neural network unit A reads image A from shared memory. i Output image features B i The image features are simultaneously read from shared memory; the main processor reads multiple image features from shared memory, further processes the image features, and identifies the target image. Neural network unit A includes convolutional kernels.

[0041] The embedded platform can utilize the TMS320C6678 device from Texas Instruments (TI). The TMS320C6678 features eight C66x cores with a maximum clock speed of 1.4 GHz, and its common operating frequency is 1 GHz or 1.25 GHz. In terms of internal storage resources, this embedded device offers abundant on-chip memory.

[0042] Preferably, the main processor can schedule and allocate the work of the neural network unit A of the slave processor through inter-core communication (IPC).

[0043] Preferably, each neural network unit A may include a convolutional layer, a batch normalization layer, and an activation function layer.

[0044] Preferably, the shared memory can be a DDR memory.

[0045] Preferably, the neural network may further include a neural network unit B for changing the image size, and the neural network unit B is disposed within the main processor.

[0046] This invention also provides a master-slave architecture multi-core parallel target recognition method based on an embedded platform, utilizing the aforementioned master-slave architecture multi-core parallel target recognition system. A trained neural network for target recognition is deployed on the embedded platform, and the weight parameters of the neural network are stored in a shared memory space. The master processor schedules and allocates tasks to the neural network units A of the slave processors, allowing multiple slave processors' neural network units A to work in parallel. Finally, the master processor recognizes the target image and outputs it.

[0047] Preferably, the neural network can be a YOLOv3 neural network; the residual component in the YOLOv3 neural network has several neural network units A.

[0048] YOLOv3 is a type of YOLO neural network, proposed by Joseph Redmon et al. in 2016. It treats object detection as a regression problem, using a convolutional neural network in an end-to-end manner to simultaneously predict the location and category of objects in an image. YOLO v3 is an improvement on YOLO v1 and YOLO v2. Addressing the low recall rate of predicted bounding boxes in YOLO v1, it significantly increases the number of predicted regions by using an anchor-box-based target region acquisition method, thereby improving the recall rate and effectively reducing the number of missed detections when targets overlap. YOLO v3 improves the backbone extraction network based on YOLO v2, enhancing its feature extraction capabilities from the input image. Furthermore, addressing the poor prediction performance of shallow prediction branches in YOLO v2, it uses a Feature Pyramid Network (FPN) structure, employing a top-down feature fusion flow to improve the detection capabilities of shallow networks. YOLO v3, as a representative network among one-stage object detection networks, is widely used in detection tasks in various fields due to its good generalization ability, fast detection speed, and high portability.

[0049] Preferably, the method may include the following steps:

[0050] Step 1: The embedded platform reads the YOLOv3 network structure and weight parameters into shared memory;

[0051] Step 2: The image is read into the embedded platform and stored in shared memory;

[0052] Step 3: The main processor executes the target recognition algorithm; when it reaches the convolution operation in the residual network component, it executes step 4;

[0053] Step 4: The main processor schedules and allocates convolution kernels to multiple slave processor neural network units A; and sequentially activates multiple slave processor neural network units A to perform convolution operations.

[0054] Step 5: Read the image to be calculated from the shared memory from the neural network unit A of the processor and perform convolution operation. After the convolution operation is completed, store the results into the shared memory in sequence and send an interrupt request to the main processor.

[0055] Step 6: After the main processor receives the convolution operation completion flags from multiple slave processors' neural network units A, it reads the image features stored in neural network units A from shared memory and continues to execute the target recognition algorithm; when the convolution operation is performed at the convolution layer, it returns to step 4 until the target recognition is completed.

[0056] Preferably, in step 4, when the main processor schedules and allocates, the convolution kernels in the convolution operation can be evenly distributed to the neural network units A of multiple slave processors; if they cannot be evenly distributed, the number of convolution kernels allocated to each slave processor can be inconsistent to ensure the optimal speed of parallel execution.

[0057] Preferably, the final feature map result calculated by neural network unit A can be stored in shared memory, without storing the data generated during the intermediate calculation process.

[0058] The structure and working principle of the present invention are further illustrated below with reference to a preferred embodiment:

[0059] like Figure 1 As shown, a master-slave architecture multi-core parallel target recognition system based on an embedded platform includes an embedded platform. The embedded platform includes a multi-core processor and shared memory, where one of the multi-core processors is the master processor and the rest are slave processors. The embedded platform contains a neural network for target recognition. The neural network includes several residual networks, each of which includes several independent neural network units A for extracting image features. Neural network units A are located within the slave processors. Other neural network components besides neural network units A are located within the master processor, which schedules and allocates the work of neural network units A. The master processor reads the image to be recognized and performs a size transformation on the image to match the input parameters of the i-th neural network unit A. The master processor then processes the size-transformed image A... i Stored in shared memory; the i-th neural network unit A reads image A from shared memory. i Output image features B i The image is loaded into shared memory; the main processor simultaneously reads multiple image features from shared memory, further processes the image features, and identifies the target image.

[0060] The embedded platform utilizes the TMS320C6678 device from Texas Instruments (TI). A lightweight target recognition algorithm is deployed on the embedded platform, and multi-core parallel computing is used to accelerate the target recognition process, improving the detection speed. The embedded platform stores the fully trained and optimized neural network model of the target detection algorithm, along with the neural network weight parameters, in shared memory. Multi-core parallel convolution computation is used to optimize the convolution calculation process of the neural network, accelerating model inference speed. Finally, the embedded platform outputs the recognized target image.

[0061] The neural network used for target recognition employs a multi-layer YOLOv3 neural network. Shared memory is provided by DDR storage.

[0062] First, the main processor reads the input image to be detected and resizes the object to match the input parameters of the neural network. The resized image is then stored in shared memory. Next, the main processor schedules the slave processors to perform neural network computations via IPC (Inter-Core Communication). During convolutional layer computations, the main processor allocates an appropriate number of convolutional kernels to each slave processor. The slave processors store the final feature map results in shared memory; intermediate computation values ​​are not stored to ensure computational efficiency and improve scheduling speed. After computation, the main processor performs model inference and outputs the recognition result.

[0063] Figure 2 The YOLOv3 multilayer neural network architecture of this invention is shown, whose basic components are CBL and ResUnit. CBL is the smallest component, consisting of three parts: a convolutional (conv) layer, a batch normalization (BN) layer, and a Leakly ReLU activation function layer. Neural network unit B of this invention adopts the CBL structure. Neural network unit A includes a convolutional kernel. The convolutional kernel performs convolution operations.

[0064] Convolution operation refers to the operation performed on a two-dimensional matrix of image data using the following formula:

[0065]

[0066] Where: the pixel value at point (i,j) in the input image is denoted as I(i,j), the weight of the m×n convolution kernel is denoted as k(s,t), and the convolution result is denoted as y(a,b).

[0067] m is the number of elements in each column of the convolution kernel, n is the number of elements in each row of the convolution kernel, s is the column shift of the image coordinates, t is the row shift of the image coordinates, and I(is,jt) is the pixel value of the input image at the point (is,jt).

[0068] For a two-dimensional image, if each row has N pixels and each column has M pixels, then the image f(x,y) can be represented by an M×N two-dimensional matrix, where each element of the matrix corresponds one-to-one with each pixel of the image. Therefore:

[0069]

[0070] For example, f(0,0) represents the image pixel value at the pixel position (0,0).

[0071] The activation function used is the Leakly ReLU function. The Leakly ReLU function is a slight modification of the ReLU function, defined as shown in the following equation. Compared to the ReLU function, the Leakly ReLU function assigns a small constant 'a' to all negative values ​​with a non-zero slope, thus preserving some information about the negative axis. The mathematical expression of the Leakly ReLU function is as follows:

[0072]

[0073] f(x) is the activation function.

[0074] f'(x) is the derivative of the activation function.

[0075] a is a very small, arbitrarily given constant.

[0076] x is the input to the neuron node.

[0077] ResUnit consists of two residual network components and an add layer, enabling residual skipping. Res_N consists of one CBL and N ResUnits, containing 1+2×N convolutional layers. The first CBL block of Res_N reduces the feature map size by half by using a convolution stride of 2.

[0078] Taking a 256×256 image as an example, after passing through the neural network, three feature maps of sizes 8×8, 16×16, and 32×32 are obtained. Each feature map generates three prior boxes of different sizes. Decoding the prior boxes yields the detection boxes. During inference, YOLOv3 divides the input image into S×S grid units based on the final feature map size for detection. First, all results below a threshold are filtered out. Then, the highest value is selected as the final output, and its center point coordinates, width, height, and confidence score are calculated.

[0079] Figure 3This paper presents a task scheduling strategy for the main processor (core0) to allocate tasks to slave processors based on factors such as dependencies and runtime overhead. The aim is to ensure that the computation time for each slave processor is approximately equal, avoiding long waiting periods that could slow down detection. After generating the task scheduling strategy, the main processor will allocate tasks based on the number of slave processors. Figure 2 For example, N slave processors are divided into N tasks, which are then executed by each slave processor.

[0080] Figure 4 This diagram illustrates the timing of a deep pipelined computation with fine-grained parallelism. Based on the kernel's task allocation, each convolution process is divided into four steps. After each slave processor completes its task, it transmits the result to the next slave processor. To implement this deep pipelined structure, it's necessary to ensure that the completion time of each slave processor is either comparable or progressively decreases. For example, after a slave processor finishes reading in image data, it transmits the read image data to the convolution kernel and begins reading in the next image. At this point, the convolution kernel should have completed the convolution operation for the previous image and is waiting for the data transmitted from the slave processor; other slave processors follow the same procedure. This ensures the completion of the deep pipelined structure.

[0081] Figure 5 This diagram illustrates the parallel processing using coarse-grained convolutional windows, which reduces the computation time required for the convolution process. This parallelism occurs within each convolutional unit; when each unit performs its operations, the weights are not only applied to a portion of the input feature image but are also used for the joint computation of multiple neural network units A.

[0082] The following is a preferred embodiment of the master-slave architecture multi-core parallel target recognition method based on an embedded platform, which employs the above-mentioned master-slave architecture multi-core parallel target recognition system based on an embedded platform. The method includes the following steps:

[0083] Step 1: The embedded platform reads the YOLOv3 network structure and weight parameters into the DDR memory to complete the deployment of the target recognition model.

[0084] Step 2: Read the RGB image into the shared memory in the embedded platform.

[0085] Step 3: The main processor of the embedded platform executes the target recognition algorithm. When it reaches the convolutional layer to perform the convolution operation, it activates N slave processors to perform parallel computation to accelerate the convolution process.

[0086] Step IV: The main processor of the embedded platform distributes the convolution kernels of each convolution operation evenly to the neural network units A of the N slave processors. If they cannot be evenly distributed, the number of convolution kernels allocated to each slave processor's neural network unit A can be inconsistent to ensure the optimal speed for parallel execution.

[0087] Step V: The main processor of the embedded platform activates N neural network units A of the slave processors in sequence to perform convolution operations through inter-core IPC communication.

[0088] Step VI: The neural network unit A of the slave processor of the embedded platform reads the feature map of the RGB image to be calculated from the shared content and performs convolution operation. After the convolution operation of the neural network unit A of the slave processor is completed, the result is stored in the shared memory in sequence. The slave processor sends an interrupt to the master processor through the inter-core communication method of IPC.

[0089] Step VII: After the main processor of the embedded platform receives the convolution completion flags from N slave processors, the main processor continues to execute the target recognition algorithm. When it reaches the convolutional layer to perform the convolution operation, it activates N slave processors and repeats steps IV to VI until the target recognition process is completed.

[0090] Step VIII: The embedded platform transmits and saves the target recognition results via Ethernet and releases the storage space occupied by this target recognition.

[0091] The aforementioned embedded platform, main processor, master-slave processor, neural network for target recognition, residual network component, DDR memory, YOLOv3 network structure, etc., all adopt applicable devices or functional components in the prior art, or are constructed using applicable devices or functional components in the prior art and conventional technical means.

[0092] From an economic and practical standpoint, comprehensive performance is unnecessary; just meeting the needs of actual use is sufficient. Therefore, low-power, highly flexible, and low-cost embedded multi-core digital signal processors can replace complex computer equipment.

[0093] The embodiments described above are only used to illustrate the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The patent scope of the present invention should not be limited by these embodiments. That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention still fall within the patent scope of the present invention.

Claims

1. A master-slave architecture multi-core parallel target recognition system based on an embedded platform, characterized in that, The embedded platform includes a multi-core processor and shared memory, where one core is the master processor and the rest are slave processors. The embedded platform contains a neural network for target recognition. This neural network includes several residual network components. Each residual network component includes several neural network units A for extracting image features. Neural network units A are located within the slave processors. All other neural network components except for neural network units A are located within the master processor, which schedules and allocates tasks to the neural network units A on the slave processors. The master processor reads the image to be recognized and performs a size transformation on it to match the input parameters of the i-th neural network unit A. The transformed image A... i Stored in shared memory; the i-th neural network unit A reads image A from shared memory. i Output image features B i The image is loaded into shared memory; the main processor simultaneously reads multiple image features from shared memory, further processes the image features, and identifies the target image. Each neural network unit A includes a convolutional layer, a batch normalization layer, and an activation function layer.

2. The master-slave architecture multi-core parallel target recognition system based on an embedded platform according to claim 1, characterized in that, The main processor schedules and allocates the work of neural network unit A from the slave processor through inter-core communication (IPC).

3. The master-slave architecture multi-core parallel target recognition system based on an embedded platform according to claim 1, characterized in that, The shared memory is DDR storage.

4. The master-slave architecture multi-core parallel target recognition system based on an embedded platform according to claim 1, characterized in that, The neural network also includes a neural network unit B for changing the image size, which is located within the main processor.

5. A method for master-slave architecture multi-core parallel target recognition based on an embedded platform, utilizing the master-slave architecture multi-core parallel target recognition system based on any one of claims 1 to 4, characterized in that, Deploy the trained neural network for target recognition on the embedded platform and store the weight parameters of the neural network in a shared memory space; The main processor schedules and allocates tasks to the neural network unit A of the slave processors, and the neural network units A of multiple slave processors work in parallel. Finally, the main processor recognizes the target image and outputs it.

6. The master-slave architecture multi-core parallel target recognition method based on an embedded platform according to claim 5, characterized in that, The neural network used is the YOLOv3 neural network.

7. The master-slave architecture multi-core parallel target recognition method based on an embedded platform according to claim 6, characterized in that, The method includes the following steps: Step 1: The embedded platform reads the YOLOv3 network structure and weight parameters into shared memory; Step 2: The image is read into the embedded platform and stored in shared memory; Step 3: The main processor executes the target recognition algorithm; when it reaches the convolution operation in the residual network component, it executes step 4; Step 4: The main processor schedules and allocates convolution kernels to multiple slave processor neural network units A; and sequentially activates multiple slave processor neural network units A to perform convolution operations. Step 5: Read the image to be calculated from the shared memory from the neural network unit A of the processor and perform convolution operation. After the convolution operation is completed, store the results into the shared memory in sequence and send an interrupt request to the main processor. Step 6: After the main processor receives the convolution operation completion flags from multiple slave processors' neural network units A, it reads the image features stored in neural network units A from shared memory and continues to execute the target recognition algorithm; when the convolution operation is performed at the convolution layer, it returns to step 4 until the target recognition is completed.

8. The master-slave architecture multi-core parallel target recognition method based on an embedded platform according to claim 7, characterized in that, In step 4, when the main processor schedules and allocates resources, it ensures that the convolution kernels in the convolution operation are evenly distributed to the neural network units A of multiple slave processors; if they cannot be evenly distributed, the number of convolution kernels allocated to each slave processor is inconsistent to ensure the optimal speed of parallel execution.

9. The master-slave architecture multi-core parallel target recognition method based on an embedded platform according to claim 6, characterized in that, The final feature map result calculated by neural network unit A is stored in shared memory, and the data generated during the intermediate calculation process is not stored.

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