Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the invention relate to semiconductor devices and methods of manufacturing the same. A semiconductor device includes a gate structure, n-type source / drain components, p-type source / drain components, an NFET channel, and a PFET channel. The gate structure is over a substrate. The n-type source / drain components are at opposite first and second sides of the gate structure, respectively. The p-type source / drain components are at opposite third and fourth sides of the gate structure, respectively. The NFET channel extends within the gate structure and connects the n-type source / drain components. The PFET channel extends within the gate structure and connects the p-type source / drain components. The NFET channel and the PFET channel are vertically spaced apart by the gate structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] Transistors are widely used components in semiconductor devices. For example, in some applications, a single integrated circuit (IC) may contain thousands of transistors. One common type of transistor used in semiconductor device manufacturing is the metal-oxide-semiconductor field-effect transistor (MOSFET). Two transistors can be coupled together to form an inverter. Summary of the Invention

[0004] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a first semiconductor layer on a substrate and forming a second semiconductor layer over the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having a first sidewall extending along a first direction and a second sidewall extending along a second direction different from the first direction; forming a first internal spacer on the first sidewall of the first semiconductor layer; forming a p-type source / drain structure on the first sidewall of the second semiconductor layer; forming a second internal spacer on the second sidewall of the second semiconductor layer; forming an n-type source / drain structure on the second sidewall of the first semiconductor layer; and forming a gate structure at least partially located between the first semiconductor layer and the second semiconductor layer.

[0005] According to another aspect of the present invention, a method of manufacturing a semiconductor device is provided, comprising: forming a layer stack on a substrate, the layer stack including an n-type field-effect transistor (NFET) channel layer, a p-type field-effect transistor (PFET) channel layer and a sacrificial layer located between the NFET channel layer and the PFET channel layer; performing a first selective etching process on opposing first sidewalls of the layer stack, wherein the first selective etching process etches the NFET channel layer at an etch rate faster than etching the PFET channel layer; after performing the first selective etching process, forming a p-type epitaxial structure on the first sidewall of the layer stack; performing a second selective etching process on opposing second sidewalls of the layer stack, wherein the second selective etching process etches the PFET channel layer at an etch rate faster than etching the NFET channel layer; after performing the second selective etching process, forming an n-type epitaxial structure on the second sidewall of the layer stack; and replacing the sacrificial layer with a gate structure.

[0006] According to another aspect of the present invention, a semiconductor device is provided, comprising: a gate structure located above a substrate; an n-type source / drain component and a p-type source / drain component disposed around the gate structure, wherein, in a top view, the gate structure has a quadrilateral profile, the n-type source / drain components are respectively located at opposite first and second sides of the quadrilateral profile of the gate structure, and the p-type source / drain components are respectively located at opposite third and fourth sides of the quadrilateral profile of the gate structure; an NFET channel extending within the gate structure and connecting the n-type source / drain component; and a PFET channel extending within the gate structure and connecting the p-type source / drain component, wherein, in a cross-sectional view, the NFET channel and the PFET channel are vertically spaced apart by the gate structure. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic circuit diagram of an example CMOS inverter according to some embodiments of the present disclosure.

[0009] Figures 2A to 19C These are top views, perspective views, and cross-sectional views of inverters at an intermediate stage of manufacturing, according to some embodiments of the present disclosure.

[0010] Figure 20A and Figure 20B This is a cross-sectional view of an inverter according to some embodiments of the present disclosure, wherein Figure 20A From the corresponding Figure 19A The section A-A' in the middle is obtained, and Figure 20B From the corresponding Figure 19A The section B-B' in the middle is obtained.

[0011] Figure 21A and Figure 21B This is a cross-sectional view of an inverter according to some embodiments of the present disclosure, wherein Figure 21A From the corresponding Figure 19A The section A-A' in the middle is obtained, and Figure 21B From the corresponding Figure 19A The section B-B' in the middle is obtained.

[0012] Figure 22A and Figure 22B This is a cross-sectional view of an inverter according to some embodiments of the present disclosure, wherein Figure 22A From the corresponding Figure 19A The section A-A' in the middle is obtained, and Figure 22B From the corresponding Figure 19A The section B-B' in the middle is obtained. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spacing relation terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to encompass different orientations of the device in use or operation. Devices may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein can be interpreted accordingly. As used herein, “approximately,” “about,” “roughly,” or “essentially” can generally mean within 20%, 10%, or 5% of a given value or range. Unless explicitly stated otherwise, the numerical values ​​given herein are approximate, meaning that the terms “approximately,” “about,” “roughly,” or “essentially” can be inferred. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink.

[0015] Figure 1 This is a schematic circuit diagram of an example complementary metal-oxide-semiconductor (CMOS) inverter 100 according to some embodiments of the present disclosure. The example inverter 100 includes a p-type field-effect transistor (PFET) 102 and an n-type field-effect transistor (NFET) 108 coupled together. When the input voltage Vin of the inverter 100 is low, the p-type transistor 102 is turned on, charging the load capacitor 104, and the output goes to the gate driver 106. DD Or, when V inWhen the voltage is high, the n-type transistor 108 is turned on, discharging the load capacitor, and the output node goes to ground 110 (e.g., Vss). In this way, the inverter 100 can perform logic swings for digital processing. Because the CMOS inverter 100 includes two transistors formed at the same horizontal height on the wafer, reducing the footprint of the inverter 100 is challenging. Therefore, embodiments of this disclosure are directed to a novel structure of an inverter having PFET channels and NFET channels arranged alternately along the vertical direction, thereby reducing the inverter's footprint.

[0016] Figures 2A to 19C These are top views, perspective views, and cross-sectional views of intermediate stages in inverter manufacturing according to some embodiments of this disclosure. Manufacturing process steps can be used to manufacture inverters as described above. Figure 1 The inverter 100 is discussed. It should be understood that it can be... Figures 2A to 19C Additional operations are provided before, during, and after the process shown, and some of the operations described below may be substituted or eliminated in other embodiments of the method. The order of operations / processes may be interchanged.

[0017] Figure 2A This is a top view taken at an intermediate stage in inverter manufacturing, and Figure 2B From Figure 2A The cross-sectional view obtained from section A-A' in the diagram. Figure 2A and Figure 2B The image shows a substrate 200. In some embodiments, substrate 200 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate. Substrate 200 may include: semiconductor materials, such as elemental semiconductors including Si and Ge; compound or alloy semiconductors, including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; and combinations thereof. Substrate 200 may be doped or substantially undoped. In a specific example, substrate 200 is a bulk silicon substrate, which may be a wafer.

[0018] Figure 2A and Figure 2BA layer stack LS formed over a substrate 200 is also shown. The layer stack LS may include one or more buffer layers 201 formed on the substrate 200. The buffer layer 201 may be used to gradually change the lattice constant from the lattice constant of the substrate 200 to the lattice constant of the epitaxial layer in the layer stack LS. The buffer layer 201 may be formed of an epitaxially grown single-crystal semiconductor material, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some embodiments, the substrate 200 is made of Si and the buffer layer 201 is made of germanium. The buffer layer 201 is epitaxially grown on the substrate 200 by one or more epitaxial or epitaxial (epi) processes. Epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes.

[0019] A first semiconductor layer (also referred to herein as a sacrificial layer) 202A is formed above the buffer layer 201. A second semiconductor layer (also referred to herein as an NFET channel layer) 204A is formed above the sacrificial layer 202A. Another first semiconductor layer (sacrificial layer) 202B is formed above the NFET channel layer 204A. A third semiconductor layer (also referred to herein as a PFET channel layer) 206A is formed above the sacrificial layer 202B. Another first semiconductor layer (sacrificial layer) 202C is formed above the PFET channel layer 206A. Another second semiconductor layer (NFET channel layer) 204B is formed above the sacrificial layer 202C. Another first semiconductor layer (sacrificial layer) 202D is formed above the NFET channel layer 204B. Another third semiconductor layer (PFET channel layer) 206B is formed above the sacrificial layer 202D.

[0020] In some embodiments, the first, second, and third semiconductor layers are stacked alternately, such that there are more than two of each of the first, second, and third semiconductor layers. The first semiconductor layers 202A-202D (collectively referred to as first semiconductor layer 202) will be removed in subsequent processes and are therefore referred to as sacrificial layers. The second semiconductor layers 204A and 204B (collectively referred to as second semiconductor layer 204) will become nanosheets, nanowires, nanoplates, or nanorings of the n-type source / drain regions formed in subsequent processes and will be retained in the final IC product as NEFT channel layers. The third semiconductor layers 206A and 206B (collectively referred to as third semiconductor layer 206) will become nanosheets, nanowires, nanosheets, or nanorings of the p-type source / drain regions formed in subsequent processes and will be retained in the final IC product as PEFT channel layers.

[0021] In some embodiments, the number of NFET channel layers 204 is 1 to 20, and the number of PFET channel layers 206 is 1 to 20. In some embodiments, the number of NFET channel layers 204 is the same as the number of PFET channel layers 206. In some embodiments, the number of NFET channel layers 204 is greater than the number of PFET channel layers 206. In some embodiments, the number of NFET channel layers 204 is less than the number of PFET channel layers 206. The number of NFET channel layers 204 and the number of PFET channel layers 206 can be selected to balance the current of the resulting inverter.

[0022] In some embodiments, the sacrificial layer 202, the NFET channel layer 204, and the PFET channel layer 206 are made of different materials selected from the group consisting of Si, Ge, Sn, SiGe, GeSn, Ge:B, SiGeSn, III-V compounds, and combinations thereof. Due to the different materials, in subsequent processes, the NFET channel layer 204 can be selectively etched while the sacrificial layer 202 and the PFET channel 206 are substantially not etched, and the PFET channel layer 206 can be selectively etched without etching the sacrificial layer 202 and the PFET channel 206. Alternatively, the NFET channel layer 204 and the sacrificial layer 202 can be selectively etched while the NFET channel layer 204 and the PFET channel layer 206 are substantially not etched. In some embodiments, the sacrificial layer 202 is a pure germanium (Ge) layer without Si or Sn.

[0023] In some embodiments, the lattice constant of the PFET channel layer 206 is greater than that of the NFET channel layer 204, therefore the PFET channel layer 206 has compressive strain and the NFET channel layer 204 has tensile strain. Compressive strain increases the hole mobility in the PFET channel layer 206, while tensile strain increases the electron mobility in the NFET channel layer 204. In some embodiments, the NFET channel layer 204 is a germanium-silicon (GeSi) layer, and the PFET channel layer 206 is a germanium-tin (GeSn) layer. In some embodiments, the NFET channel layer 204 is a boron-doped germanium (Ge:B) layer, and the PFET channel layer 206 is an undoped GeSi layer. In some embodiments, the NFET channel layer 204 is a Ge-free Si layer, and the PFET channel layer 206 is a GeSi layer. In some embodiments, the NFET channel layer 204 is a Sn-free Ge layer, and the PFET channel layer 206 is an undoped GeSn layer.

[0024] In some embodiments, the thickness of each NFET channel layer 204 is less than the critical thickness of the epitaxial material of the NFET channel layer 204, and the thickness of each PFET channel layer 206 is less than the critical thickness of the epitaxial material of the PFET channel layer 206. As used herein, "critical thickness" refers to the thickness at which the epitaxial layer can maintain an elastic strain energy below the dislocation formation energy. When the film thickness is below the critical thickness, the elastic strain layer is thermodynamically stable and no dislocations form. Because the thickness of each NFET channel layer 204 is less than its critical thickness, and the thickness of each PFET channel layer 206 is less than its critical thickness, the NFET channel layer 204 maintains tensile strain without strain relaxation or with negligible strain relaxation, and the PFET channel layer 206 maintains compressive strain without strain relaxation or with negligible strain relaxation. In some embodiments, the NFET channel layer 204 and the PFET channel layer 206 each have a thickness ranging from about 1 nm to about 50 nm.

[0025] In some embodiments, sacrificial layer 202 is used to define the spacing between two adjacent NFET channel layers 204 and PFET channel layers 206. For example, the spacing between NFET channel layers 204A and PFET channel layers 206A can be adjusted by sacrificial layer 202B, the spacing between NFET channel layers 204B and PFET channel layers 206A can be adjusted by sacrificial layer 202C, and the spacing between PFET channel layers 206B and NFET channel layers 204B can be adjusted by sacrificial layer 202D. Therefore, the thickness of sacrificial layer 202 depends on the target distance between adjacent NFET channels and PFET channels. For example, each sacrificial layer 202 has a thickness ranging from about 1 nm to about 50 nm.

[0026] The sacrificial layer 202, the NFET channel layer 204, and the PFET channel layer 206 can be formed by one or more epitaxial or epitaxial (epi) processes. Epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes.

[0027] Figure 3A yes Figure 2A A top view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 3B From Figure 3A The cross-sectional view obtained from the section A-A' or B-B' in the diagram. Figure 3A and Figure 3BIn this process, a patterned mask 208 is formed above the topmost PFET channel layer 206B. In some embodiments, the patterned mask 208 includes silicon nitride (Si3N4), silicon oxycarbide (SiOC), silicon oxide, or combinations thereof. The patterned mask 208 can be formed, for example, by depositing a mask material (e.g., silicon nitride) layer over a layer stack LS, coating a photoresist layer over the mask material layer, patterning the photoresist layer into a photoresist mask using a photolithography process, and using the photoresist mask as an etching mask to etch the mask material layer to form the patterned mask 208.

[0028] like Figure 3A As shown in the top view, the patterned mask 208 has a cross-shaped pattern 208M, a pair of X-direction linear patterns 208X extending along the X direction at the upper and lower ends of the cross-shaped pattern 208M, and a pair of Y-direction linear patterns 208Y extending along the Y direction at the left and right ends of the cross-shaped pattern 208M. The X-direction linear patterns 208X correspond to the top view pattern of the subsequently formed n-type source / drain regions. The Y-direction linear patterns 208Y correspond to the top view pattern of the subsequently formed p-type source / drain regions. In some embodiments, the intersection angle θ of the cross-shaped pattern 208M is in the range of up to about 90 degrees.

[0029] Figure 3CThis is an enlarged top view of the patterned mask 208. The cross-shaped pattern 208M has an X-direction width X1 at the boundary between the cross-shaped pattern 208M and the X-direction linear pattern 208X. The X-direction width X1 corresponds to the channel width of the subsequently formed NFET channel and is in the range, for example, from about 0.1 nm to about 100 μm. The cross-shaped pattern 208M has a Y-direction width Y1 at the boundary between the cross-shaped pattern 208M and the Y-direction linear pattern 208X. The Y-direction width Y1 corresponds to the channel width of the subsequently formed PFET channel and is in the range, for example, from about 0.1 nm to about 100 μm. In some embodiments, the X-direction width X1 is the same as the Y-direction width Y1, so the subsequently formed NFET channel has the same channel width as the subsequently formed PFET channel. In some other embodiments, the X-direction width X1 is different from the Y-direction width Y1, so the subsequently formed NFET channel has a different channel width than the subsequently formed PFET channel. For example, when the X-direction width X1 is greater than the Y-direction width Y1, the subsequently formed NFET channel will have a larger channel width than the subsequently formed PFET channel; when the X-direction dimension X1 is smaller than the Y-direction dimension Y1, the subsequently formed NFET channel will have a smaller channel width than the subsequently formed PFET channel. As a result, the X-direction dimension X1 of the cross-shaped pattern 208M can be selected to adjust the NFET channel width and thus the NFET gate length (Lg), and the Y-direction dimension Y1 of the cross-shaped pattern 208M can be selected to adjust the PFET channel width and thus the PFET gate length (Lg), which in turn helps to adjust the current of the NFET and PFET.

[0030] exist Figure 3C In the patterned mask 208, the cross-shaped pattern 208M has an X-direction length X2 extending from a first Y-direction linear pattern 208Y in the Y-direction linear pattern 208Y to a second Y-direction linear pattern 208Y in the Y-direction linear pattern 208Y. The X-direction length X2 of the cross-shaped pattern 208M corresponds to the channel length of the subsequently formed PFET channel. The cross-shaped pattern 208M also has a Y-direction length Y2 extending from a first X-direction linear pattern 208X in the X-direction linear pattern 208X to a second X-direction linear pattern 208X in the X-direction linear pattern 208X. The Y-direction length Y2 of the cross-shaped pattern 208M corresponds to the channel length of the subsequently formed NFET channel. Figure 3C In the illustrated embodiment, the cross-shaped pattern 208M has an X-direction width X1 that is the same as the Y-direction width Y1, and an X-direction length X2 that is the same as the Y-direction length Y2. In some other embodiments, the cross-shaped pattern 208M has different dimensions. For example, in... Figure 3DIn another example of the patterned mask 208 shown, the cross-shaped pattern 208M has a Y-direction width Y1 greater than the X-direction width X1, and an X-direction length X2 less than the Y-direction length Y2. In such an embodiment, the channel width of the subsequently formed PFET channel structure (corresponding to the Y-direction width Y1) is greater than the channel width of the subsequently formed NFET channel structure (corresponding to the X-direction width X1), and the channel length of the PFET channel structure (corresponding to the X-direction length X2) is shorter than the channel length of the NFET channel structure (corresponding to the Y-direction length Y2). Dimensions X1, X2, Y1, and Y2 can be selected to ensure that the total current of the subsequently formed PFET and NFET is appropriate.

[0031] Figure 4A yes Figure 3A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 4B yes Figure 4A Top view of the structure shown. Figure 4C From Figure 4A The cross-sectional view obtained from the section A-A' or B-B' in the diagram. Figures 4A to 4C In this process, a patterned mask 208 is used as an etching mask to pattern the layer stack into a patterned layer stack PS through one or more etching processes. The one or more etching processes may include wet etching, anisotropic dry etching, or a combination thereof, and may use one or more etchants that etch the sacrificial layer 202, NFET channel layer 204, and PFET channel layer 206 at an etching rate faster than that used to etch the patterned mask 208. The top-view pattern of the patterned mask 208 is thus transferred to the underlying layers, and each layer in the resulting patterned layer stack PS (including buffer layer 201, sacrificial layer 202, NFET channel layer 204, and PFET channel layer 206) inherits the top-view pattern of the patterned mask 208. The top-view pattern of the patterned mask 208 includes a cross-shaped pattern PM, a pair of X-direction linear patterns PX located at the upper and lower ends of the cross, and a pair of Y-direction linear patterns PY at the left and right ends of the cross, as previously discussed. Figures 3C to 3D Detailed description. Therefore, when in Figure 4B When viewed in a top view, the resulting patterned layer stack PS has Y-direction sidewalls SY extending along the Y-direction on the left and right sides of the patterned layer stack PS, and X-direction sidewalls SX extending along the X-direction on the upper and lower sides of the patterned layer stack PS. Although Figures 4A to 4C The patterned layer stack PS shown has, as Figure 4CThe vertical sidewalls are shown in the cross-sectional view, but in some other embodiments, the etching process can result in tapered sidewalls, such that each layer in the patterned layer stack PS has a width that decreases with increasing distance from the substrate 200. In some embodiments, the sacrificial layer 202, NFET channel layer 204, and PFET channel layer 206 in the patterned layer stack PS have widths ranging from about 1 nm to about 500 nm (i.e., the maximum linear dimension viewed from the top).

[0032] In some embodiments, a patterned layer stack PS is formed by anisotropic dry etching. Taking anisotropic dry etching plasma etching as an example, it has... Figures 3A to 3B The substrate 200 of the illustrated structure is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a mixture of one or more of the following gases: chlorine-based gases (e.g., Cl2, SiCl4, etc.), fluorine-based gases (e.g., CF4, SF6, CH2F2, CH3F, CHF3, etc.), and hydrogen bromide (HBr) for a duration sufficient to expose the substrate 200 without causing or causing negligible damage to the patterned mask 208. By way of example and not limitation, plasma etching can be performed at RF power between about 1 and about 1000 watts (e.g., 150 watts). Once the etching process is complete, the patterned mask 208 can be removed by a selective wet etching process, for example, using H3PO4 or other suitable etchants that can selectively etch nitride materials of the patterned mask 208.

[0033] Figure 5A yes Figure 4A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 5B yes Figure 5A A top view of the structure shown, and Figure 5C From Figure 5A The cross-sectional view obtained from the section A-A' or B-B' in the diagram. Figures 5A to 5C In this configuration, a dummy gate structure 210 is formed above the patterned layer stack PS. The dummy gate structure 210 has four sides recessed from the Y-direction linear pattern PY and the X-direction linear pattern PX, respectively. Therefore, the Y-direction linear pattern PY exposed by the dummy gate structure 210 can be replaced by a p-type source / drain epitaxial structure in a subsequent process, and the X-direction linear pattern PX exposed by the dummy gate structure 210 can be replaced by an n-type source / drain epitaxial structure in a subsequent process. Thus, the Y-direction linear pattern PY is interchangeably referred to as the PFET source / drain region in the patterned stack PS, and the X-direction linear pattern PX is interchangeably referred to as the NFET source / drain region in the patterned stack PS. Figure 5BIn some embodiments shown, the dummy gate structure 210 has a square top-view profile. In some other embodiments, the dummy gate structure 210 may have a rectangular top-view profile, which has the longest linear dimension in the X or Y direction.

[0034] In some embodiments, the dummy gate structure 210 includes a dummy gate 211, which may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate 211 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, etc. For example, the dummy gate 211 may be formed by depositing the dummy gate material over a substrate 200 using physical vapor deposition (PVD), CVD, sputtering deposition, etc., and then planarizing the dummy gate material (e.g., by chemical mechanical polishing (CMP) process). Subsequently, the planarized dummy gate material is patterned using suitable photolithography and etching techniques.

[0035] like Figure 5B and Figure 5C As shown, a gate spacer 212 is formed on the sidewall of the dummy gate 211. In some embodiments of the spacer formation step, a spacer material layer is deposited on the substrate 200. The spacer material layer may be a conformal layer subsequently etched back to form the gate sidewall spacer. In the illustrated embodiment, the spacer material layer is conformally disposed on the top and sidewalls of the dummy gate 211. The spacer material layer may include a dielectric material such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. The spacer material layer can be formed by pen-depositing the dielectric material on the dummy gate 211 using a process such as CVD, subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. An anisotropic etching process is then performed on the deposited spacer material layer to expose portions of the patterned layer stack PS not covered by the dummy gate 211 (e.g., in the PFET source / drain region PY and NFET source / drain region PX of the patterned layer stack PS). This anisotropic etching process completely removes portions of the spacer material layer directly on the dummy gate 211. Portions of the spacer material layer on the sidewalls of the dummy gate 211 can be retained to form a gate spacer, referred to for simplicity as gate spacer 212.

[0036] In some embodiments, such as Figure 5B As shown in the top view, four gate spacers 212 are formed on the four sides of the square dummy gate 211. Figure 5BAs shown, when viewed from the top view, these gate spacers 212 are connected as square annular spacers surrounding the square dummy gate 211. Therefore, when in Figure 5B When viewed in the top view shown, the annular spacer 212 separates the dummy gate 211 from the PFET source / drain regions PY to the left and right of the dummy gate 211, and also separates the dummy gate 211 from the NFET source / drain regions PX to the top and bottom of the dummy gate 211. It is understood that the discussion of the square shape of the dummy gate structure and the square annular shape of the gate spacer is illustrative only, and other embodiments of the invention may include a rectangular dummy gate structure and a rectangular annular spacer surrounding the rectangular dummy gate structure. In this document, the dummy gate 211 and the surrounding gate spacer 212 may be collectively referred to as the dummy gate structure 210. For simplicity and clarity, the dashed lines indicating the potential boundary between the dummy gate 211 and the gate spacer 212 are only used for... Figure 5B and Figure 5C As shown in the figures, and will not be shown again in the accompanying drawings relating to subsequent steps.

[0037] Figure 6A yes Figure 5A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 6B yes Figure 6A Top view of the structure shown. Figure 6C From Figure 6A The cross-sectional view obtained from the mid-section A-A' Figure 6D From Figure 6A The cross-sectional view obtained from section B-B' in the diagram. Figures 6A to 6D In, for example, during an anisotropic etching step, the PFET source / drain region PY extending laterally along the X direction beyond the dummy gate structure 210 in the patterned layer stack PS is removed until the substrate 200 is exposed. The etching is performed using an etchant that etches the patterned stack PS but barely etches the dummy gate structure 210. In other words, the dummy gate structure 210 has higher etch resistance to the etching process than the patterned stack PS. Therefore, the height of the dummy gate structure 210 is substantially not reduced during the etching step. In some embodiments, the etching step is performed using an etching mask (e.g., a photoresist mask and / or a nitride mask) formed over the NFET source / drain region PX to allow the etching step to etch the PFET source / drain region PY while keeping the NFET source / drain region PX intact.

[0038] In some embodiments, anisotropic dry etching can be used to remove the PFET source / drain region PY. Taking anisotropic dry etching plasma etching as an example, the PFET source / drain region PY can be etched in a plasma environment generated by RF or microwave power in a mixture of one or more of the following gases: chlorine-based gases (e.g., Cl2, SiCl4, etc.), fluorine-based gases (e.g., CF4, SF6, CH2F2, CH3F, CHF3, etc.), and hydrogen bromide (HBr) for a duration sufficient to expose the substrate 200 beneath the PFET source / drain region PY. During this stage, because the PFET source / drain region PY has been removed, but the NFET source / drain region PX remains in the patterned layer stack PS, each layer in the patterned layer stack PS is longer in the Y direction than in the X direction.

[0039] Figure 7A yes Figure 6A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 7B yes Figure 7A Top view of the structure shown. Figure 7C From Figure 7A The cross-sectional view obtained from the section A-A' in the middle. Figure 7D From Figure 7A The cross-sectional view obtained from the section B-B'. Figures 7A to 7D In this process, the Y-direction sidewalls of the NFET channel layer 204, exposed in a previous step by removing the PFET source / drain region PY, are laterally recessed using an appropriate etching technique to form sidewall recesses R1 between the corresponding sacrificial layers 202. Although the sidewalls of the NFET channel layer 204 in the recesses R1 are... Figure 7C The middle section is shown as straight, but the sidewalls can be concave or convex. In some embodiments, the etching step is a selective etching step performed using an etching mask (e.g., a photoresist mask and / or a nitride mask) formed over the NFET source / drain region PX, such that portions of the NFET channel layer 204 in the NFET source / drain region PX remain substantially intact without lateral recesses. In other words, selective etching is performed only on the Y-direction sidewalls SY of the patterned layer stack PS by using a patterned mask that exposes only the Y-direction sidewalls of the patterned layer stack PS.

[0040] In some embodiments where the NFET channel layer 204 is GeSi and the PFET channel layer 206 is GeSn, the NFET channel layer 204 can be laterally etched using a selective etching process that etches GeSi at a faster etch rate than GeSn. For example, the NFET channel layer 204 formed of GeSi can be selectively etched using plasma etching with plasma generated from fluorine-based gases (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein the etching conditions (e.g., the flow rate of the fluorine-based gas, the plasma chamber temperature, and / or the plasma chamber pressure) are adjusted to etch GeSi at a faster etch rate than GeSn. For example, the GeSi selective etching step can be an isotropic dry etching process using CF4 as the primary precursor gas, and performed at a flow rate of CF4 gas in the range of about 1 standard cubic centimeter per minute (sccm) to about 100 sccm (e.g., 300 sccm), at an RF power in the range of about 0 W to about 1000 W (e.g., 700 W), and at a pressure in the range of about 0 Torr to about 300 Torr (e.g., 350 millitorr).

[0041] In some embodiments where the NFET channel layer 204 is Ge:B and the PFET channel layer 206 is undoped GeSi or GeSn, the NFET channel layer 204 can be laterally etched using a selective etching process that etches Ge:B at a faster etch rate than etching undoped GeSi or GeSn. For example, the NFET channel layer 204 formed of Ge:B can be selectively etched using plasma etching with plasma generated from fluorine-based gases (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), since the etch rate increases with increasing boron concentration in the aforementioned etching chemicals.

[0042] In some embodiments where the NFET channel layer 204 is Si and the PFET channel layer 206 is GeSi, the NFET channel layer 204 can be laterally etched using a selective etching process that etches Si at a faster etch rate than GeSi. For example, the NFET channel layer 204 formed of Si can be selectively etched using a fluorine-based gas (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein the etching conditions (e.g., the flow rate of the fluorine-based gas, the plasma chamber temperature, and / or the plasma chamber pressure) are adjusted to etch Si at a faster etch rate than GeSi. In some other embodiments, the NFET channel layer 204 formed of Si can be selectively etched using a wet etching process that uses tetramethylammonium hydroxide (TMAH) as a wet etchant.

[0043] In some embodiments where the NFET channel layer 204 is Ge and the PFET channel layer 206 is GeSn, the NFET channel layer 204 can be laterally etched using a selective etching process that etches Ge at a faster etch rate than GeSn. For example, the NFET channel layer 204 formed of Ge can be selectively etched using a fluorine-based gas (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein the etching conditions (e.g., the flow rate of the fluorine-based gas, the plasma chamber temperature, and / or the plasma chamber pressure) are adjusted to etch Ge at a faster etch rate than GeSn. For example, the Ge selective etching step can be an isotropic dry etching process using NF3 as the primary precursor gas, and performed at a flow rate of NF3 gas in the range of about 1 standard cubic centimeter per minute (sccm) to about 100 sccm (e.g., 7 sccm), at a room temperature in the range of about 0 degrees Celsius to about 100 degrees Celsius (e.g., 14 degrees Celsius), and at a pressure in the range of about 1 to about 100 tors (e.g., 7 tors).

[0044] Figure 8A yes Figure 7A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 8B yes Figure 8A Top view of the structure shown. Figure 8C From Figure 8A The cross-sectional view obtained from the section A-A' in the middle. Figure 8D From Figure 8A The cross-sectional view obtained from section B-B' in the diagram. Figures 8A to 8D In this configuration, after the NFET channel layer 204 is laterally recessed, an internal spacer 214 of the PFET is formed in the sidewall recess R1. The internal spacer 214 of the PFET acts as an isolation component between the subsequently formed PFET source / drain epitaxial structure and the NFET channel layer 204.

[0045] The internal spacer 214 is formed from an internal spacer layer, which is deposited using a conformal deposition process such as CVD, ALD, etc. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as a low-k material with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the internal spacer 214. While the outer sidewalls of the internal spacer 214 are shown flush with the sidewalls of the PFET channel layer 206 and the sacrificial layer 202, the outer sidewalls of the internal spacer 214 may extend beyond or be recessed from the sidewalls of the PFET channel layer 206 and the sacrificial layer 202. Furthermore, while the outer sidewalls of the internal spacer 214 are... Figure 8A and Figure 8C The spacer 214 is shown as straight, but the outer sidewalls of the inner spacer 214 may be concave or convex. The inner spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc. In some embodiments, the thickness of the inner spacer 214 is in the range of about 0.1 nm to about 50 nm.

[0046] Figure 9A yes Figure 8A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 9B yes Figure 9A Top view of the structure shown. Figure 9C From Figure 9A The cross-sectional view obtained from the section A-A' in the middle. Figure 9D From Figure 9A The cross-sectional view obtained from section B-B' in the diagram. Figures 9A to 9D In this embodiment, a bottom dielectric isolation structure 216 is formed on the substrate 200. In some embodiments, the bottom dielectric isolation structure 216 is located in the region of the previously removed PFET source / drain region PY. In some other embodiments, the bottom dielectric isolation structure 216 covers all exposed areas of the substrate 200. The bottom dielectric isolation structure 216 can be used to electrically isolate the subsequently formed p-type source / drain epitaxial structure from the underlying substrate 200, which in turn avoids unwanted leakage current in the substrate 200, thereby avoiding unwanted short circuits between the source / drain epitaxial structures.

[0047] In some embodiments, the bottom dielectric isolation structure 216 may be an oxide (such as silicon oxide), a nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based materials are deposited and post-cured in a remote plasma system to transform them into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process may be used. Once the dielectric material has been deposited, it may be selectively etched back to below the bottommost one of the PFET channel layers 206, which in turn allows for the epitaxial growth of a p-type source / drain structure from the exposed surface of the PFET channel layer 206 directly above the bottom dielectric isolation structure 216. In some embodiments, the etched-back dielectric material is patterned using suitable photolithography and etching techniques to form the bottom dielectric isolation structure 216 located in the region of the previously removed PFET source / drain region PY.

[0048] Figure 10A yes Figure 9A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 10B yes Figure 10A Top view of the structure shown. Figure 10C From Figure 10A The cross-sectional view obtained from the section A-A' in the middle. Figure 10D From Figure 10A The cross-sectional view obtained from section B-B'. It should be understood that, for clarity, Figure 10A The perspective view and subsequent perspective views are compared with the previous perspective view (e.g., Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A To depict from different perspectives. Figures 10A to 10D In this configuration, p-type epitaxial source / drain structures 218 are formed on the previously removed PFET source / drain region PY, and the PFET channel layer 206 extends continuously from a first p-type epitaxial source / drain structure 218 in the p-type epitaxial source / drain structures 218 to a second p-type epitaxial source / drain structure 218 in the p-type epitaxial source / drain structures 218. In some embodiments, the p-type epitaxial source / drain structures 218 may apply compressive strain to the PFET channel layer 206, thereby improving PFET device performance. The p-type epitaxial source / drain structures 218 are spaced apart along the X direction, with dummy gate structures 210 located therebetween. In some embodiments, the p-type epitaxial source / drain structures 218 are spaced apart from the dummy gate structures 210 because the dummy gate structures 210 have opposing sidewalls that are laterally recessed from the corresponding sidewalls of the PFET channel layer 206. In some embodiments, the internal spacer 214 is used to separate the p-type epitaxial source / drain structure 218 from the NFET channel layer 204 by an appropriate lateral distance, so that the p-type epitaxial source / drain structure 218 is not short-circuited with the NFET channel layer 204.

[0049] In some embodiments, the epitaxial source / drain structure 218 may include any acceptable material suitable for the PFET. For example, if the PFET channel layer 206 is Ge 1-x Sn x The p-type epitaxial source / drain structure 218 may include a material on which compressive strain is applied to the PFET channel layer 206, such as Ge. 1-y Sn y Where y > x. In some embodiments, the epitaxial source / drain structure 218 includes Si, Ge, Sn, and Si 1-x Ge x Si 1-x-y Ge x Sn yIII-V compounds, etc. In some embodiments, epitaxial growth is performed using a patterned mask formed over a substrate 200 other than the target region directly above the bottom dielectric isolation structure 216. As a result, epitaxial growth occurs only on the exposed surface of the PFET channel layer 206 and exposes the sacrificial layer 202 in the region directly above the bottom dielectric isolation structure 216, which in turn prevents unwanted epitaxial growth of the semiconductor layer in the NFET source / drain region PX. In some embodiments, epitaxial growth can be performed using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. In some embodiments, the p-type epitaxial source / drain structures 218 each have a thickness ranging from about 1 nm to about 100 μm.

[0050] A p-type epitaxial structure 218 can be formed by implanting a p-type dopant (e.g., boron or gallium) into the p-type epitaxial structure 218, followed by an annealing process. The source / drain structure 218 can have a density of approximately 1 x 10⁻⁶. 17 atoms / cm 3 1x10 22 atoms / cm 3 The concentration of p-type impurities (e.g., boron or gallium) is between these values. In some embodiments, p-type dopants can be used to in-situ dope the p-type epitaxial structure 218 during growth.

[0051] Figure 11A yes Figure 10A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 11B yes Figure 11A Top view of the structure shown. Figure 11C From Figure 11A The cross-sectional view obtained from the section A-A' in the middle. Figure 11D From Figure 11A The cross-sectional view obtained from section B-B' in the diagram. Figures 11A to 11D In the anisotropic etching step, for example, the NFET source / drain region PX extending laterally beyond the dummy gate structure 210 in the patterned layer stack PS is removed until the substrate 200 is exposed. The etching is performed using an etchant that etches the patterned stack PS but barely etches the dummy gate structure 210. In other words, the dummy gate structure 210 has higher etch resistance to the etching process than the patterned stack PS. Therefore, the height of the dummy gate structure 210 is substantially not reduced during the etching step. In some embodiments, the etching step is performed using an etching mask (e.g., a photoresist mask and / or a nitride mask) formed over the p-type epitaxial source / drain structure 218 to allow the etching step to etch the NFET source / drain region PX while keeping the p-type epitaxial source / drain structure 218 intact.

[0052] In some embodiments, anisotropic dry etching can be used to remove the NFET source / drain region PX. Taking anisotropic dry etching plasma etching as an example, the NFET source / drain region PX can be etched by maintaining a plasma environment generated by RF or microwave power in a mixture of one or more of the following gases: chlorine-based gases (e.g., Cl2, SiCl4, etc.), fluorine-based gases (e.g., CF4, SF6, CH2F2, CH3F, CHF3, etc.), and hydrogen bromide gas (HBr) for a duration sufficient to expose the substrate 200 beneath the NFET source / drain region PX.

[0053] Figure 12A yes Figure 11A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 12B yes Figure 12A Top view of the structure shown. Figure 12C From Figure 12A The cross-sectional view obtained from the section A-A' in the middle. Figure 12D From Figure 12A The cross-sectional view obtained from section B-B' in the diagram. Figures 12A to 12D In this process, the X-direction sidewalls of the PFET channel layer 206, exposed in a previous step by removing the NFET source / drain region PX, are laterally recessed using an appropriate etching technique to form sidewall recesses R2 between the corresponding sacrificial layers 202. Although the sidewalls of the PFET channel layer 206 in the recesses R2 are... Figure 12D The middle section is shown as straight, but the sidewalls may be concave or convex. In some embodiments, the etching step is a selective etching step performed using an etching mask (e.g., a photoresist mask and / or a nitride mask) formed over the p-type epitaxial source / drain structure 218. More specifically, selective etching is performed only on the X-direction sidewalls SX of the patterned layer stack PS by using a patterned mask that exposes only the X-direction sidewalls of the patterned layer stack PS.

[0054] In some embodiments where the NFET channel layer 204 is GeSi and the PFET channel layer 206 is GeSn, the PFET channel layer 206 can be laterally etched using a selective etching process that etches GeSn at a faster etch rate than GeSi. For example, the PFET channel layer 206 formed of GeSn can be selectively etched using plasma etching with plasma generated from fluorine-based gases (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein the etching conditions (e.g., the flow rate of the fluorine-based gas, the plasma chamber temperature, and / or the plasma chamber pressure) are adjusted to etch GeSn at a faster etch rate than GeSi. For example, a GeSn selective etching step can be an isotropic dry etching process using NF3 as the primary precursor gas, and performed at a flow rate of NF3 gas from about 1 standard cubic centimeter per minute (sccm) to about 1000 sccm, at a room temperature ranging from about 0 degrees Celsius to about 100 degrees Celsius, and at a pressure ranging from about 1 to about 300 tors. As previously discussed with respect to the selective etching of the NFET channel layer 204 formed from GeSi, plasma etching using fluorine-based gases can also be used to selectively etch GeSi. In that case, the GeSn selective etching process is performed under different process conditions (e.g., fluorine-based gas flow rate, room temperature, and / or room pressure) than the GeSi selective etching process. In other words, the process conditions can be adjusted to selectively etch either GeSn or GeSi.

[0055] In some embodiments where the NFET channel layer 204 is Ge:B and the PFET channel layer 206 is undoped GeSi or GeSn, the PFET channel layer 206 can be laterally etched using a selective etching process that etches the undoped GeSi or GeSn at a faster etch rate than etching Ge:B. For example, the PFET channel layer 206 formed of undoped GeSi or GeSn can be selectively etched using plasma etching with plasma generated from fluorine-based gases (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein etching conditions (e.g., fluorine-based gas flow rate, plasma chamber temperature, and / or plasma chamber pressure) are adjusted to etch the undoped GeSi or GeSn at a faster etch rate than etching Ge:B. In some embodiments, the PFET channel layer 206 formed of GeSn or GeSi can be selectively etched using a wet etching process that uses hydrogen peroxide (H2O2) as a wet etchant, because the etch rate in H2O2 etching decreases with increasing boron concentration.

[0056] In some embodiments where the NFET channel layer 204 is Si and the PFET channel layer 206 is GeSi, the PFET channel layer 206 can be laterally etched using a selective etching process that etches GeSi at a faster etch rate than etching Si. For example, the PFET channel layer 206 formed of GeSi can be selectively etched using fluorine-based gases (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein the etching conditions (e.g., the flow rate of the fluorine-based gas, the plasma chamber temperature, and / or the plasma chamber pressure) are adjusted to etch GeSi at a faster etch rate than etching Si. As previously discussed regarding the selective etching of the NFET channel layer 204 formed of Si, plasma etching using fluorine-based gases can also be used to selectively etch Si. In that case, the GeSi selective etching process is performed under different process conditions (e.g., the flow rate of the fluorine-based gas, the chamber temperature, and / or the chamber pressure) than the Si selective etching process. In other words, the process conditions can be adjusted to selectively etch either GeSi or Si.

[0057] In some embodiments where the NFET channel layer 204 is Ge and the PFET channel layer 206 is GeSn, the PFET channel layer 206 can be laterally etched using a selective etching process that etches GeSn at a faster etch rate than etching Ge. For example, the PFET channel layer 206 formed of GeSn can be selectively etched using plasma etching with plasma generated from fluorine-based gases (e.g., CF4, NF3, etc.), oxygen (e.g., O2), and / or nitrogen (e.g., N2), wherein the etching conditions (e.g., the flow rate of the fluorine-based gas, the plasma chamber temperature, and / or the plasma chamber pressure) are adjusted to etch GeSn at a faster etch rate than etching Ge. For example, a GeSn selective etching step can be an isotropic dry etching process using NF3 as the primary precursor gas, and performed at a flow rate of NF3 gas ranging from about 1 standard cubic centimeter per minute (sccm) to about 100 sccm, at a room temperature ranging from about 0 degrees Celsius to about 100 degrees Celsius, and at a pressure ranging from about 0 Torr to about 300 Torr. As previously discussed with respect to the selective etching of the NFET channel layer 204 formed of Ge, plasma etching using fluorine-based gases can also be used to selectively etch Ge. In that case, the GeSn selective etching process is performed under different process conditions (e.g., fluorine-based gas flow rate, room temperature, and / or room pressure) than the Ge selective etching process. In other words, the process conditions can be adjusted to selectively etch GeSn or Ge.

[0058] Figure 13A yes Figure 12A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 13B yes Figure 13A Top view of the structure shown. Figure 13C From Figure 13A The cross-sectional view obtained from the section A-A' in the middle. Figure 13D From Figure 13A The cross-sectional view obtained from section B-B' in the diagram. Figures 13A to 13D In the process, after the laterally recessed PFET channel layer 206, an NFET internal spacer 220 is formed in the sidewall recess R2. The NFET internal spacer 220 serves as an isolation component between the subsequently formed NFET source / drain epitaxial structure and the PFET channel layer 206.

[0059] The NFET internal spacer 220 is formed by an internal spacer layer, which is deposited using a conformal deposition process such as CVD, ALD, etc. The internal spacer layer can include materials such as silicon nitride or silicon oxynitride, although any suitable material can be used, such as low-k materials with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the internal spacer layer 220. Although Figure 13D The outer sidewall of the internal spacer layer 220 shown is flush with the sidewalls of the NFET channel layer 204 and the sacrificial layer 202, but the outer sidewall of the internal spacer 220 may extend beyond or be recessed from the sidewalls of the NFET channel layer 204 and the sacrificial layer 202. Furthermore, although the outer sidewall of the internal spacer 220 is... Figure 13A and Figure 13D The spacer 220 is shown as straight, but the outer sidewalls of the inner spacer 220 may be concave or convex. The inner spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc. In some embodiments, the thickness of the inner spacer 220 is in the range of about 0.1 nm to about 500 nm.

[0060] Figure 14A yes Figure 13A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 14B yes Figure 14A Top view of the structure shown. Figure 14C From Figure 14A The cross-sectional view obtained from the section A-A' in the middle. Figure 14D From Figure 14A The cross-sectional view obtained from section B-B' in the diagram. Figures 14A to 14DIn this embodiment, a bottom dielectric isolation structure 222 is formed on the substrate 200. In some embodiments, the bottom dielectric isolation structure 222 is located in the region of the previously removed NFET source / drain region PX. In some other embodiments, the bottom dielectric isolation structure 222 covers all exposed areas of the substrate 200. The bottom dielectric isolation structure 222 can be used to electrically isolate the subsequently formed n-type source / drain epitaxial structure from the underlying substrate 200, which will in turn avoid unwanted leakage current in the substrate 200, thereby avoiding unwanted short circuits between the source / drain epitaxial structures.

[0061] In some embodiments, the bottom dielectric isolation structure 222 may be an oxide (such as silicon oxide), a nitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based materials are deposited and post-cured in a remote plasma system to transform them into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process may be used. Once the dielectric material has been deposited, it may be selectively etched back to below the bottommost one of the NFET channel layers 204, which in turn allows for the epitaxial growth of an n-type source / drain structure from the exposed surface of the NFET channel layer 204 directly above the bottom dielectric isolation structure 222. In some embodiments, the etched-back dielectric material is patterned using suitable photolithography and etching techniques to form the bottom dielectric isolation structure 222 in a region located in the previously removed NFET source / drain region PX. In some embodiments, the bottom dielectric isolation structure 222 is formed of the same dielectric material as the bottom dielectric isolation structure 216 used to isolate the p-type epitaxial source / drain structure 218 from the substrate 200.

[0062] Figure 15A yes Figure 14A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 15B yes Figure 15A Top view of the structure shown. Figure 15C From Figure 15A The cross-sectional view obtained from the section A-A' in the middle. Figure 15D From Figure 15A The cross-sectional view obtained from section B-B' in the diagram. Figures 15A to 15DIn this configuration, an n-type epitaxial source / drain structure 224 is formed on a previously removed NFET source / drain region PX, and an NFET channel layer 204 extends continuously from a first n-type epitaxial source / drain structure 224 in the n-type epitaxial source / drain structure 224 to a second n-type epitaxial source / drain structure 224 in the n-type epitaxial source / drain structure 224. In some embodiments, the n-type epitaxial source / drain structure 224 may apply tensile strain to the NFET channel layer 204, thereby improving NFET device performance. The n-type epitaxial source / drain structures 224 are spaced apart along the Y direction, with dummy gate structures 210 located therebetween. In some embodiments, the n-type epitaxial source / drain structures 224 are spaced apart from the dummy gate structures 210 because the dummy gate structures 210 have sidewalls that are laterally recessed from the corresponding sidewalls of the NFET channel layer 204. In some embodiments, the internal spacer 220 is used to separate the n-type epitaxial source / drain structure 224 from the PFET channel layer 206 by an appropriate lateral distance, such that the n-type epitaxial source / drain structure 224 is not short-circuited with the PFET channel layer 206.

[0063] In some embodiments, the epitaxial source / drain structure 224 may comprise any acceptable material suitable for an NFET. For example, the n-type epitaxial source / drain structure 224 may comprise phosphorus-doped silicon (Si:P). In some embodiments, epitaxial growth is performed using a patterned mask formed over a substrate 200, except for the region directly above the bottom dielectric isolation structure 222. As a result, epitaxial growth occurs only on the exposed surface of the NFET channel layer 204 and exposes the sacrificial layer 202 in the region directly above the bottom dielectric isolation structure 222, thereby preventing unwanted epitaxial growth from occurring in other regions. In some embodiments, epitaxial growth may be performed using CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. In some embodiments, the n-type epitaxial structure 224 has a thickness ranging from about 1 nm to about 100 μm.

[0064] An n-type epitaxial structure 224 can be formed by implanting an n-type dopant (e.g., phosphorus or arsenic) into the epitaxial structure 224, followed by an annealing process. The resulting source / drain structure 224 can have an n-type source / drain structure of approximately 1 × 10⁻⁶. 17 atoms / cm 3 1×10 22 atoms / cm 3 The concentration of n-type impurities (e.g., phosphorus or arsenic) is between these values. In some embodiments, n-type dopants can be used to in-situ dope the n-type epitaxial structure 224 during growth.

[0065] Figure 16A yes Figure 15A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 16B yes Figure 16A Top view of the structure shown. Figure 16C From Figure 16A The cross-sectional view obtained from the section A-A' in the middle. Figure 16D From Figure 16A The cross-sectional view obtained from section B-B' in the diagram. Figures 16A to 16D In one or more etching steps, the dummy gate structure 210 is removed, thereby forming a gate trench GT1 in the space surrounded by the p-type epitaxial source / drain structure 218 and the n-type epitaxial source / drain structure 224. In some embodiments, the dummy gate structure 210 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate structure 210 at a faster rate than other materials on the etching substrate 200. In some embodiments, dummy gate removal etching is performed using an etching mask (e.g., a photoresist mask and / or a nitride mask) formed on the p-type epitaxial source / drain structure 218 and the n-type epitaxial source / drain structure 224, thus preventing unwanted damage to these source / drain structures. In some embodiments, an interlayer dielectric (ILD) is formed over the p-type epitaxial source / drain structure 218 and the n-type epitaxial source / drain structure 224 prior to the dummy gate removal step, and the ILD is not removed and is therefore retained in the final IC product.

[0066] Figure 17A yes Figure 16A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 17B yes Figure 17A Top view of the structure shown. Figure 17C From Figure 17A The cross-sectional view obtained from the section A-A' in the middle. Figure 17D From Figure 17A The cross-sectional view obtained from section B-B' in the diagram. Figures 17A to 17D In this process, the buffer layer 201 and the sacrificial layer 202 are removed by selective etching, thereby forming openings O1 between adjacent pairs in the NFET channel layer 204 and the PFET channel layer 206, respectively, with openings O1 located below the bottom NFET channel layer 204A. In this manner, the PFET channel layer 206 is suspended above the substrate 200 and connected to the p-type source / drain structure 218, and the NFET channel layer 204 is also suspended above the substrate 200 and connected to the n-type source / drain structure 224. The NFET channel layer 204 and the PFET channel layer 206 are alternately arranged in the gate trench GT1 and spaced apart by openings O1.

[0067] This step can be interchangeably referred to as the channel release process. In this intermediate processing step, the opening O1 can be filled with ambient conditions (e.g., air, nitrogen, etc.). The selective etching process removes the material of the buffer layer 201 and the sacrificial layer 202 (e.g., Ge) at a rate faster than or substantially non-etching the material of the NFET channel layer 204 (e.g., GeSi) and PFET channel layer 206 (e.g., GeSi). For example, the Ge selective etching step can be an isotropic dry etching process using NF3 as the primary precursor gas, and performed at a flow rate of NF3 gas in the range of about 1 standard cubic centimeter per minute (sccm) to about 100 sccm (e.g., 7 sccm), at a room temperature in the range of about 0 degrees Celsius to about 100 degrees Celsius (e.g., 14 degrees Celsius), and at a pressure in the range of about 1 to about 100 tors (e.g., 7 tors).

[0068] Figure 18A yes Figure 17A A perspective view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 18B yes Figure 18A Top view of the structure shown. Figure 18C From Figure 18A The cross-sectional view obtained from the section A-A' in the middle. Figure 18D From Figure 18A The cross-sectional view obtained from section B-B' in the diagram. Figures 18A to 18D In this process, a replacement gate structure 230 is formed. The replacement gate structure 230 can be a high-k / metal gate stack, however other compositions are also possible. The replacement gate structure 230 forms a gate associated with the multi-channel provided by the NFET channel layer 204, and also forms a gate associated with the multi-channel provided by the PFET channel layer 206. The replacement gate structure 230 thus serves as the final gate for the NFET formed by the NFET channel layer 204 and the PFET formed by the PFET channel layer 206. In other words, the NFET channel layer 204 and the PFET channel layer 206 share the same gate structure, so the gate terminals of the resulting NFET and the gate terminals of the resulting PFET are coupled together to function as an inverter, reducing space requirements due to the overlap of the NFET and PFET channel layers 204 and 206.

[0069] An alternative gate structure 230 is formed within a gate trench GT1 and an opening O1 provided by the release NFET and PFET channel layers 204 and 206. In some embodiments, the alternative gate structure 230 includes a gate dielectric layer 226 formed over the top and bottom surfaces of each of the NFET and PFET channel layers 204 and 206, and a metal gate 228 formed over the gate dielectric layer 226. In some embodiments, the gate dielectric layer 226 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer over the interface layer. As used and described herein, a high-k gate dielectric includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermally heated silicon oxide (~3.9). The metal gate 228 includes one or more work-function metal layers and a fill metal formed over the one or more work-function metal layers. The one or more work-function metal layers and fill metal used in the high-k / metal gate structure may include metals, metal alloys, or metal silicides. Additionally, the formation of high-k / metal gate stacks may include deposition to form various gate materials, one or more pad layers, and one or more CMP processes to remove excess gate material. Gate dielectric layer 226 is... Figure 18B Top view and Figure 18C and Figure 18D As shown in the cross-sectional view, for simplicity and clarity, [the details are not shown in the original text]. Figure 18A As shown in the perspective view.

[0070] In some embodiments, the interface layer of the gate dielectric layer 226 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 226 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 226 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (La2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0071] The metal gate 228 includes one or more n-type work function metal (N-metal) layers and / or one or more p-type work function metal (P-metal) layers. The n-type work function metal may, exemplarily, include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC), tungsten carbide (WC)), aluminum compounds, and / or other suitable materials. The p-type work function metal may, exemplarily, include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. The metal gate may also include fill metal to fill the remaining portion of the gate trench GT1 and the opening O1. The filler metal may include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0072] Figure 19A yes Figure 18A A top view of an intermediate stage in inverter manufacturing, following the stage shown. Figure 19B From Figure 19A The cross-sectional view obtained from the section A-A' in the middle. Figure 19C From Figure 19A The cross-sectional view obtained from section B-B' in the diagram. Figures 19A to 19C In the process, gate contact 232 is formed above replacement gate structure 230, and common source / drain contact (e.g., common drain contact) 234 is formed in the first p-type source / drain structure 218 of p-type source / drain structure 218 (e.g., in...). Figure 18B In the top view of the p-type source / drain structure 218 on the left and the first n-type source / drain structure 224 in the n-type source / drain structure 224 (e.g., in...) Figure 18BIn the top view of the n-type source / drain structure 224, above the lower n-type source / drain structure 224, a PFET source / drain contact (e.g., a PFET source contact) 236 is formed above the second p-type source / drain structure 218 of the p-type source / drain structure 218, and an NFET source / drain contact (e.g., an NFET source contact) 238 is formed above the second n-type source / drain structure 224 of the n-type source / drain structure 224. The common source / drain contact 234 has a first portion 234Y extending along the Y direction above the first p-type source / drain structure 218 and a second portion 234X extending along the X direction above the first n-type source / drain structure 224 of the n-type source / drain structure 224. The first portion 234Y is connected to the left end of the second portion 234X, such that the common source / drain contact 234 has an L-shaped top view profile. The PFET source / drain contact 236 is disconnected from the common source / drain contact 234 and electrically coupled to Vdd, and the NFET source / drain contact 238 is disconnected from the common source / drain contact 234 and electrically coupled to ground (e.g., Vss), thereby forming an inverter. In some embodiments, the contact 236 coupled to Vdd can be interchangeably referred to as the Vdd contact, and the contact 238 coupled to Vss can be interchangeably referred to as the Vss contact. Figures 19A to 19C As shown, the inverter is formed by NFETs and PFETs sharing a vertical overlap region, which in turn reduces the inverter's footprint to, for example, about 0.006 μm. 2 From approximately 0.007 μm 2 (For example, approximately 0.0064 μm) 2 ).

[0073] exist Figures 19A to 19C In the illustrated embodiment, the number of NFET channel layers 204 is the same as the number of PFET channel layers 206. However, in some other embodiments, the number of NFET channel layers and PFET channel layers can be different to balance the current in the inverter. For example, as Figure 20A and Figure 20B As shown, the inverter includes a single NFET channel layer 204 and three PFET channel layers 206 above the NFET channel layer 204. This inverter can be used with... Figures 2A to 19C To manufacture using similar steps as shown, except... Figures 2A to 2B In addition to the layer stacking steps shown, epitaxial growth is modified to form a single NFET channel layer and three PFET channel layers above the NFET channel layer. Alternatively, as... Figure 21A and Figure 21B As shown, the inverter includes three NFET channel layers 204 and a single PFET channel layer 206 above the NFET channel layers 204. This inverter can be used with... Figures 2A to 19C To manufacture using similar steps as shown, except... Figures 2A to 2B In addition to the layer stacking steps shown, epitaxial growth is modified to form three NFET channel layers and a PFET channel layer above the NFET channel layers. Alternatively, as... Figure 22A and Figure 22B As shown, the inverter comprises three alternating PFET channel layers 206 and two NFET channel layers 204. This inverter can be used as follows: Figures 2A to 19C The manufacturing process is similar to that shown, except that... Figures 2A to 2B In addition to the layer stacking steps shown, the epitaxial growth was modified to alternately grow three PFET channel layers and two NFET channel layers.

[0074] Based on the above discussion, it can be seen that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and no particular advantage is necessary for all embodiments. One advantage is that the inverter's footprint is reduced because the NFET and PFET share an overlap region and a single gate structure. Another advantage is that the vertical spacing between the NFET channel layer and the PFET channel layer can be easily controlled by the thickness of the sacrificial layer formed between the NFET channel layer and the PFET channel layer. Another advantage is that the number of PFET channel layers and the number of NFET channel layers can be selected to balance the inverter current. Another advantage is that the cross-shaped pattern of the NFET channel layer and PFET channel layer stack can be used to adjust the NFET gate length and PFET gate length, thereby optimizing the total current of the NFET and PFET. Another advantage is that the vertically stacked NFET and PFET can be fabricated simultaneously in the same front-end process (FEOL) process, so the NFET and PFET have the same thermal budget.

[0075] In some embodiments, a method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate and forming a second semiconductor layer over the first semiconductor layer, the first and second semiconductor layers having a first sidewall extending along a first direction and a second sidewall extending along a second direction different from the first direction. A first internal spacer is formed on the first sidewall of the first semiconductor layer; a p-type source / drain structure is formed on the first sidewall of the second semiconductor layer; a second internal spacer is formed on the second sidewall of the second semiconductor layer; an n-type source / drain structure is formed on the second sidewall of the first semiconductor layer; and a gate structure is formed at least partially between the first and second semiconductor layers. In some embodiments, the second semiconductor layer is formed of a material different from the first semiconductor layer. In some embodiments, the first semiconductor layer has tensile strain. In some embodiments, the second semiconductor layer has compressive strain. In some embodiments, the method further includes etching the first sidewall of the first semiconductor layer before forming the first internal spacer, such that the first sidewall of the first semiconductor layer is laterally recessed from the first sidewall of the second semiconductor layer. In some embodiments, the method further includes etching the second sidewall of the second semiconductor layer before forming the second internal spacer, such that the second sidewall of the second semiconductor layer is laterally recessed from the second sidewall of the first semiconductor layer. In some embodiments, the method further includes forming a bottom dielectric isolation structure on a substrate after forming a first internal spacer, wherein p-type source / drain structures are formed on the bottom dielectric isolation structure. In some embodiments, the method further includes forming a bottom dielectric isolation structure on a substrate after forming a second internal spacer, wherein n-type source / drain structures are formed on the bottom dielectric isolation structure. In some embodiments, the method further includes forming a third semiconductor layer over a first semiconductor layer before forming a second semiconductor layer; and removing the third semiconductor layer after forming the p-type source / drain structures and the n-type source / drain structures to form an opening between the first semiconductor layer and the second semiconductor layer, wherein a gate structure is at least partially formed in the opening between the first semiconductor layer and the second semiconductor layer. In some embodiments, the method further includes forming a common source / drain contact electrically connecting one of the p-type source / drain structures to one of the n-type source / drain structures. In some embodiments, the common source / drain contact has an L-shaped top view profile.

[0076] In some embodiments, a method of manufacturing a semiconductor includes forming a layer stack on a substrate, the layer stack including an NFET channel layer, a PFET channel layer, and a sacrificial layer located between the NFET channel layer and the PFET channel layer; performing a first selective etch process on opposing first sidewalls of the layer stack, wherein the first selective etch process etches the NFET channel layer at an etch rate faster than etching the PFET channel layer; after performing the first selective etch process, forming a p-type epitaxial structure on the first sidewall of the layer stack; performing a second selective etch process on opposing second sidewalls of the layer stack, wherein the second selective etch process etches the PFET channel layer at an etch rate faster than etching the NFET channel layer; after performing the second selective etch process, forming an n-type epitaxial structure on the second sidewall of the layer stack; and replacing the sacrificial layer with a gate structure. In some embodiments, the method further includes forming an internal spacer on the first sidewall of the layer stack after performing the first selective etch process and before forming the p-type epitaxial structure, wherein the internal spacer is positioned on the NFET channel layer. In some embodiments, the method further includes forming an internal spacer on a second sidewall of the layer stack after performing a second selective etching process and before forming an n-type epitaxial structure, wherein the internal spacer is positioned on the PFET channel layer. In some embodiments, replacing the sacrificial layer with a gate structure includes performing a third selective etching process to remove the sacrificial layer, leaving an opening between the PFET channel layer and the NFET channel layer; and forming a gate structure at least partially in the opening between the PFET channel layer and the NFET channel layer.

[0077] In some embodiments, the semiconductor device includes a gate structure, n-type source / drain components, p-type source / drain components, an NFET channel, and a PFET channel. The gate structure is located above a substrate. The n-type source / drain components and the p-type source / drain components are disposed around the gate structure. In a top view, the gate structure has a quadrilateral profile, with the n-type source / drain components located at opposite first and second sides of the quadrilateral profile of the gate structure, and the p-type source / drain components located at opposite third and fourth sides of the quadrilateral profile of the gate structure, respectively. The NFET channel extends within the gate structure and connects to the n-type source / drain components. The PFET channel extends within the gate structure and connects to the p-type source / drain components. In a cross-sectional view, the NFET channel and the PFET channel are vertically separated by the gate structure. In some embodiments, the device further includes a first internal spacer separating the NFET channel from a first p-type source / drain component in the p-type source / drain components, and a second internal spacer separating the NFET channel from a second p-type source / drain component in the p-type source / drain components. In some embodiments, the device further includes a third internal spacer separating the PFET channel from a first n-type source / drain component in the n-type source / drain components, and a fourth internal spacer separating the PFET channel from a second n-type source / drain component in the n-type source / drain components. The first and second internal spacers are spaced apart along a first direction, and the third and fourth internal spacers are spaced apart along a second direction different from the first direction. In some embodiments, the device further includes a common source / drain contact electrically connecting one of the p-type source / drain components and one of the n-type source / drain components, and the common source / drain contact has an L-shaped top view profile. In some embodiments, the device further includes a Vdd contact above one of the p-type source / drain components and a Vss contact above one of the n-type source / drain components. Viewed from the top, the Vdd and Vss contacts extend in different directions.

[0078] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first semiconductor layer is formed on a substrate and a second semiconductor layer is formed above the first semiconductor layer, the first semiconductor layer and the second semiconductor layer having a first sidewall extending along a first direction and a second sidewall extending along a second direction different from the first direction; A first internal spacer is formed on the first sidewall of the first semiconductor layer; A p-type source / drain structure is formed on the first sidewall of the second semiconductor layer; A second internal spacer is formed on the second sidewall of the second semiconductor layer; An n-type source / drain structure is formed on the second sidewall of the first semiconductor layer; as well as A gate structure is formed that is at least partially located between the first semiconductor layer and the second semiconductor layer.

2. The method according to claim 1, wherein, The second semiconductor layer is formed of a different material than the first semiconductor layer.

3. The method according to claim 1, wherein, The first semiconductor layer has tensile strain.

4. The method according to claim 1, wherein, The second semiconductor layer has compressive strain.

5. The method according to claim 1, further comprising: Before forming the first internal spacer, the first sidewall of the first semiconductor layer is etched such that the first sidewall of the first semiconductor layer is laterally recessed from the first sidewall of the second semiconductor layer.

6. The method according to claim 1, further comprising: Before forming the second internal spacer, the second sidewall of the second semiconductor layer is etched such that the second sidewall of the second semiconductor layer is laterally recessed from the second sidewall of the first semiconductor layer.

7. The method according to claim 1, further comprising: After the first internal spacer is formed, a bottom dielectric isolation structure is formed on the substrate, wherein the p-type source / drain structures are respectively formed on the bottom dielectric isolation structure.

8. The method according to claim 1, further comprising: After the second internal spacer is formed, a bottom dielectric isolation structure is formed on the substrate, wherein the n-type source / drain structures are respectively formed on the bottom dielectric isolation structure.

9. The method according to claim 1, further comprising: A third semiconductor layer is formed on top of the first semiconductor layer before the second semiconductor layer is formed; and After forming the p-type source / drain structure and the n-type source / drain structure, the third semiconductor layer is removed to form an opening between the first semiconductor layer and the second semiconductor layer. The gate structure is at least partially formed in the opening between the first semiconductor layer and the second semiconductor layer.

10. The method according to claim 1, further comprising: A common source / drain contact is formed to electrically connect one of the p-type source / drain structures to one of the n-type source / drain structures.

11. The method according to claim 10, wherein, The common source / drain contact has an L-shaped top view profile.

12. A method for manufacturing a semiconductor device, comprising: A layer stack is formed on a substrate, the layer stack including an NFET channel layer, a PFET channel layer and a sacrificial layer located between the NFET channel layer and the PFET channel layer; A first selective etching process is performed on the opposing first sidewalls of the stacked layers, wherein the first selective etching process etches the NFET channel layer at a faster etching rate than etching the PFET channel layer. After performing the first selective etching process, a p-type epitaxial structure is formed on the first sidewall of the stacked layer; A second selective etching process is performed on the opposing second sidewalls of the stacked layers, wherein the second selective etching process etches the PFET channel layer at a faster etching rate than etching the NFET channel layer; After performing the second selective etching process, an n-type epitaxial structure is formed on the second sidewall of the stacked layer; and Replace the sacrificial layer with a gate structure.

13. The method of claim 12, further comprising: After performing the first selective etching process and before forming the p-type epitaxial structure, an internal spacer is formed on the first sidewall of the layer stack, wherein the internal spacer is positioned on the NFET channel layer.

14. The method of claim 12, further comprising: After performing the second selective etching process and before forming the n-type epitaxial structure, an internal spacer is formed on the second sidewall of the layer stack, wherein the internal spacer is positioned on the PFET channel layer.

15. The method according to claim 12, wherein, Replacing the sacrificial layer with the gate structure includes: A third selective etching process is performed to remove the sacrificial layer, leaving an opening between the PFET channel layer and the NFET channel layer; and The gate structure is formed at least partially in the opening between the PFET channel layer and the NFET channel layer.

16. A semiconductor device, comprising: The gate structure is located above the substrate; n-type source / drain components and p-type source / drain components are disposed around the gate structure, wherein, in a top view, the gate structure has a quadrilateral profile, the n-type source / drain components are located on opposite first and second sides of the quadrilateral profile of the gate structure, and the p-type source / drain components are located on opposite third and fourth sides of the quadrilateral profile of the gate structure, respectively. An NFET channel extends within the gate structure and connects the n-type source / drain components; and The PFET channel extends within the gate structure and connects the p-type source / drain components. In a cross-sectional view, the NFET channel and the PFET channel are vertically spaced apart by the gate structure.

17. The semiconductor device of claim 16, further comprising: The first internal spacer separates the NFET channel from the first p-type source / drain component in the p-type source / drain component; and The second internal spacer separates the NFET channel from the second p-type source / drain component in the p-type source / drain component.

18. The semiconductor device of claim 17, further comprising: The third internal spacer separates the PFET channel from the first n-type source / drain component in the n-type source / drain component; and A fourth internal spacer separates the PFET channel from the second n-type source / drain component in the n-type source / drain component, wherein the first internal spacer and the second internal spacer are spaced apart along a first direction, and the third internal spacer and the fourth internal spacer are spaced apart along a second direction different from the first direction.

19. The semiconductor device of claim 16, further comprising: A common source / drain contact electrically connects one of the p-type source / drain components and one of the n-type source / drain components, the common source / drain contact having an L-shaped top view profile.

20. The semiconductor device of claim 16, further comprising: The Vdd contact is located above one of the p-type source / drain components; and The Vss contact is located above one of the n-type source / drain components, wherein, in a top view, the Vdd contact and the Vss contact extend in different directions.

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