Antifuse array structure and memory

Abstract

Embodiments of the present application relate to the field of semiconductor circuit design, and more particularly to an antifuse array structure and memory, comprising: a plurality of antifuse integrated structures arranged in an antifuse matrix along the bitline and wordline extension directions; the antifuse integrated structure comprising: a first antifuse storage MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse storage MOS transistor sharing a common active area; the first switch transistor and the second switch transistor are each controlled by two adjacent wordlines, a common terminal of the first switch transistor and the second switch transistor being connected to the bitline; the first antifuse storage MOS transistor and the second antifuse storage MOS transistor are each controlled by adjacent programming wires, and the programming wires are also used to control adjacent antifuse integrated structures along the bitline extension direction. This allows a memory array of the same capacity to occupy a smaller layout area, thereby increasing the spacing between antifuse storage cells within the original layout area.

Description

Technical Field

[0001] The present application relates to the field of semiconductor circuit design, and in particular to an antifuse array structure and a memory. Background Art

[0002] Semiconductor devices are essential for many modern applications. Memory devices, used to store data, play a crucial role within these devices. With technological advancements, the capacity of memory devices continues to increase; in other words, the density of memory arrays arranged on substrates is increasing.

[0003] For antifuse memories, as the density of the memory array increases, the spacing between antifuse memory cells decreases, making it difficult to ensure the electrical isolation effect of electrical components between the antifuse memory cells.

[0004] Therefore, there is an urgent need to improve the layout of the antifuse array structure to ensure the electrical isolation effect of the electrical components between the antifuse memory cells. Summary of the Invention

[0005] The embodiments of the present application provide an antifuse array structure and a memory, and provide a new antifuse array layout method to achieve a memory array of the same capacity occupying only a smaller layout area, thereby increasing the spacing between antifuse memory cells on the basis of the original layout area, and ensuring the electrical isolation effect of the electrical components between the antifuse memory cells.

[0006] An embodiment of the present application provides an antifuse array structure, comprising: a plurality of antifuse integrated structures arranged in an antifuse matrix in a bit line extension direction and a word line extension direction, wherein the bit line extension direction and the word line extension direction intersect; each antifuse integrated structure comprises: a first antifuse storage MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse storage MOS transistor, which are sequentially arranged along the extension direction of an active region, wherein the first antifuse storage MOS transistor, the first switch transistor, the second switch transistor, and the second antifuse storage MOS transistor share an active region, wherein the extension directions of the active regions intersect with the extension directions of the bit line and the word line, respectively; the first switch transistor and the second switch transistor are respectively controlled by two adjacent word lines, a common end of the first switch transistor and the second switch transistor is connected to the bit line, and the first antifuse storage MOS transistor and the second antifuse storage MOS transistor are respectively controlled by adjacent programming wires, and in the bit line extension direction, the programming wires are also used to control adjacent antifuse integrated structures.

[0007] The antifuse integrated structure includes a first antifuse storage MOS transistor, a second antifuse storage MOS transistor, a first switch transistor and a second switch transistor, wherein the first antifuse storage MOS transistor and the second antifuse storage MOS transistor are controlled by adjacent programming wires, that is, two antifuse storage cells are controlled by adjacent programming wires, and the first switch transistor and the second switch transistor serve as switch transistors of the antifuse storage cells and are controlled by adjacent word lines; it is known to those skilled in the art that in the antifuse array, the extension direction of the programming wire is the same as the extension direction of the word line, that is, the extension direction of the programming wire is perpendicular to the extension direction of the bit line; wherein, in the bit line In the bit line extension direction, the programming conductor is also used to control two adjacent antifuse integrated structures arranged along the bit line extension direction. The same programming conductor is used to control an antifuse storage unit in two adjacent antifuse integrated structures connected to the same bit line, and the two antifuse storage units belong to two adjacent antifuse integrated structures respectively, thereby reducing the layout length of the antifuse storage array in the bit line extension direction; on the basis of the original layout area and layout of the storage array with the same capacity, the spacing between the switch unit and the antifuse storage unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components of the antifuse storage array.

[0008] In addition, the active area includes an active area body, the length direction of the active area body is the extension direction of the active area, and in the extension direction of the active area, the width of the active area body is the same at all locations to ensure that the spacing between the active devices in the antifuse matrix is ​​the same, further ensuring the electrical isolation effect of the active devices in the antifuse matrix.

[0009] In addition, the active region includes a raised portion disposed on at least one side of the main active region body. In the direction of extension of the active region, the raised portion is shorter than the main active region body, and the width of the central portion of the active region is greater than the width of the active region at both ends. The provision of the raised portion increases the width-to-length ratio of the active region where the first and second switching transistors are located, thereby improving the conductivity of the first and second switching transistors and preventing data read errors in the anti-fuse memory cell caused by poor conductivity between the first and second switching transistors.

[0010] In addition, the active area includes a protrusion, and in a direction perpendicular to the extension direction of the active area, the protrusions of two adjacent active areas are located on different sides of the active area body.

[0011] In addition, in the bit line extension direction, the gate of the second anti-fuse storage MOS transistor of each anti-fuse integrated structure and the gate of the first anti-fuse storage MOS transistor of the adjacent anti-fuse integrated structure are connected to the same programming wire.

[0012] In addition, the gate of the first antifuse storage MOS tube is connected to the first programming wire; the gate of the first switch tube is connected to the first word line, the source is connected to the first antifuse storage MOS tube, and the drain is connected to the bit line; the gate of the second switch tube is connected to the second word line, the source is connected to the second antifuse storage MOS tube, and the drain is connected to the bit line; the gate of the second antifuse storage MOS tube is connected to the second programming wire.

[0013] In addition, the active area includes: a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region arranged in sequence along the extension direction of the active area; the first doped region is the vacant end of the first anti-fuse MOS tube, the second doped region is the common end of the first anti-fuse storage MOS tube and the first switch tube, the third doped region is the common end of the first switch tube and the second switch tube, the fourth doped region is the common end of the second switch tube and the second anti-fuse storage MOS tube, and the fifth doped region is the vacant end of the second anti-fuse MOS tube; the bit line is electrically connected to the third doped region.

[0014] The antifuse array structure also includes an insulating layer covering the active region, wherein the bit lines are disposed on the insulating layer. The insulating layer also includes a conductive via that exposes the top surface of the third doped region; and a conductive layer that fills the conductive via, with one end contacting the third doped region and one end contacting the bit lines, thereby electrically connecting the bit lines to the third doped region. A bit line extension layer connects the bit lines to the conductive layer, ensuring stable electrical contact between the bit lines and the conductive layer and preventing conductive defects in the resulting antifuse matrix.

[0015] Furthermore, the conductive vias are located on the same straight line in the direction of the bit line extension and in the direction of the word line extension. By regularly positioning the conductive vias, the subsequent bit lines can be arranged along a straight line, simplifying the bit line formation process.

[0016] In addition, the gate of the first anti-fuse storage MOS tube is set on the top surface of the active area between the first doping area and the second doping area, the gate of the first switching tube is set on the top surface of the active area between the second doping area and the third doping area, the gate of the second switching tube is set on the top surface of the active area between the third doping area and the fourth doping area, and the gate of the second anti-fuse storage MOS tube is set on the top surface of the active area between the fourth doping area and the fifth doping area.

[0017] In addition, the gate of the first anti-fuse storage MOS tube is buried in the active area between the first doping area and the second doping area, the gate of the first switching tube is buried in the active area between the second doping area and the third doping area, the gate of the second switching tube is buried in the active area between the third doping area and the fourth doping area, and the gate of the second anti-fuse storage MOS tube is buried in the active area between the fourth doping area and the fifth doping area.

[0018] Furthermore, the antifuse matrix includes multiple columns of antifuse integrated structures arranged along the wordline extension direction. The bit lines connected to the first column of antifuse integrated structures serve as first dummy bit lines, while the bit lines connected to the last column of antifuse integrated structures serve as second dummy bit lines. By providing dummy bit lines at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures at the edges of the matrix is ​​consistent with that of the antifuse integrated structures within the matrix, preventing defects in the antifuse memory cells at the edges from causing malfunction.

[0019] In addition, the antifuse matrix includes multiple rows of antifuse integrated structures arranged along the bit line extension direction. The gates of the first antifuse MOS transistors in the first row of antifuse integrated structures are connected to a first dummy programming conductor, and the gates of the second antifuse MOS transistors in the last row of antifuse integrated structures are connected to a second dummy programming conductor. By providing dummy programming conductors at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures at the edges of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures within the matrix, preventing defects in the antifuse memory cells at the edges from causing malfunction.

[0020] In addition, the gate of the first switch transistor in the first row of antifuse integrated structures is connected to the first dummy word line, and the gate of the second switch transistor in the last row of antifuse integrated structures is connected to the second dummy word line. The first dotted programming wire and the second dummy programming wire are located at the outermost edge of the antifuse matrix, while the first and second dummy word lines are located at the second outermost edge of the antifuse matrix. By providing dummy word lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures at the edge of the antifuse matrix is ​​consistent with that of the antifuse integrated structures within the matrix, preventing defects in the antifuse memory cells at the edge from causing malfunction.

[0021] An embodiment of the present application further provides a memory including a memory array, wherein the memory array adopts the above-mentioned antifuse array structure.

[0022] In the direction of bit line extension, the layout length of the antifuse memory array is reduced. Therefore, based on the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A circuit diagram of an antifuse integrated structure provided in one embodiment of the present application;

[0024] Figure 2 A circuit diagram of an antifuse matrix provided in one embodiment of the present application;

[0025] Figure 3A schematic diagram of connecting an antifuse memory cell to the same programming wire in an adjacent antifuse integrated structure provided by one embodiment of the present application;

[0026] Figure 4 and Figure 5 A schematic top view of the layout structure of an antifuse integrated structure provided in one embodiment of the present application;

[0027] Figure 6 A schematic cross-sectional diagram of a layout structure of an antifuse integrated structure provided in one embodiment of the present application;

[0028] Figure 7 A schematic cross-sectional view of a layout structure of another antifuse integrated structure provided in one embodiment of the present application;

[0029] Figure 8 and Figure 9 A schematic diagram of a layout structure of an antifuse matrix provided in one embodiment of the present application;

[0030] Figure 10 and Figure 11 A schematic diagram of the layout structure of the bit lines in the antifuse matrix provided in one embodiment of the present application;

[0031] Figure 12 A schematic diagram of a virtual structure of a memory provided in another embodiment of the present application;

[0032] Figure 13 A timing diagram of the programming phase and the reading phase of a memory provided by another embodiment of the present application. DETAILED DESCRIPTION

[0033] For antifuse memories, as the density of the memory array increases, the spacing between antifuse memory cells decreases, making it difficult to ensure the electrical isolation effect of electrical components between the antifuse memory cells.

[0034] An embodiment of the present application provides an antifuse array structure and a new antifuse array layout method to achieve a storage array of the same capacity occupying only a smaller layout area, thereby increasing the spacing between antifuse storage cells on the basis of the original layout area, thereby ensuring the electrical isolation effect of the electrical components between the antifuse storage cells.

[0035] Those skilled in the art will appreciate that, in the various embodiments of this application, many technical details are provided to help readers better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can still be implemented.

[0036] Figure 1 A circuit diagram of the antifuse integrated structure provided in this embodiment, Figure 2A circuit diagram of the antifuse matrix provided in this embodiment, Figure 3 The schematic diagram of connecting an antifuse memory cell to the same programming wire in adjacent antifuse integrated structures provided in this embodiment is as follows: Figure 4 and Figure 5 A schematic top view of the layout structure of the antifuse integrated structure provided in this embodiment, Figure 6 A schematic cross-sectional view of the layout structure of an antifuse integrated structure provided in this embodiment is shown in FIG. Figure 7 A schematic cross-sectional view of the layout structure of another antifuse integrated structure provided in this embodiment, Figure 8 and Figure 9 A schematic diagram of a layout structure of an antifuse matrix provided in this embodiment, Figure 10 and Figure 11 This is a schematic diagram of the layout structure of the bit lines in the antifuse matrix provided in this embodiment. The antifuse array structure provided in this embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0037] refer to Figure 1 and Figure 2 , an antifuse array structure, comprising:

[0038] Multiple antifuse integrated structures 100 (refer to Figure 1 ), arranged in an antifuse matrix in the extending direction of the bit line BL and the word line WL (reference Figure 2 ), the extending direction of the bit line BL intersects with the extending direction of the word line WL.

[0039] It should be noted that the drawings of this embodiment use the example in which the extension direction of the bit line BL and the extension direction of the word line WL are perpendicular to each other for illustration, and do not constitute a limitation of this embodiment. In other embodiments, the extension direction of the bit line BL and the extension direction of the word line WL can be appropriately adjusted so that the extension direction of the bit line BL and the extension direction of the word line WL intersect but are not perpendicular.

[0040] Combine Figure 4 and Figure 5 Each antifuse integrated structure 100 includes: a first antifuse storage MOS transistor 101, a first switch transistor 111, a second switch transistor 112, and a second antifuse storage MOS transistor 102 arranged in sequence along the extension direction of the active area 200, and the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 share the active area 200.

[0041] The extension direction of the active region 200 intersects with the extension direction of the bit line BL and the extension direction of the word line WL.

[0042] The first switch transistor 111 and the second switch transistor 112 are respectively controlled by two adjacent word lines WL. The common end of the first switch transistor 111 and the second switch transistor 112 is connected to the bit line BL. The first anti-fuse storage MOS transistor 101 and the second anti-fuse storage MOS transistor are respectively controlled by the programming wire PGM between the two word lines WL. In the extension direction of the bit line BL, the programming wire PGM is also used to control the adjacent anti-fuse integrated structure 100.

[0043] It should be noted that Figure 2 It is only a partial schematic diagram of the formed anti-fuse matrix, which is only used to reflect the arrangement of the anti-fuse matrix in the embodiment of the present application, and does not constitute a limitation on the number of bit lines BL, word lines WL and programming conductors PGM. In specific use, the number of corresponding bit lines BL, word lines WL and programming conductors PGM can be selected according to the required capacity of the storage array; in addition, the values ​​in "<>" are only used to distinguish different bit lines BL, word lines WL or programming conductors PGM, and do not constitute a limitation on this embodiment.

[0044] The antifuse integrated structure 100 includes a first antifuse storage MOS transistor 101, a second antifuse storage MOS transistor 102, a first switch transistor 111, and a second switch transistor 112. The first antifuse storage MOS transistor 101 and the second antifuse storage MOS transistor 102 are controlled by adjacent programming wires PGM, that is, two antifuse storage cells are controlled by adjacent programming wires PGM, and the first switch transistor 111 and the second switch transistor 112 serve as switch transistors of the antifuse storage cells and are controlled by adjacent word lines WL. It is known to those skilled in the art that in the antifuse array, the extension direction of the programming wire PGM is the same as the extension direction of the word line WL, that is, the programming wire PGM is connected to the antifuse array. The extension direction of the PGM is perpendicular to the extension direction of the bit line BL. In the extension direction of the bit line BL, the programming conductor PGM is also used to control two adjacent anti-fuse integrated structures 100 arranged along the extension direction of the bit line BL. The same programming conductor PGM is used to control an anti-fuse memory cell in two adjacent anti-fuse integrated structures 100 connected to the same bit line BL, thereby reducing the layout length of the anti-fuse memory array in the extension direction of the bit line BL. On the basis of the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the anti-fuse memory cell located in the same active area is increased to ensure the electrical isolation effect of the electrical components of the anti-fuse memory array.

[0045] Specifically, the gate of the first anti-fuse storage MOS transistor 101 is connected to the first programming wire PGM <1> The gate of the first switch tube 111 is connected to the first word line WL <1> One end of the source or drain is connected to the first anti-fuse storage MOS tube 101, and the other end is connected to the bit line BL. The gate of the second switch tube 112 is connected to the second word line WL <2> One end of the source or drain is connected to the second anti-fuse storage MOS tube 102, and the other end is connected to the bit line BL. The gate of the second anti-fuse storage MOS tube 102 is connected to the second programming wire PGM. <2> .

[0046] In addition, reference Figure 3 In the extending direction of the bit line BL, for any two adjacent anti-fuse integrated structures 100, the gate of the second switch tube 112 of one anti-fuse integrated structure 100 is connected to the word line WL <n-2>The gate of the second anti-fuse storage MOS transistor 102 is connected to the programming wire PGM <m>Another anti-fuse integrated structure 100 of the first anti-fuse storage MOS tube 101 gate connected to the programming wire PGM <m>The gate of the first switch 111 is connected to the word line WL <n-1>In the direction of extension of the bit line BL, the first switch tube 111 and the second switch tube 112 in any two adjacent anti-fuse integrated structures 100 are connected to the bit line BL <n>superior.

[0047] That is, in the extending direction of the bit line BL, the gate of the second anti-fuse storage MOS transistor 102 of each anti-fuse integrated structure 100 is connected to the same programming wire PGM as the gate of the first anti-fuse storage MOS transistor 101 of the adjacent anti-fuse integrated structure 100. <m>.

[0048] It should be noted that in other examples, it can also be set as follows: in the bit line extension direction, the gate of the first anti-fuse storage MOS tube of each anti-fuse integrated structure is connected to the same programming wire as the gate of the second anti-fuse storage MOS tube of the adjacent anti-fuse integrated structure.

[0049] refer to Figure 4 and Figure 5 , for the first anti-fuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112 and the second anti-fuse storage MOS transistor 102 arranged in the same active area; Figure 5 In one example, the active area 200 includes an active area body, the length direction of the active area body is the extension direction of the active area 200, and the width of the active area body is the same at all locations in the extension direction of the active area 200, so as to ensure that the spacing between each active device in the antifuse matrix is ​​the same, and further ensure the electrical isolation effect of each active device in the antifuse matrix.

[0050] Furthermore, the active area also includes a raised portion, which is disposed on at least one side of the main active area body, specifically on at least one side along the length of the active area. Along the extension direction of the active area 200, the raised portion is shorter than the length of the main active area body; along the extension direction of the word line WL, the width of the central portion of the active area 200 is greater than the width of the ends of the active area 200. The raised portion and the main active area body are used to form the first switching transistor 111 and the second switching transistor 112, so that the channel width of the first switching transistor 111 and the second switching transistor 112 is the sum of the widths of the raised portion and the main active area body. The protrusion is provided to increase the width-to-length ratio of the active region where the first switch transistor 111 and the second switch transistor 112 are located, thereby improving the conductivity of the first switch transistor 111 and the second switch transistor 112. This ensures that sufficient fuse voltage flows through the first anti-fuse storage MOS transistor 101 and the second anti-fuse storage MOS transistor 102, thereby avoiding data reading and writing errors in the anti-fuse storage unit caused by poor conductivity of the first switch transistor 111 and the second switch transistor 112. In addition, the increase in the width of the central portion of the active region 200 also facilitates the preparation of the first switch transistor 111 and the second switch transistor 112.

[0051] In one example, the active region 200 includes a raised portion. For two adjacent antifuse integrated structures 100 in the same row, the raised portions of the two adjacent active regions are located on different sides of the main body of the active region 200 in a direction perpendicular to the extension of the active region 200. By having the raised portions of the two adjacent rows of antifuse integrated structures 100 located on different sides of the main body of the active region, the active regions of the two adjacent rows can be closely arranged while increasing the area of ​​the active region, thereby reducing the area of ​​the antifuse array structure.

[0052] In this example, for two adjacent antifuse integrated structures 100 in the same column, in the direction perpendicular to the extension of the active region 200, the protrusions of the two adjacent active regions can be located on the same side or different sides of the main body of the active region 200; in another example, referring to Figure 4 The active area 200 includes two protrusions, which are arranged on opposite sides of the active area body, and the protrusions are symmetrically arranged based on the active area body.

[0053] In some embodiments, along the extending direction of the bit line BL, the orthographic projections of the active regions of two adjacent antifuse integrated structures 100 on a plane perpendicular to the extending direction of the bit line BL at least partially overlap, thereby further reducing the area of ​​the antifuse array structure.

[0054] In some embodiments, along the direction of word line WL extension, the orthographic projections of the active regions of two adjacent antifuse integrated structures 100 on a plane perpendicular to the direction of bit line BL extension at least partially overlap, thereby further reducing the area of ​​the antifuse array structure.

[0055] Specifically, refer to Figure 6 and Figure 7 , the active area 200 includes:

[0056] A first doping region 212 , a second doping region 222 , a third doping region 232 , a fourth doping region 242 and a fifth doping region 252 are sequentially arranged along the extending direction of the active region 200 .

[0057] Among them, the active area 200 is surrounded by an isolation region 201, the first doped region 212 is the vacant end of the first anti-fuse storage MOS tube 101; the second doped region 222 is the common end of the first anti-fuse storage MOS tube 101 and the first switch tube 111; the third doped region 232 is the common end of the first switch tube 111 and the second switch tube 112; the fourth doped region 242 is the common end of the second switch tube 112 and the second anti-fuse storage MOS tube 102; and the fifth doped region 252 is the vacant end of the second anti-fuse storage MOS tube 102.

[0058] That is, the source of the first anti-fuse storage MOS transistor 101 is idle, and the drain is connected to the drain of the first switch transistor 111. The source of the first switch transistor 111 is connected to the bit line BL, so that after the first switch transistor 111 is turned on, the first anti-fuse storage MOS transistor 101 and the bit line BL are electrically connected. The source of the second anti-fuse storage MOS transistor 102 is idle, and the drain is connected to the drain of the second switch transistor 112. The source of the second switch transistor 112 is connected to the bit line BL, so that after the second switch transistor 112 is turned on, the second anti-fuse storage MOS transistor 102 and the bit line BL are electrically connected.

[0059] Since the first switch 111 and the second switch 112 have the same source connection relationship, the layout area of ​​the antifuse integrated structure 100 can be reduced by sharing the source, that is, by sharing the same doping region.

[0060] For the anti-fuse memory cell, the anti-fuse MOS tube is controlled by the programming line PGM to form a memory cell. The word line WL controls the switch tube to facilitate the writing of storage data on the bit line BL. When the corresponding word line WL is selected, the anti-fuse memory cell is electrically connected to the bit line BL. The discharge speed of the anti-fuse memory cell on the bit line BL (after a preset time, by comparing the bit line BL voltage with the standard voltage) can be used to determine whether the anti-fuse memory cell is broken down, thereby obtaining the 1-bit binary data stored in the anti-fuse memory cell.

[0061] In a specific example, refer to Figure 6 The gate of the first antifuse storage MOS transistor 101 is arranged on the top surface of the active region 200 between the first doping region 212 and the second doping region 222. The gate of the first switch transistor 111 is arranged on the top surface of the active region 200 between the second doping region 222 and the third doping region 232. The gate of the second switch transistor 112 is arranged on the top surface of the active region 200 between the third doping region 232 and the fourth doping region 242. The gate of the second antifuse storage MOS transistor 102 is arranged on the top surface of the active region 200 between the fourth doping region 242 and the fifth doping region 252. That is, the active regions of the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are arranged in a top-gate manner.

[0062] In a specific example, refer to Figure 7 The gate of the first antifuse storage MOS transistor 101 is buried in the active region 200 between the first doping region 212 and the second doping region 222. The gate of the first switch transistor 111 is buried in the active region 200 between the second doping region 222 and the third doping region 232. The gate of the second switch transistor 112 is buried in the active region 200 between the third doping region 232 and the fourth doping region 242. The gate of the second antifuse storage MOS transistor 102 is buried in the active region 200 between the fourth doping region 242 and the fifth doping region 252. That is, the active regions of the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are arranged in a buried gate manner.

[0063] Combine Figure 6 and Figure 7 The antifuse integrated structure 100 further includes an insulating layer 203 covering the active region 200 , and a bit line BL ( 205 ) is disposed on the insulating layer 203 and electrically connected to the third doped region 232 .

[0064] Specifically, the insulating layer 200 has a conductive through hole (not shown) and a conductive layer 204, the conductive through hole (not shown) exposes the top surface of the third doped region 232; the conductive layer 204 fills the conductive through hole (not shown), one end of which contacts the third doped region 232 and the other end contacts the BL (205) so that the bit line is electrically connected to the third doped region 232.

[0065] For the layout diagram of the antifuse matrix, refer to Figure 8 and Figure 10 The antifuse matrix includes multiple rows of antifuse integrated structures 100 arranged along the extension direction of the bit line BL and multiple columns of antifuse integrated structures 100 arranged along the extension direction of the word line WL. Each row of antifuse integrated structure 100 includes multiple antifuse integrated structures 100 arranged along the extension direction of the word line WL, and each column of antifuse integrated structure 100 includes multiple antifuse integrated structures 100 arranged along the extension direction of the bit line BL.

[0066] refer to Figure 9 and Figure 11 , in the extending direction of the bit line BL, the conductive vias are located on the same straight line; in the extending direction of the word line WL, the conductive vias are located on the same straight line. The conductive layer 204 (refer to Figure 6 and Figure 7 ) are located on the same straight line in the extending direction of the word line WL and the extending direction of the bit line BL. By regularly arranging the positions of the conductive through holes, the subsequent BL (205) can be arranged along a straight line, thereby simplifying the formation process of the bit line BL (205).

[0067] In one example, the antifuse integrated structures 100 connected by the same word line WL are arranged at equal intervals. That is, in the extending direction of the word line WL, the spacing between adjacent antifuse integrated structures 100 is equal, to avoid the situation where the spacing between adjacent antifuse integrated structures 100 is too small to damage the overall electrical isolation effect of the antifuse memory array.

[0068] In one example, the antifuse integrated structures 100 connected by the same bit line BL are arranged at equal intervals. That is, in the extending direction of the bit line BL, the spacing between adjacent antifuse integrated structures 100 is equal to avoid the situation where the spacing between adjacent antifuse integrated structures 100 is too small to damage the overall electrical isolation effect of the antifuse memory array.

[0069] In one example, the bit line BL connected to the first column of antifuse integrated structures 100 is the first dummy bit line Dummy1, and the bit line BL connected to the last column of antifuse integrated structures 100 is the second dummy bit line Dummy2. By providing dummy bit lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures within the matrix, thereby preventing defects in the antifuse memory cells at the edge from causing malfunction.

[0070] In one example, the gate of the first storage MOS transistor 101 in the first row of antifuse integrated structures 100 is connected to a first dummy programming wire Dummy3, and the gate of the second storage MOS transistor in the last row of antifuse integrated structures 100 is connected to a second dummy programming wire Dummy4. By providing dummy programming wires at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures within the matrix, preventing defects in the antifuse storage cells at the edge from causing malfunction.

[0071] Furthermore, the gate of the first switch tube 111 in the first row of antifuse integrated structures 100 is connected to the first virtual word line Dummy5, ​​and the gate of the second switch tube 112 in the last row of antifuse integrated structures 100 is connected to the second virtual word line Dummy6. The first dotted programming wire Dummy3 and the second virtual programming wire Dummy4 are located at the outermost side of the antifuse matrix, and the first virtual word line Dummy5 and the second virtual word line Dummy6 are located at the second outermost side of the antifuse matrix. By setting up virtual word lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​guaranteed to be consistent with that of the antifuse integrated structures within the matrix, thereby preventing defects in the antifuse storage cells at the edge from malfunctioning.

[0072] The embodiment of the present application reduces the layout length of the antifuse memory array in the bit line extension direction. Therefore, based on the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure.

[0073] It should be noted that the specific connection method of the "source" and "drain" defined above does not constitute a limitation on the embodiments of this application. In other embodiments, the connection method of "drain" replacing "source" and vice versa can be adopted. In addition, in order to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that other units do not exist in this embodiment.

[0074] Another embodiment of the present application also provides a memory, wherein the memory array of the memory applies the antifuse array structure provided in the above embodiment. By applying the antifuse array structure provided in the above embodiment as the memory array, on the basis of the original layout area and layout of the memory array with the same capacity, the spacing between the switch unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure.

[0075] Figure 12 A schematic diagram of the virtual structure of the memory provided in this embodiment, Figure 13 The following is a timing diagram of the programming phase and the reading phase of the memory provided by this embodiment. The memory provided by this embodiment is further described in detail with reference to the accompanying drawings, as follows:

[0076] refer to Figure 12 The memory includes: a memory array 403, which adopts the antifuse array structure provided by the above embodiment; a control unit 401, which is used to receive a row address signal Row_ADD, a programming enable signal PGM_En and a word line enable signal WL_En; a row selection control unit 402, which is connected to the memory array 403 and the control unit 401, and is used to generate a programming selection signal PGM according to the row address signal Row_ADD and the programming enable signal PGM_En. <n 2:0>, generates a word line selection signal WL according to the row address signal Row_ADD and the word line enable signal WL_En <n:0>; A column selection control unit 404 is connected to the memory array 403 and is used to turn on the corresponding bit line WL of the memory array 403 according to a bit line selection signal (not shown).

[0077] Among them, the programming enable signal PGM_En is used to indicate that the programming wire is turned on, and the word line enable signal WL_En is used to indicate that the bit line is turned on; the programming selection signal PGM_En is used to indicate that the programming wire is turned on. <n 2:0>Used to turn on the programming conductor PGM in the corresponding memory array 403; word line selection signal WL <n:0>It is used to turn on the word line WL in the corresponding memory array 403 .

[0078] Specific reference Figure 13 In the programming phase, the programming enable signal PGM_En and the row address signal Row_ADD are provided to generate the programming selection signal PGM <n 2:0>, to select the corresponding anti-fuse MOS tube to fuse to form an anti-fuse storage unit, and through the word line selection signal WL <n:0>The control switch is turned on and data is written to the anti-fuse memory cell through the corresponding bit line BL. In the read phase, the word line enable signal WL_En and the row address signal Row_ADD are provided to generate the word line selection signal WL <n:0>, so as to select the corresponding anti-fuse memory cell and electrically connect it to the bit line BL.

[0079] Through the common control of the bit line BL and the word line WL, when the corresponding word line WL is selected, the anti-fuse memory unit is electrically connected to the bit line BL, and the discharge speed of the charge on the bit line BL is controlled by the anti-fuse memory unit (after a preset time, the voltage of the bit line BL is adjusted by comparing it with the standard voltage V REF Comparison), it can be determined whether the anti-fuse memory cell is broken down, thereby obtaining 1 bit of binary data stored in the anti-fuse memory cell.

[0080] It should be noted that, since the programming conductor PGM in this embodiment is connected to two anti-fuse memory cells controlled by different word lines WL, the programming selection signal PGM <n 2:0>The required high level duration must cover twice the word line selection signal WL <n:0>is high for a period of time to complete data programming.

[0081] It is worth mentioning that all units involved in this embodiment are logical units. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this application, this embodiment does not include units that are not closely related to solving the technical problem proposed by this application. However, this does not mean that other units do not exist in this embodiment.

[0082] It should be noted that, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems raised by this application, but this does not mean that there are no other units in this embodiment; ordinary technicians in this field can understand that the above-mentioned embodiments are specific embodiments for implementing this application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of this application. < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / m>

Claims

1. An antifuse array structure, characterized in that: include: A plurality of antifuse integrated structures are arranged into an antifuse matrix in a bit line extension direction and a word line extension direction, wherein the bit line extension direction and the word line extension direction intersect; Each antifuse integrated structure includes: a first antifuse storage MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse storage MOS transistor sequentially arranged along an extension direction of an active region, wherein the first antifuse storage MOS transistor, the first switch transistor, the second switch transistor, and the second antifuse storage MOS transistor share the active region, and the extension direction of the active region intersects with the extension direction of the bit line and the extension direction of the word line respectively; The first switch transistor and the second switch transistor are respectively controlled by two adjacent word lines, a common terminal of the first switch transistor and the second switch transistor is connected to a bit line, the first anti-fuse storage MOS transistor and the second anti-fuse storage MOS transistor are respectively controlled by adjacent programming wires, and in the direction in which the bit lines extend, the programming wires are also used to control adjacent anti-fuse integrated structures; The active region includes an active region body, the length direction of the active region body is the extension direction of the active region, and the width of the active region body at all locations in the extension direction of the active region is the same; The active area further includes a protrusion, which is arranged on at least one side of the active area body. In the extension direction of the active area, the length of the protrusion is smaller than the length of the active area body, and the width of the middle of the active area is larger than the width of both ends of the active area.

2. The antifuse array structure according to claim 1, wherein: The active area includes one protruding portion, and in a direction perpendicular to an extension direction of the active area, the protruding portions of two adjacent active areas are located on different sides of the main body of the active area.

3. The antifuse array structure according to claim 1, wherein: In the extending direction of the bit line, the gate of the second anti-fuse storage MOS transistor of each anti-fuse integrated structure is connected to the same programming wire as the gate of the first anti-fuse storage MOS transistor of the adjacent anti-fuse integrated structure.

4. The antifuse array structure according to claim 1, wherein: include: The gate of the first anti-fuse storage MOS tube is connected to a first programming wire; The gate of the first switch tube is connected to the first word line, the source is connected to the first anti-fuse storage MOS tube, and the drain is connected to the bit line; The gate of the second switch tube is connected to the second word line, the source is connected to the second anti-fuse storage MOS tube, and the drain is connected to the bit line; The gate of the second anti-fuse storage MOS tube is connected to the second programming wire.

5. The antifuse array structure according to claim 1, wherein: The active region includes: A first doping region, a second doping region, a third doping region, a fourth doping region and a fifth doping region arranged in sequence along an extension direction of the active region; The first doped region is an idle end of the first anti-fuse MOS transistor, the second doped region is a common end of the first anti-fuse storage MOS transistor and the first switch transistor, the third doped region is a common end of the first switch transistor and the second switch transistor, the fourth doped region is a common end of the second switch transistor and the second anti-fuse storage MOS transistor, and the fifth doped region is an idle end of the second anti-fuse MOS transistor; The bit line is electrically connected to the third doping region.

6. The antifuse array structure according to claim 5, wherein: Also includes: an insulating layer covering the active area, wherein the bit line is arranged on the insulating layer; The insulating layer further comprises a conductive through hole, wherein the conductive through hole exposes the top surface of the third doping region; A conductive layer fills the conductive through hole, one end of the conductive layer contacts the third doping region, and the other end contacts the bit line, so that the bit line is electrically connected to the third doping region.

7. The antifuse array structure according to claim 6, wherein: include: In the direction of extension of the bit line, the conductive through holes are located on the same straight line; In the word line extending direction, the conductive vias are located on the same straight line.

8. The antifuse array structure according to claim 5, wherein: The gate of the first anti-fuse storage MOS tube is set on the top surface of the active area between the first doping area and the second doping area, the gate of the first switching tube is set on the top surface of the active area between the second doping area and the third doping area, the gate of the second switching tube is set on the top surface of the active area between the third doping area and the fourth doping area, and the gate of the second anti-fuse storage MOS tube is set on the top surface of the active area between the fourth doping area and the fifth doping area.

9. The antifuse array structure according to claim 5, wherein: The gate of the first anti-fuse storage MOS tube is buried in the active area between the first doping area and the second doping area, the gate of the first switch tube is buried in the active area between the second doping area and the third doping area, the gate of the second switch tube is buried in the active area between the third doping area and the fourth doping area, and the gate of the second anti-fuse storage MOS tube is buried in the active area between the fourth doping area and the fifth doping area.

10. The antifuse array structure according to claim 1, wherein: The antifuse matrix includes multiple columns of antifuse integrated structures arranged along the word line extension direction, wherein the bit lines connected to the antifuse integrated structures in the first column are first virtual bit lines, and the bit lines connected to the antifuse integrated structures in the last column are second virtual bit lines.

11. The antifuse array structure according to claim 1, wherein: The antifuse matrix includes multiple rows of antifuse integrated structures arranged along the bit line extension direction, wherein the gate of the first antifuse MOS transistor in the first row of the antifuse integrated structures is connected to a first virtual programming wire, and the gate of the second antifuse MOS transistor in the last row of the antifuse integrated structures is connected to a second virtual programming wire.

12. The antifuse array structure according to claim 11, wherein: The gate of the first switch tube in the anti-fuse integrated structure in the first row is connected to the first virtual word line, and the gate of the second switch tube in the anti-fuse integrated structure in the last row is connected to the second virtual word line; wherein, the first virtual programming wire and the second virtual programming wire are located at the outermost side of the anti-fuse matrix, and the first virtual word line and the second virtual word line are located at the second outer side of the anti-fuse matrix.

13. A memory comprising a memory array, characterized in that: The storage array adopts the antifuse array structure according to any one of claims 1 to 12.

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