Wafer test structure and preparation method thereof

Abstract

The present disclosure provides a wafer test structure and a method for preparing the same, relating to the field of semiconductor technology. The test structure includes at least one test unit; each test unit is disposed on a dicing path of the wafer, and each test unit includes a first active area and a second active area connected to each other, a first conductive plug disposed on the first active area, and a second conductive plug disposed on the second active area; and a contact structure is disposed on one of the first active area and the second active area. In the present disclosure, the contact structure in the test unit is identical to the bitline contact structure in the chip region of the wafer. By measuring the resistance value of the contact structure in the test unit, this resistance value can be used as the resistance value of the bitline contact structure in the chip region of the wafer, thereby ensuring the accuracy of the resistance value of the bitline contact structure in the chip region.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a wafer test structure and a preparation method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or apparatuses. DRAM is usually composed of multiple memory cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the dynamic random access memory, and the voltage on the word line controls the opening and closing of the transistor; one end of the transistor is electrically connected to the bit line (BL), and the other end of the transistor is electrically connected to the capacitor, and data information is stored or output through the bit line. Among them, one end of the transistor is connected to the bit line through a bit line contact structure (BLC). The resistance of the bit line contact structure is the main factor affecting the timeliness of data information transmission. Therefore, a test structure is needed to test the resistance of the bit line contact structure.

[0003] The resistance of the bit line contact structure measured in the related art has low accuracy and cannot truly represent the resistance of the bit line contact structure in the corresponding memory cell structure. Summary of the Invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a wafer test structure and a method for preparing the same, which can solve the technical problem in the related art that the resistance value of the bit line contact structure cannot be accurately measured.

[0005] The embodiments of the present disclosure provide the following technical solutions:

[0006] A first aspect of an embodiment of the present disclosure provides a wafer test structure, comprising: at least one test unit; the test unit is disposed on a dicing street of the wafer;

[0007] Each of the test units includes a first active area and a second active area connected to each other, a first conductive plug is provided on the first active area, a second conductive plug is provided on the second active area, and one of the first active area and the second active area is provided with a contact structure, and the contact structure is the same as the bit line contact structure of the chip area of ​​the wafer.

[0008] In some embodiments, the test structure further includes a voltage test device and a current input device;

[0009] One end of the voltage testing device is connected to one of the first conductive plug and the second conductive plug, and the other end of the voltage testing device is connected to the contact structure; one end of the current input device is connected to the other of the first conductive plug and the second conductive plug, and the other end of the current input device is connected to the contact structure.

[0010] In some embodiments, the test unit further includes a first wire, a second wire, and a third wire, wherein the first wire is electrically connected to the first conductive plug, the third wire is electrically connected to the second conductive plug, the second wire is electrically connected to the contact structure, and along the first direction, the second wire includes a first end and a second end arranged opposite to each other.

[0011] In some embodiments, the contact structure is disposed in the first active region and between the first conductive plug and the second conductive plug;

[0012] One end of the voltage testing device is connected to the first wire, and the other end of the voltage testing device is connected to the first end of the second wire;

[0013] One end of the current input device is connected to the third wire, and the other end of the current input device is connected to the second end of the second wire.

[0014] In some embodiments, the contact structure is disposed in the second active region and between the first conductive plug and the second conductive plug;

[0015] One end of the voltage testing device is connected to the third wire, and the other end of the voltage testing device is connected to the first end of the second wire;

[0016] One end of the current input device is connected to the first wire, and the other end of the current input device is connected to the second end of the second wire.

[0017] In some embodiments, the first conductive plug and the second conductive plug each include a capacitive contact structure.

[0018] In some embodiments, the second conductive line includes a bit line, and the bit line extends along a first direction, wherein the first direction has a preset angle with an extension direction of the first active region.

[0019] In some embodiments, the first conductive line and the third conductive line include metal wires.

[0020] In some embodiments, the first conductive plug is disposed at an end of the first active region away from the second active region; and the second conductive plug is disposed at an end of the second active region away from the first active region.

[0021] A second aspect of the present disclosure provides a method for preparing a test structure of a wafer, comprising the following steps:

[0022] Providing a wafer, the wafer comprising a plurality of chip regions and dicing streets located between adjacent chip regions;

[0023] forming at least one test unit in the cutting street, each of the test units comprising a first active region and a second active region connected to each other;

[0024] A contact structure is formed in both the first active area and the second active area, wherein the contact structure is the same as a bit line contact structure in the chip area of ​​the wafer;

[0025] A first conductive plug is formed on the first active region, and a second conductive plug is formed on the second active region.

[0026] In some embodiments, the step of forming at least one test unit in the dicing street includes:

[0027] forming a first mask layer on the cutting street;

[0028] Patterning the first mask layer to form a first mask pattern in the first mask layer, wherein the first mask pattern includes a plurality of columns of mask stripe groups, the plurality of columns of mask stripe groups being sequentially arranged along a third direction, each column of the mask stripe groups including a plurality of first mask stripes spaced apart along the first direction, wherein each of the first mask stripes extends along a second direction, the first direction and the third direction being perpendicular to each other, and the second direction intersecting the first direction;

[0029] A portion of the substrate not blocked by the first mask strips is removed to form a plurality of active area groups within the substrate, each of the active area groups including a plurality of active areas spaced apart along a first direction, each of the active areas including a first active area and a second active area connected to each other, and a region of the substrate where the active area group is removed forms a groove.

[0030] In some embodiments, the step of forming at least one test unit in the dicing street includes:

[0031] forming a second mask layer on the cutting street;

[0032] Patterning the second mask layer to form a second mask pattern in the second mask layer, wherein the second mask pattern includes a plurality of second mask strips and first openings separating the plurality of second mask strips, wherein the second mask strips extend along a second direction and the plurality of second mask strips are spaced apart in a direction perpendicular to the second direction;

[0033] removing a portion of each second mask strip to form a plurality of second openings in each second mask strip, wherein the second openings are spaced apart along the second direction;

[0034] A portion of the thickness of the substrate exposed in the first opening and the second opening is removed to form a plurality of active area groups in the substrate, each of the active area groups including a plurality of active areas spaced apart along a first direction, wherein each of the active areas includes a first active area and a second active area connected to each other, and the area of ​​the substrate where the active area group is removed constitutes a groove.

[0035] In some embodiments, after the step of removing a portion of the thickness of the substrate to form a plurality of active area groups in the substrate, the method further includes:

[0036] An insulating material is deposited in the groove to form a shallow trench isolation structure.

[0037] In some embodiments, after the step of forming contact structures on both the first active area and the second active area in the test unit, the preparation method includes:

[0038] A second conductive line is formed, wherein the second conductive line is connected to the contact structure of the second active region.

[0039] In some embodiments, after the step of forming a first conductive plug in the first active area of ​​the test unit, the preparation method further includes:

[0040] A first conductive line and a third conductive line are formed, wherein the first conductive line is connected to the first conductive plug, and the third conductive line is connected to the second conductive plug.

[0041] In the test structure of the wafer and the preparation method thereof provided in the embodiments of the present disclosure, a test unit is formed in the cutting path of the wafer, and the contact structure in the test unit is formed together with the bit line contact structure in the chip area of ​​the wafer. In this way, the resistance value of the contact structure in the test unit can be measured, and the resistance value can be used as the resistance value of the bit line contact structure in the chip area of ​​the wafer to ensure the accuracy of the resistance value of the bit line contact structure in the chip area of ​​the wafer, thereby providing a numerical reference for the design of the semiconductor structure.

[0042] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the wafer test structure and preparation method thereof provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 A schematic diagram of a test structure provided in the related art;

[0045] Figure 2 A schematic diagram of a wafer provided in accordance with an embodiment of the present disclosure;

[0046] Figure 3 A schematic diagram of a wafer test structure provided by an embodiment of the present disclosure;

[0047] Figure 4 A flow chart of a method for preparing a test structure of a wafer provided in an embodiment of the present disclosure;

[0048] Figure 5 A schematic diagram of forming a first mask layer in the method for preparing a test structure of a wafer provided by an embodiment of the present disclosure;

[0049] Figure 6 A schematic diagram of forming an active area group in a method for preparing a test structure of a wafer provided by an embodiment of the present disclosure;

[0050] Figure 7 A schematic diagram of forming a second mask layer in the method for preparing a test structure of a wafer provided by an embodiment of the present disclosure;

[0051] Figure 8 Schematic diagram of forming a second opening in the method for preparing a test structure of a wafer provided in an embodiment of the present disclosure

[0052] Figure 9 A schematic diagram of forming a first dielectric layer and a first through hole in a method for preparing a test structure provided by an embodiment of the present disclosure;

[0053] Figure 10 A schematic diagram of forming a contact structure in a method for preparing a test structure provided in an embodiment of the present disclosure;

[0054] Figure 11 A schematic diagram of forming a second dielectric layer and a second through hole in the method for preparing a test structure provided by an embodiment of the present disclosure;

[0055] Figure 12 A schematic diagram of forming a second conductive line in a method for preparing a test structure provided by an embodiment of the present disclosure;

[0056] Figure 13A schematic diagram of forming a third through hole, a fourth through hole, a fifth through hole, and a sixth through hole in a method for preparing a test structure provided in an embodiment of the present disclosure;

[0057] Figure 14 A schematic diagram of forming a first conductive plug and a second conductive plug in a method for preparing a test structure provided by an embodiment of the present disclosure;

[0058] Figure 15 A top view of a test unit provided in an embodiment of the present disclosure;

[0059] Figure 16 A schematic diagram of forming a first conductive line and a second conductive line in a method for preparing a test structure provided in an embodiment of the present disclosure.

[0060] Reference numerals:

[0061] 100: Wafer; 110: Chip area; 120: Cutting road; 130: Substrate; 140: Isolation structure; 200: Test unit; 210: First active area; 211: First conductive plug; 212: Contact structure; 220: Second active area; 221: Second conductive plug; 230: First conductive wire; 240: Second conductive wire; 250: Third conductive wire; 300: Voltage test device; 400: Current input device; 500: Active area group; 60 0: First mask layer; 610: Mask stripe group; 611: First mask stripe; 700: First dielectric layer; 710: First through-hole; 800: Second dielectric layer; 810: Second through-hole; 820: Third through-hole; 830: Fourth through-hole; 840: Fifth through-hole; 850: Sixth through-hole; 860: First filling region; 870: Second filling region; 900: Second mask layer; 910: Second mask stripe; 920: First opening; 930: Second opening;

[0062] 10: Conductive structure; 20: Connecting wires. DETAILED DESCRIPTION

[0063] In the related art, in order to test the resistance of the bit line contact structure in the chip area of ​​the wafer, a substrate is usually provided first, and a plurality of through holes are formed in the substrate by patterning the substrate. Then, a conductive material for preparing the bit line contact structure is deposited in the through holes by a deposition process to form a conductive structure 10. Figure 1As shown, connecting wires 20 are then formed within the substrate to connect the various conductive structures 10, connecting the conductive structures 10 in series. The total resistance of all conductive structures 10 is then measured and divided by the number of conductive structures 10 to ultimately obtain the resistance of a single conductive structure 10. This resistance is then used to characterize the resistance of the bitline contact structures within the chip region of the wafer. However, due to process influences during the fabrication of the bitline contact structures, the shape or structure of each bitline contact structure may differ from the ideal state. Therefore, the conductive structure cannot fully simulate the shape and structure of the bitline contact structure, resulting in a discrepancy between the resistance of the bitline contact structure obtained in the above manner and the actual resistance of the bitline contact structure.

[0064] After repeated thinking and discussion, the inventors of the present disclosure discovered that if a test unit is formed directly on the cutting path of the wafer, the contact structure on the test unit can be prepared together with the bit line contact structure in the chip area of ​​the wafer, so that the resistance value of the bit line contact structure in the chip area of ​​the wafer can be accurately measured.

[0065] In view of this, in the embodiment of the present disclosure, a test unit is formed in the cutting path of the wafer, and the contact structure in the test unit is formed together with the bit line contact structure in the chip area of ​​the wafer. In this way, the resistance value of the contact structure in the test unit can be measured, and the resistance value can be used as the resistance value of the bit line contact structure in the chip area of ​​the wafer to ensure the accuracy of the resistance value of the bit line contact structure in the chip area of ​​the wafer, thereby providing a numerical reference for the design of the semiconductor structure.

[0066] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0067] When preparing a chip, multiple chip areas can be formed on the wafer first, and then the multiple chip areas can be separated by a cutting tool to form multiple chip monomers. Figure 2 The wafer 100 may include a plurality of chip regions 110 and cutting lanes 120 for separating the chip regions 110 , wherein the plurality of chip regions 110 may be arranged in an array, and several of the plurality of cutting lanes 120 extend along a row direction, and several of the cutting lanes 120 extend along a column direction.

[0068] like Figure 3As shown, the test structure of the wafer provided by the embodiment of the present disclosure includes at least one test unit 200, wherein the at least one test unit 200 is arranged on the cutting street 120 of the wafer.

[0069] like Figure 3 As shown, the test unit 200 includes a first active area 210 and a second active area 220 connected to each other, wherein the first active area 210 and the second active area 220 extend in the same direction, both extending along the second direction, which can be Figure 3 Center Y direction.

[0070] A first conductive plug 211 is provided on the first active area 210 , and a second conductive plug 221 is provided on the second active area 220 . The first conductive plug 211 and the second conductive plug 221 may be capacitor contact structures formed together with the capacitor contact structure in the chip area of ​​the wafer.

[0071] A contact structure 212 is provided in one of the first active area 210 and the second active area 220, that is, the contact structure 212 can be provided in the first active area 210 or in the second active area 220, wherein the contact structure 212 is the same as the bit line contact structure in the chip area of ​​the wafer, that is, the contact structure 212 and the bit line contact structure in the chip area of ​​the wafer are prepared under the same process.

[0072] It should be noted that the first active area 210 , the second active area 220 , the first conductive plug 211 , the contact structure 212 and the second conductive plug 221 are all formed on the dicing street 120 of the wafer.

[0073] In this embodiment, since the contact structure on the test unit is prepared simultaneously with the bit line contact structure in the chip area of ​​the wafer in the same preparation process, the contact structure on the test unit can replicate the bit line contact structure in the chip area of ​​the wafer, and then the above-mentioned measurement structure can be used to accurately measure the resistance value of the bit line contact structure in the chip area of ​​the wafer, providing a numerical reference for the design of the semiconductor structure.

[0074] Furthermore, this embodiment connects the first active area and the second active area together to form a larger active area. This facilitates the subsequent connection of voltage measurement equipment and current input equipment to the test unit, thereby improving the convenience of testing the resistance of the contact structure. Furthermore, by measuring the resistance of a single contact structure, this embodiment avoids the errors caused by measuring multiple conductive structures in related technologies, allowing accurate measurement of the resistance value of the bitline contact structure in the chip area of ​​the wafer.

[0075] In some embodiments, continue to refer to Figure 3One end of the voltage testing device 300 is connected to one of the first conductive plug 211 and the second conductive plug 221 , and the other end of the voltage testing device 300 is connected to the contact structure 212 .

[0076] One end of the current input device 400 is connected to the other of the first conductive plug 211 and the second conductive plug 221 , and the other end of the current input device 400 is connected to the contact structure 212 .

[0077] For example, if one end of the voltage testing device 300 is connected to the first conductive plug 211 , correspondingly, one end of the current input device 400 is connected to the second conductive plug 221 .

[0078] The voltage testing device 300 may include a voltmeter, and the current input device 400 may include a current source. For example, the current source may be an AC power source or a DC power source.

[0079] In this embodiment, a constant current is provided to one of the active areas through a current input device. Since the second active area is connected to the first active area, the constant current is transmitted to the other active area, so that a constant current exists on the contact structure. The voltage value on the contact structure is measured using a voltage testing device, and the resistance value of the contact structure is calculated using the ratio between the voltage value and the constant current.

[0080] It should be noted that the voltage testing device 300 and the first conductive plug 211 may be directly connected or indirectly connected, or the voltage testing device 300 and the contact structure 212 may be directly connected or indirectly connected.

[0081] For example, continue to refer to Figure 3 The test unit 200 also includes a first wire 230, a second wire 240 and a third wire 250, the first wire 230 is electrically connected to the first conductive plug 211, the second wire 240 is electrically connected to the contact structure 212, and the third wire 250 is electrically connected to the second conductive plug 221, wherein the contact structure 212 can be connected to the middle area of ​​the second wire 240.

[0082] Along the first direction, i.e. along Figure 3 In the X direction, the second wire 240 has a first end 241 and a second end 242 that are oppositely arranged. Figure 3 Taking the illustrated orientation as an example, the first end 241 is the rear end of the second conductive wire 240 , and the second end 242 is the front end of the second conductive wire 240 .

[0083] When the contact structure 212 is arranged in the first active area 210 and is located between the first conductive plug 211 and the second conductive plug 221, one end of the voltage testing device 300 is connected to the first wire 230, and the other end of the voltage testing device 300 is connected to the first end 241 of the second wire 240, wherein the connection end of the voltage testing device 300 and the first wire 230 is not the same end as the connection end of the first wire 230 and the first conductive plug 211. Exemplarily, the rear end of the first wire 230 is connected to the voltage testing device 300, and the front end of the first wire 230 is connected to the first conductive plug 211.

[0084] One end of the current input device 400 is connected to the third wire 250, and the other end of the current input device 400 is connected to the second end 242 of the second wire 240, wherein the connection end between the current input device 400 and the third wire 250 is not the same as the connection end between the third wire 250 and the second conductive plug 221. Exemplarily, the rear end of the third wire 250 is connected to the current input device 400, and the front end of the second wire 240 is connected to the second conductive plug 221.

[0085] When the contact structure 212 is arranged in the second active area 220 and is located between the first conductive plug 211 and the second conductive plug 221, one end of the voltage testing device 300 is connected to the third wire 250, and the other end of the voltage testing device 300 is connected to the first end 241 of the second wire 240; wherein, the connection end of the voltage testing device 300 and the third wire 250 is not the same as the connection end of the third wire 250 and the second conductive plug 221. For example, the rear end of the third wire 250 is connected to the voltage testing device 300, and the front end of the third wire 250 is connected to the second conductive plug 221.

[0086] One end of the current input device 400 is connected to the first wire 230, and the other end of the current input device 400 is connected to the first end 241 of the second wire 240, wherein the connection end of the current input device 400 and the first wire 230 is not the same as the connection end of the first wire 230 and the first conductive plug 211. Exemplarily, the rear end of the first wire 230 is connected to the current input device 400, and the front end of the first wire 230 is connected to the first conductive plug 211.

[0087] In this embodiment, by connecting the first wire, the second wire and the third wire, the voltage difference measured by the voltage testing equipment can be the voltage on the contact structure, avoiding the interference of the parasitic resistance of the active area and the conductive plug, and improving the test accuracy.

[0088] In some embodiments, the second conductive line 240 may include a bit line extending along a first direction. The first direction and the extending directions of the first active area 210 and the second active area 220 have a preset angle, wherein the preset angle may be between 0-90°.

[0089] The first conductive line 230 and the third conductive line 250 may include metal wires. For example, the metal wires may be made of copper, aluminum, or tungsten.

[0090] In this embodiment, the first and third wires can be completed together with the preparation of metal wires in the chip area of ​​the wafer, and the second wire can be completed together with the preparation of bit lines in the chip area of ​​the wafer, so as to simplify the preparation process of the test structure and thereby reduce the production cost of the test structure.

[0091] Continue to refer Figure 3 The first conductive plug 211 may be disposed at an end of the first active region 210 away from the second active region 220 . For example, the first conductive plug 211 may be disposed on the left side of the contact structure 212 , that is, in the left half of the first active region 210 .

[0092] The second conductive plug 221 is disposed at an end of the second active region 220 away from the first active region 210 . For example, the second conductive plug 221 is disposed on the right side of the contact structure 212 , that is, in the right half of the second active region 220 .

[0093] This embodiment designs the positions of the first conductive plug, the second conductive plug, and the contact structure so that the voltage difference measured by the voltage testing equipment is the voltage on the contact structure, avoiding interference from the parasitic resistance of the active area and the conductive plug, and improving test accuracy.

[0094] like Figure 4 As shown, the method for preparing a wafer test structure provided by an embodiment of the present disclosure includes the following steps:

[0095] Step S100: providing a wafer, the wafer including a plurality of chip areas and dicing lanes between adjacent chip areas, the structure of which can be further referred to Figure 2 .

[0096] Step S200: forming at least one test unit in a cutting street, wherein each test unit has a first active region and a second active region connected to each other.

[0097] It should be noted that both the chip region 110 and the dicing street 120 should have a substrate, and the first active region 210 and the second active region 220 are both formed on the substrate within the dicing street.

[0098] As a feasible implementation of the test unit, Figure 5As shown, a first mask layer 600 is formed on the substrate of the cutting street 120 , wherein the first mask layer 600 may include a photoresist layer or a multi-layer sub-mask layer, which is not specifically limited in this embodiment.

[0099] After the first mask layer 600 is formed, the first mask layer 600 may be patterned to form a first mask pattern in the first mask layer 600, wherein the first mask pattern includes a plurality of columns of mask stripe groups 610, such as Figure 5 As shown, a column of mask stripe groups 610 is located Figure 5 In the box in , multiple columns of mask strip groups 610 can be arranged sequentially along the third direction, that is, multiple columns of mask strip groups 610 are arranged sequentially along the row direction W.

[0100] Each column of mask strip groups 610 includes a plurality of first mask strips 611 spaced apart along a first direction. Figure 5 Each column of mask strip groups 610 includes a plurality of first mask strips 611 spaced apart from each other. Figure 5 The X direction of the arrangement, wherein each first mask strip 611 extends along the second direction, the second direction is as follows Figure 5 The second direction intersects the first direction, and the third direction and the first direction are perpendicular to each other.

[0101] Afterwards, if Figure 6 As shown, an etching solution or etching gas is used to remove the thickness of the substrate 130 that is not blocked by the first mask strip 611, so as to form a plurality of mutually isolated active area groups 500 in the substrate 130. The plurality of active area groups 500 are sequentially arranged along the row direction W, wherein one active area group 500 is arranged as shown in FIG. Figure 6 in the box.

[0102] Each active area group 500 includes a plurality of active areas spaced apart along the first direction, that is, each active area group 500 includes a plurality of active areas spaced apart along the first direction. Figure 6 The active regions 210 and 220 are spaced apart in the X direction, wherein each active region includes a first active region 210 and a second active region 220 connected to each other, and each active region constitutes a test unit 200 .

[0103] As another feasible implementation of the test unit, Figure 7 As shown, a second mask layer 900 is formed on the cutting street, wherein the second mask layer 900 may include a photoresist layer or a multi-layer sub-mask layer, which is not specifically limited in this embodiment.

[0104] After the second mask layer 900 is formed, the second mask layer 900 is patterned to form a second mask pattern in the second mask layer 900. The second mask pattern includes a plurality of second mask strips 910 and first openings 920 separating the plurality of second mask strips 910. For example, second openings are formed between adjacent second mask strips 910.

[0105] The second mask strips 910 extend along the second direction, and a plurality of second mask strips 910 are spaced apart in a direction perpendicular to the second direction, wherein the second direction intersects the row direction, wherein the second direction is Figure 7 In the Y direction, the row direction is Figure 7 Center W direction.

[0106] Afterwards, a plurality of mask blocks arranged at intervals may be formed on the second mask strip, with portions of the second mask strip exposed between adjacent mask blocks. Then, an etching solution or etching gas is used to remove portions of each second mask strip 910, that is, to remove the areas exposed between adjacent mask blocks, so as to form a plurality of second openings 930 in each second mask strip 910. The second openings 930 are arranged at intervals along the second direction, and their structure is as follows: Figure 8 shown.

[0107] A portion of the thickness of the substrate 130 exposed in the first opening 920 and the second opening 930 is removed to form a plurality of active area groups 500 in the substrate 130. Each active area group includes a plurality of active areas spaced apart along the first direction. Each active area includes a first active area 210 and a second active area 220 connected to each other. Each active area constitutes a test unit 200. The first active area 210 and the second active area 220 extend in the second direction. The structure of the test unit 200 can be further described with reference to FIG. Figure 6 .

[0108] After a portion of the thickness of the substrate 130 is removed, a groove will be formed in the substrate 130. That is, the area in the substrate 130 where the active area group is removed is a groove. Therefore, after the test unit is formed, it is necessary to use a deposition process to deposit an insulating material in the groove to form a shallow trench isolation structure 140. The shallow trench isolation structure 140 is used to realize the insulation setting between adjacent test units 200, wherein the insulating material may include silicon oxide.

[0109] Step S300: forming contact structures in both the first active region and the second active region.

[0110] For example, Figure 9As shown, a first dielectric layer 700 may be formed on the first active area 210 and the second active area 220 by a deposition process, and then the first dielectric layer 700 may be patterned to form two first through holes 710 spaced apart in the first dielectric layer 700, wherein a projection of one of the first through holes 710 on the substrate 130 is located in the first active area 210, and a projection of the other first through hole 710 on the substrate 130 is located in the second active area 220.

[0111] Afterwards, if Figure 10 As shown, a contact structure 212 is formed in the first through hole 710 using a deposition process, so that the contact structure 212 located in the first active area is electrically connected to the first active area 210, and the contact structure 212 located in the second active area is electrically connected to the second active area, wherein the contact structure 212 can be a bit line contact structure.

[0112] like Figure 11 and Figure 12 As shown, to form the contact structure 212, a second dielectric layer 800 can be formed on the first dielectric layer 700, and then the second dielectric layer 800 is patterned to form two second through holes 810 spaced apart in the second dielectric layer 800. Each second through hole 810 exposes a contact structure 212. Thereafter, a conductive material is deposited into the second through hole 810 through a deposition process to form a second conductive wire 240. The second conductive wire 240 is connected to the contact structure 212.

[0113] like Figure 13 As shown, after the second conductive line 240 is formed, a third through hole 820, a fourth through hole 830, a fifth through hole 840 and a sixth through hole 850 are formed in the second dielectric layer 800. The bottom of the third through hole 820 is the top surface of the first active area 210, and the third through hole 820 is located on the side of the contact structure 212 in the first active area 210 away from the second active area 220, so as to Figure 11 Taking the shown orientation as an example, the third through hole 820 is located on the left side of the contact structure 212 in the first active area 210; the bottom of the fourth through hole 830 is the top surface of the first active area 210, and the fourth through hole 830 is located on the right side of the contact structure 212 in the first active area 210, the bottom of the fifth through hole 840 is the top surface of the second active area 220, and the fifth through hole 840 is located on the left side of the contact structure 212 in the second active area 220, the bottom of the sixth through hole 850 is the top surface of the second active area 220, and the sixth through hole 850 is located on the side of the contact structure 212 in the second active area 220 away from the first active area 210, that is, the sixth through hole 850 is located on the right side of the contact structure 212 in the second active area 220.

[0114] like Figure 14As shown, a conductive material is deposited into the third through hole 820, the fourth through hole 830, the fifth through hole 840 and the sixth through hole 850 through a deposition process. The conductive material fills the third through hole 820, the fourth through hole 830, the fifth through hole 840 and the sixth through hole 850. The conductive material is etched back. The conductive material in the third through hole 820 constitutes the first conductive plug 211, and the conductive material in the sixth through hole 850 constitutes the second conductive plug 221. The top surface of the first conductive plug 211 and the top surface of the second conductive plug 221 are both flush with the top surface of the first dielectric layer 700. The top view of the structure formed is shown in FIG. Figure 15 shown.

[0115] It should be noted that when depositing the conductive material, the conductive material will also be deposited in the fourth through hole 830 and the fifth through hole 840 to form a conductive column. The conductive column and the first conductive plug and the second conductive plug are equivalent to the capacitor contact structure in the chip area.

[0116] like Figure 16 As shown, after the conductive plug is formed, the top surface of the first conductive plug 211 and the second dielectric layer 800 form a first filling area 860, and the top surface of the second conductive plug 221 and the second dielectric layer 800 form a second filling area 870. Then, a deposition process is used to form the first conductive line 230 in the first filling area 860 and the third conductive line 250 in the second filling area 870.

[0117] Finally, an insulating material is deposited in the area enclosed by the conductive pillar and the second dielectric layer 800 , and the insulating material and the second dielectric layer 800 form a whole.

[0118] When the resistance of the contact structure 212 needs to be tested, a voltage test device and a current input device may be used for measurement, for example, Figure 3 As shown, when it is necessary to test the resistance of the contact structure 212 located in the first active area 210, one end of the voltage testing device 300 is connected to the first conductive plug 211, and the other end of the voltage testing device 300 is connected to the contact structure 212 located in the first active area 210, one end of the current input device 400 is connected to the second conductive plug 221, and the other end of the current input device 400 is connected to the contact structure 212 in the first active area 210.

[0119] In this embodiment, a constant current is provided to the second active area through a current input device. Since the second active area is connected to the first active area, the constant current will be transmitted to the first active area, so that a constant current exists in the contact structure located in the first active area. In this embodiment, a voltage testing device is used to measure the voltage value on the contact structure, and the resistance value of the contact structure is calculated using the ratio between the voltage value and the constant current.

[0120] In addition, when it is necessary to test the resistance of the contact structure 212 on the second active area 220, a voltage testing device 300 can be set between the second conductive plug 221 and the contact structure 212 located in the second active area 220. For example, one end of the voltage testing device 300 is connected to the third wire 250, and the other end of the voltage testing device 300 is connected to the second wire 240 connected to the contact structure 212 located in the second active area 220.

[0121] A current input device 400 is arranged between the first conductive plug 211 and the contact structure 212 in the second active area 220. For example, one end of the current input device 400 is connected to the first wire 230, and the other end of the current input device 400 is connected to the second wire 240 connected to the contact structure 212 located in the second active area 220.

[0122] A constant current is provided to the first active area through a current input device. Since the first active area is connected to the second active area, the constant current will be transmitted to the second active area, so that a constant current exists in the contact structure located in the second active area. This embodiment uses a voltage testing device to measure the voltage value on the contact structure, and uses the ratio between the voltage value and the constant current to calculate the resistance value of the contact structure.

[0123] In this embodiment, since the contact structure on the test unit is prepared simultaneously with the bit line contact structure in the chip area of ​​the wafer in the same preparation process, the contact structure on the test unit can replicate the bit line contact structure in the chip area of ​​the wafer, and then the above-mentioned measurement method can be used to accurately measure the resistance value of the bit line contact structure in the chip area of ​​the wafer, providing theoretical support for the design of semiconductor structures.

[0124] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0125] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0126] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A wafer test structure, characterized in that: comprising at least one testing unit, wherein the testing unit is arranged on a dicing street of the wafer; Each of the test units includes a first active area and a second active area connected to each other, a first conductive plug is provided on the first active area, a second conductive plug is provided on the second active area, and a contact structure is provided on one of the first active area and the second active area, and the contact structure is the same as the bit line contact structure of the chip area of ​​the wafer; The test structure also includes a voltage test device and a current input device; One end of the voltage testing device is connected to one of the first conductive plug and the second conductive plug, and the other end of the voltage testing device is connected to the contact structure; One end of the current input device is connected to the other of the first conductive plug and the second conductive plug, and the other end of the current input device is connected to the contact structure; The test unit further includes a first wire, a second wire, and a third wire, wherein the first wire is electrically connected to the first conductive plug, the third wire is electrically connected to the second conductive plug, and the second wire is electrically connected to the contact structure, and along the first direction, the second wire includes a first end and a second end oppositely disposed; The contact structure is provided in the first active area and is located between the first conductive plug and the second conductive plug; One end of the voltage testing device is connected to the first wire, and the other end of the voltage testing device is connected to the first end of the second wire; One end of the current input device is connected to the third wire, and the other end of the current input device is connected to the second end of the second wire.

2. The wafer test structure according to claim 1, wherein: The contact structure is disposed in the second active region and between the first conductive plug and the second conductive plug; One end of the voltage testing device is connected to the third wire, and the other end of the voltage testing device is connected to the first end of the second wire; One end of the current input device is connected to the first wire, and the other end of the current input device is connected to the second end of the second wire.

3. The wafer test structure according to any one of claims 1 to 2, characterized in that: The first conductive plug and the second conductive plug each include a capacitor contact structure.

4. The wafer test structure according to any one of claims 1 to 2, characterized in that: The second conductive line includes a bit line, and the bit line extends along the first direction. The first direction has a preset angle with an extension direction of the first active region and the second active region.

5. The wafer test structure according to claim 4, characterized in that: The first conductive line and the third conductive line include metal wires.

6. The wafer test structure according to any one of claims 1-2, characterized in that: The first conductive plug is disposed at an end of the first active region away from the second active region; The second conductive plug is disposed at an end of the second active region away from the first active region.

7. A method for preparing a test structure of a wafer, characterized in that: The steps include: Providing a wafer, the wafer comprising a plurality of chip regions and dicing streets located between adjacent chip regions; forming at least one test unit in the cutting street, each of the test units comprising a first active region and a second active region connected to each other; A contact structure is formed in both the first active area and the second active area, and the contact structure is the same as the bit line contact structure in the chip area; A first conductive plug is formed on the first active area, and a second conductive plug is formed on the second active area; The step of forming at least one test unit in the cutting street includes: forming a first mask layer on the cutting street; Patterning the first mask layer to form a first mask pattern in the first mask layer, wherein the first mask pattern includes a plurality of columns of mask stripe groups, the plurality of columns of mask stripe groups being sequentially arranged along a third direction, each column of the mask stripe groups including a plurality of first mask stripes spaced apart along the first direction, wherein each of the first mask stripes extends along a second direction, the first direction and the third direction being perpendicular to each other, and the second direction intersecting the first direction; A portion of the substrate not blocked by the first mask strips is removed to form a plurality of active area groups within the substrate, each of the active area groups including a plurality of active areas spaced apart along a first direction, each of the active areas including a first active area and a second active area connected to each other, and a region of the substrate where the active area group is removed forms a groove.

8. The method for preparing a wafer test structure according to claim 7, wherein: The step of forming at least one test unit in the cutting street includes: forming a second mask layer on the cutting street; Patterning the second mask layer to form a second mask pattern in the second mask layer, wherein the second mask pattern includes a plurality of second mask strips and first openings separating the plurality of second mask strips, wherein the second mask strips extend along a second direction and the plurality of second mask strips are spaced apart in a direction perpendicular to the second direction; removing a portion of each second mask strip to form a plurality of second openings in each second mask strip, wherein the second openings are spaced apart along the second direction; A portion of the thickness of the substrate exposed in the first opening and the second opening is removed to form a plurality of active area groups in the substrate, each of the active area groups including a plurality of active areas spaced apart along a first direction, wherein each of the active areas includes a first active area and a second active area connected to each other, and the area of ​​the substrate where the active area group is removed constitutes a groove.

9. The method for preparing a wafer test structure according to claim 7 or 8, characterized in that: After the step of removing a portion of the thickness of the substrate to form a plurality of active area groups in the substrate, the method further includes: An insulating material is deposited in the groove to form a shallow trench isolation structure.

10. The method for preparing a wafer test structure according to claim 9, wherein: After the step of forming contact structures on both the first active area and the second active area in the test unit, the preparation method includes: A second conductive line is formed, wherein the second conductive line is connected to the contact structure of the first active region.

11. The method for preparing a wafer test structure according to claim 9, characterized in that: After the step of forming contact structures on both the first active area and the second active area in the test unit, the preparation method includes: A second conductive line is formed, wherein the second conductive line is connected to the contact structure of the second active region.

12. The method for preparing a wafer test structure according to claim 9, wherein: After the step of forming a first conductive plug in the first active area of ​​the test unit, the preparation method further includes: A first conductive line and a third conductive line are formed, wherein the first conductive line is connected to the first conductive plug, and the third conductive line is connected to the second conductive plug.

13. A method for preparing a test structure of a wafer, characterized in that: The steps include: Providing a wafer, the wafer comprising a plurality of chip regions and dicing streets located between adjacent chip regions; forming at least one test unit in the cutting street, each of the test units comprising a first active region and a second active region connected to each other; A contact structure is formed in both the first active area and the second active area, and the contact structure is the same as the bit line contact structure in the chip area; A first conductive plug is formed on the first active area, and a second conductive plug is formed on the second active area; The step of forming at least one test unit in the cutting street includes: forming a second mask layer on the cutting street; Patterning the second mask layer to form a second mask pattern in the second mask layer, wherein the second mask pattern includes a plurality of second mask strips and first openings separating the plurality of second mask strips, wherein the second mask strips extend along a second direction and the plurality of second mask strips are spaced apart in a direction perpendicular to the second direction; removing a portion of each second mask strip to form a plurality of second openings in each second mask strip, wherein the second openings are spaced apart along the second direction; A portion of the thickness of the substrate exposed in the first opening and the second opening is removed to form a plurality of active area groups in the substrate, each of the active area groups including a plurality of active areas spaced apart along a first direction, wherein each of the active areas includes a first active area and a second active area connected to each other, and the area of ​​the substrate where the active area group is removed constitutes a groove.

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