High-voltage-resistant switch device integrated with low-voltage device, preparation method thereof, and chip

Abstract

This application relates to a high-voltage resistant switching device integrating low-voltage components, its fabrication method, and a chip. The high-voltage resistant switching device integrating low-voltage components includes an N-type silicon carbide substrate, a drift layer, a buffer layer, a channel layer, a barrier layer, a high-voltage drain, and an intermediate metal layer, a high-voltage source, and a high-voltage gate disposed within the high-voltage device region. By disposing the high-voltage drain on the back side of the N-type silicon carbide substrate, a conductive path can be formed consisting of the high-voltage drain, the N-type silicon carbide substrate, a second drift region, an intermediate metal layer, a two-dimensional electron gas, and a high-voltage source. By incorporating the N-type silicon carbide substrate and the second drift region as part of the conductive path, the characteristics of silicon carbide are utilized to improve the high-voltage withstand performance of the formed semiconductor device. A shallow trench isolation layer can cut off the two-dimensional electron gas, making each device region independent. The first drift region can prevent the high voltage in the high-voltage device region from affecting the operation of the HEMT device in the low-voltage device region.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a high-voltage-resistant switching device integrated with a low-voltage device and a preparation method and a chip thereof. BACKGROUND

[0002] At present, gallium nitride (GaN) is a new third-generation semiconductor material, has many excellent characteristics, and is a mainstream of future development of power semiconductors.

[0003] Gallium nitride currently commonly used substrate materials (SiC / Si / GaN / sapphire, etc.) each have their advantages and disadvantages. Silicon carbide, although expensive, can greatly reduce the lattice dislocation of gallium nitride, and improve yield and device performance.

[0004] Although the existing gallium nitride high electron mobility transistor (HEMT) device has a fast switching speed, the gallium nitride HEMT device has poor high-voltage resistance, and cannot be applied to a high-voltage environment. In particular, when the gallium nitride HEMT device is applied with high voltage, it is easy to be broken down. SUMMARY

[0005] The application aims to provide a high-voltage-resistant switching device integrated with a low-voltage device and a preparation method and a chip thereof, and aims to solve the problem of easy breakdown of the traditional gallium nitride HEMT device under high voltage.

[0006] A first aspect of the application provides a high-voltage-resistant switching device integrated with a low-voltage device, comprising: an N-type silicon carbide substrate; a drift layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked on the front surface of the N-type silicon carbide substrate; wherein the drift layer comprises a first drift region and a second drift region arranged side by side, and a plurality of floating island structures different in doping type from the drift layer are arranged in the first drift region; a first shallow trench isolation layer is arranged in the barrier layer and the channel layer, and extends into the buffer layer, so as to divide the barrier layer and the channel layer into a high-voltage device region and a low-voltage device region; a high-voltage drain electrode is arranged on the back surface of the N-type silicon carbide substrate; an intermediate metal layer is arranged on the second drift region and contacts the first side of the buffer layer, the channel layer and the barrier layer of the high-voltage device region; a high-voltage source electrode is arranged on the second side of the barrier layer in the high-voltage device region and extends into the channel layer; a high-voltage gate electrode is arranged on the barrier layer between the intermediate metal layer and the high-voltage source electrode; a low-voltage source electrode, a low-voltage drain electrode and a low-voltage gate electrode are all arranged in the low-voltage device region to form a corresponding low-voltage HEMT device.

[0007] In one embodiment, the drift layer is N-type silicon carbide, the floating island structure is P-type silicon carbide; the barrier layer is aluminum gallium nitride, and the channel layer is gallium nitride.

[0008] In one embodiment, the floating island structures are arranged in parallel with the N-type silicon carbide substrate, and the distance between adjacent floating island structures is equal.

[0009] In one embodiment, the width of each floating island structure is not less than the width of the low-voltage device region.

[0010] In one embodiment, the ion doping concentration of each floating island structure is in a positive proportional relationship with the distance from the N-type silicon carbide substrate.

[0011] In one embodiment, a second shallow trench isolation layer is further included, which is arranged in the barrier layer and the channel layer of the low-voltage device region and extends to the buffer layer to divide the low-voltage device region into a plurality of low-voltage device sub-regions, and each low-voltage device sub-region is located above the first drift region; the low-voltage source, the low-voltage drain, and the low-voltage gate are arranged in each low-voltage device.

[0012] In one embodiment, the low-voltage source and the low-voltage drain are arranged on the channel layer and in contact with the barrier layer, and the low-voltage gate is arranged on the barrier layer between the low-voltage source and the low-voltage drain.

[0013] In one embodiment, a first P-type cap layer is further included, which is arranged between the barrier layer and the high-voltage gate.

[0014] The second aspect of the embodiment of the present application provides a preparation method of a high-voltage-resistant switch device integrated with low-voltage devices, comprising: depositing a drift layer on the front surface of an N-type silicon carbide substrate; wherein the drift layer comprises a first drift region and a second drift region arranged side by side, and a plurality of floating island structures with a doping type different from that of the drift layer are arranged in the first drift region; sequentially depositing a buffer layer, a channel layer, a barrier layer and a P-type cap layer on the front surface of the drift layer; etching the P-type cap layer to form a first P-type cap layer and a second P-type cap layer; etching the channel layer and the barrier layer to form a first trench and a second trench, and depositing an insulating material in the first trench and the second trench to form a first shallow trench isolation layer and a second shallow trench isolation layer; wherein the first shallow trench isolation layer extends to the buffer layer to divide the barrier layer and the channel layer into a high-voltage device region and a low-voltage device region; the second shallow trench isolation layer extends to the buffer layer and is located in the low-voltage device region to divide the low-voltage device region into a plurality of low-voltage device sub-regions; etching the channel layer and the barrier layer to form a plurality of low-voltage electrode trenches in the low-voltage device region, and to form a first high-voltage trench and a second high-voltage trench in the high-voltage device region; the first high-voltage trench is located on a first side of the buffer layer, the channel layer and the barrier layer and extends to the second drift region, and the second high-voltage trench is located on a second side of the barrier layer in the high-voltage device region and extends to the channel layer; depositing a metal material in the plurality of low-voltage electrode trenches to form a low-voltage source electrode and a low-voltage drain electrode, and depositing a metal material in the first high-voltage trench and the second high-voltage trench to form an intermediate metal layer and a high-voltage source electrode, respectively; forming a high-voltage gate on the barrier layer or the first P-type cap layer in the high-voltage device region, forming a low-voltage gate on the barrier layer or the second P-type cap layer in the low-voltage device region, and forming a high-voltage drain on the back surface of the N-type silicon carbide substrate.

[0015] The third aspect of the embodiment of the present application provides a chip comprising the high-voltage-resistant switch device integrated with low-voltage devices as described above, or the chip comprises the high-voltage-resistant switch device integrated with low-voltage devices prepared by the preparation method as described above.

[0016] Compared with the prior art, the embodiment of the present application has the beneficial effect that a two-dimensional electron gas (2DEG) can be formed between the channel layer and the barrier layer. By arranging the high-voltage drain on the back surface of the N-type silicon carbide substrate, a conductive path composed of the high-voltage drain, the N-type silicon carbide substrate, the second drift region, the intermediate metal layer, the two-dimensional electron gas and the high-voltage source electrode can be formed. By taking the N-type silicon carbide substrate and the second drift region as part of the conductive path, the high-voltage-resistant characteristic of the N-type silicon carbide substrate is utilized to improve the high-voltage-resistant performance of the semiconductor device formed.

[0017] The two-dimensional electron gas can be cut off by the shallow trench isolation layer, so that each device region is independent of each other. The high voltage in the high-voltage device region can be prevented from affecting the semiconductor switch formed in the low-voltage device region when passing through the second drift region through the first drift region. The low-voltage switch device is formed in each low-voltage device region, and the formed low-voltage switch device can be used to form a related low-voltage digital circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices is provided for the first embodiment of the present application.

[0019] Figure 2 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices is provided for the first embodiment of the present application. Figure 1

[0020] Figure 3 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices is provided for the first embodiment of the present application. Figure 2

[0021] Figure 4 A flowchart of a preparation method of a high-voltage-resistant switch device integrated with low-voltage devices is provided for the second embodiment of the present application.

[0022] Figure 5 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S100 is executed.

[0023] Figure 6 A structure diagram of a first epitaxial layer and a second epitaxial layer.

[0024] Figure 7 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S200 is executed.

[0025] Figure 8 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S300 is executed.

[0026] Figure 9 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S400 is executed.

[0027] Figure 10 A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S500 is executed.

[0028] Figure 11 Another structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S500 is executed.

[0029] Figure 12 ​​A structure diagram of a high-voltage-resistant switch device integrated with low-voltage devices after step S600 is executed;

[0030] Figure 13 A structure diagram of a chip provided by the third embodiment of the present application is provided.

[0031] The above description of drawings: 10, chip; 20, high-voltage-resistant switch device integrated with low-voltage devices; 100, N-type silicon carbide substrate; 200, drift layer; 210, first drift region; 211, floating island structure; 220, second drift region; 230, first epitaxial layer; 240, second epitaxial layer; 250, ion implantation region; 300, buffer layer; 400, channel layer; 500, barrier layer; 510, first shallow trench isolation layer; 520, high-voltage device region; 530, low-voltage device region; 531, low-voltage device sub-region; 540, second shallow trench isolation layer; 610, high-voltage drain; 620, intermediate metal layer; 630, high-voltage source; 631, high-voltage filling metal layer; 632, high-voltage lead metal layer; 640, high-voltage gate; 650, first high-voltage trench; 660, second high-voltage trench; 700, P-type cap layer; 710, first P-type cap layer; 720, second P-type cap layer; 810, low-voltage source; 811, source filling metal layer; 812, source lead metal layer; 820, low-voltage drain; 821, drain filling metal layer; 822, drain lead metal layer; 830, low-voltage gate; 840, low-voltage electrode trench. DETAILED DESCRIPTION

[0032] In order to make the technical problems, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0033] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0034] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be formed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] Figure 1 A schematic diagram of the high-voltage resistant switching device integrating low-voltage devices according to the first embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0037] A high-voltage resistant switching device integrating low-voltage devices includes: an N-type silicon carbide substrate 100, a drift layer 200, a buffer layer 300, a channel layer 400, a barrier layer 500, and a first shallow trench isolation layer 510.

[0038] like Figure 1 As shown, a drift layer 200, a buffer layer 300, a channel layer 400, and a barrier layer 500 are sequentially stacked on the front side of an N-type silicon carbide substrate 100. The drift layer 200 includes a first drift region 210 and a second drift region 220 arranged side-by-side between the N-type silicon carbide substrate 100 and the buffer layer 300. The first drift region 210 contains a plurality of floating island structures 211 parallel to the N-type silicon carbide substrate 100. The doping type of the floating island structures 211 is different from that of the drift layer 200. Specifically, the ions doped in the drift layer 200 can be N-type ions, while the ions doped in the floating island structures 211 can be P-type ions. A first shallow trench isolation layer 510 is disposed within the barrier layer 500 and the channel layer 400, extending into the buffer layer 300, to divide the barrier layer 500 and the channel layer 400 into a high-voltage device region 520 and a low-voltage device region 530; the material of the first shallow trench isolation layer 510 can be an insulating material. In one example, such as Figure 1 As shown, a first shallow trench isolation layer 510 divides a low-voltage device region 530 located on the second side of the first shallow trench isolation layer 510 and a high-voltage device region 520 located on the first side of the first shallow trench isolation layer 510. The second side is opposite to the first side; in one embodiment, the first side corresponds to the right side, and the second side corresponds to the left side.

[0039] The high-voltage switching device integrating low-voltage components also includes a high-voltage drain 610, an intermediate metal layer 620, a high-voltage source 630, a high-voltage gate 640, a low-voltage source 810, a low-voltage drain 820, and a low-voltage gate 830.

[0040] like Figure 1As shown, the high-voltage drain 610 is disposed on the back of the N-type silicon carbide substrate 100. The intermediate metal layer 620 is disposed on the second drift region 220 and contacts the first side of the buffer layer 300, the channel layer 400 and the barrier layer 500 in the high-voltage device region 520. The high-voltage source 630 is disposed on the second side of the barrier layer 500 in the high-voltage device region 520 and extends into the channel layer 400. The high-voltage gate 640 is disposed on the barrier layer 500 between the intermediate metal layer 620 and the high-voltage source 630. The low-voltage source 810, the low-voltage drain 820 and the low-voltage gate 830 are all disposed in the low-voltage device region 530 to form corresponding low-voltage HEMT devices. The specific structures and positions of the low-voltage source 810, the low-voltage drain 820 and the low-voltage gate 830 can be configured according to actual needs.

[0041] It should be noted that a conductive two-dimensional electron gas can be formed between the channel layer 400 and the barrier layer 500. By disposing the high-voltage drain 610 on the back of the N-type silicon carbide substrate 100, a conductive path composed of the high-voltage drain 610, the N-type silicon carbide substrate 100, the second drift region 220, the intermediate metal layer 620, the two-dimensional electron gas and the high-voltage source 630 can be formed. By using the N-type silicon carbide substrate 100 as part of the conductive path, the high-voltage resistance of the semiconductor device formed is improved by taking advantage of the high-voltage resistance of the N-type silicon carbide substrate 100.

[0042] The shallow trench isolation layer can cut off the two-dimensional electron gas and make each device region independent of each other, and each device region can be used to form at least one complete HEMT device. The first shallow trench isolation layer 510 can isolate the high-voltage device region 520 and the low-voltage device region 530. By using the first drift region 210, the high-voltage HEMT device in the high-voltage device region 520 can avoid affecting the low-voltage HEMT device formed in the low-voltage device region 530 when the high-voltage current passes through the second drift region 220.

[0043] In an embodiment, the material of the shallow trench isolation layer can be silicon dioxide (SiO2) or silicon nitride (SiN).

[0044] In an embodiment, the materials of the first drift region 210, the N-type silicon carbide substrate 100 and the second drift region 220 are all N-type silicon carbide (N-type SiC), and the material of the floating island structure 211 is P-type silicon carbide (P-type SiC). The floating island structure 211 can isolate the second drift region 220 and the low-voltage device region 530, and avoid affecting the low-voltage device region 530 when the high-voltage device region 520 conducts electricity through the second drift region 220. In preparation, the floating island structure 211 can be formed by ion implantation.

[0045] In an embodiment, the plurality of floating island structures 211 are parallel to the N-type silicon carbide substrate 100, and the distance between adjacent floating island structures 211 is equal. The plurality of floating island structures 211 arranged in parallel makes the electric field in the first drift region 210 more uniform, avoiding local electric field strength too large, so that the drift layer 200 is not broken down.

[0046] In an embodiment, the width of the plurality of floating island structures 211 is not less than the width of the low-voltage device region 530, and equal to the width of the first drift region 210. The width of the second drift region 220 is greater than the width of the intermediate metal layer 620, and less than the width of the high-voltage device region 520. In an example, the width of the second drift region 220 is equal to half the width of the high-voltage device region 520, so as to avoid the second drift region 220 being too small, thereby ensuring that the second drift region 220 can sufficiently conduct high-voltage current. In an example, the width of the floating island structure 211 is greater than the width of the low-voltage device region 530. Wherein, the high-voltage source electrode 630 is located above the first drift region 210, and the intermediate metal layer 620 is located above the second drift region 220.

[0047] In an embodiment, the ion doping concentration of the N-type silicon carbide substrate 100 is greater than the ion doping concentration of the second drift region 220.

[0048] In an embodiment, the ion doping concentration of the plurality of floating island structures 211 is in a positive proportional relationship with the distance from the N-type silicon carbide substrate 100, that is, the ion doping concentration of the floating island structure 211 closer to the buffer layer 300 is higher, so as to optimize the electric field of the first drift region 210.

[0049] In an embodiment, the material of the barrier layer 500 is aluminum gallium nitride (AlGaN), and the material of the channel layer 400 is gallium nitride (GaN). The material of the buffer layer 300 is aluminum nitride (AlN). AlGaN and GaN contact will generate two-dimensional electron gas, and by controlling the on-off of the two-dimensional electron gas, the on-off of the corresponding switching device can be controlled.

[0050] In an embodiment, the material of the high-voltage gate electrode 640 is a Schottky metal, and the materials of the high-voltage source electrode 630 and the high-voltage drain electrode 610 are ohmic metals. Wherein, the material of the high-voltage gate electrode 640 can be any one of aluminum (Al) and platinum (Pt), and the materials of the high-voltage source electrode 630 and the high-voltage drain electrode 610 can be titanium (Ti).

[0051] In an embodiment, as shown in FIG. 6, the plurality of floating island structures 211 are arranged in parallel to the N-type silicon carbide substrate 100, and the distance between adjacent floating island structures 211 is equal. The plurality of floating island structures 211 arranged in parallel makes the electric field in the first drift region 210 more uniform, avoiding local electric field strength too large, so that the drift layer 200 is not broken down. Figure 1As shown, the high-voltage gate 640 is directly arranged on the barrier layer 500, and the high-voltage power device of the embodiment is a depletion mode (D-mode) power device. When the voltage applied to the high-voltage gate 640 is 0, the two-dimensional electron gas between the high-voltage source 630 and the high-voltage drain 610 is turned on, that is, the depletion mode power device is in a conducting state. When the value of the negative voltage applied to the high-voltage gate 640 is greater than the turn-on voltage of the depletion mode power device, the corresponding two-dimensional electron gas below the high-voltage gate 640 is cut off, and the depletion mode power device is turned off.

[0052] In an embodiment, as shown in FIG. 6, the high-voltage power device further includes a first P-type cap layer 710 arranged between the barrier layer 500 and the high-voltage gate 640. Figure 2

[0053] Specifically, the material of the first P-type cap layer 710 is P-type gallium nitride (P-GaN).

[0054] It should be noted that the power device with the first P-type cap layer 710 arranged between the high-voltage gate 640 and the barrier layer 500 is an enhancement mode (E-mode) power device. When a positive voltage with a value greater than the turn-on voltage is applied to the high-voltage gate 640, the two-dimensional electron gas between the high-voltage source 630 and the intermediate metal layer 620 can remain conductive, and the current received by the high-voltage drain 610 can be transmitted to the high-voltage source 630 through the N-type silicon carbide substrate 100, the second drift region 220, the intermediate metal layer 620 and the two-dimensional electron gas in turn.

[0055] When the voltage applied to the high-voltage gate 640 is less than the turn-on voltage or is a negative voltage, the corresponding two-dimensional electron gas below the high-voltage gate 640 is cut off. At this time, the current received by the high-voltage drain 610 cannot be transmitted to the high-voltage source 630 through the two-dimensional electron gas after being transmitted to the intermediate metal layer 620 through the N-type silicon carbide substrate 100 and the second drift region 220 in turn.

[0056] In an embodiment, as shown in FIG. 6, the high-voltage power device further includes a first P-type cap layer 710 arranged between the barrier layer 500 and the high-voltage gate 640. Figure 1 As shown, the second shallow trench isolation layer 540 is arranged in the barrier layer 500 and the channel layer 400 of the low-voltage device region 530 and penetrates into the buffer layer 300, so as to divide the low-voltage device region 530 into a plurality of low-voltage device sub-regions 531, and the plurality of low-voltage device sub-regions 531 are all located above the first drift region 210. Each low-voltage device sub-region 531 is used to form a low-voltage HEMT device.

[0057] ​In one embodiment, each low-voltage device sub-region 531 is provided with a low-voltage source 810, a low-voltage drain 820, and a low-voltage gate 830 to form a low-voltage HEMT device. The low-voltage source 810 and low-voltage drain 820 are respectively disposed on both sides of the barrier layer 500 in the corresponding low-voltage device sub-region 531 and extend into the channel layer 400 in the corresponding low-voltage device sub-region 531. The low-voltage gate 830 is disposed on the barrier layer 500 between the low-voltage source 810 and the low-voltage drain 820. Figure 2 As shown, since the low-voltage gate 830 is directly disposed on the barrier layer 500, the low-voltage HEMT device formed by this low-voltage device region 530 is a D-mode HEMT. Figure 2 As shown, in one example, in the three device regions, the low-voltage gate 830 in the middle low-voltage device region 530 is directly disposed on the barrier layer 500.

[0058] In one embodiment, a second P-type capping layer 720 is also provided between the low-voltage gate 830 and the barrier layer 500 in a portion of the low-voltage device sub-region 531. Because the second P-type capping layer 720 is provided between the low-voltage gate 830 and the barrier layer 500, the HEMT device formed in this low-voltage device region 530 is an E-mode HEMT. Figure 2 As shown, in one example, in the three device regions, the low-voltage gate 830 in the low-voltage device region 530 located on the left is disposed on the barrier layer 500 through the second P-type capping layer 720.

[0059] It should be noted that both D-mode HEMTs and E-mode HEMTs can be set in each low-voltage device sub-area 531. The number and location of D-mode HEMTs and E-mode HEMTs can be determined according to the actual situation.

[0060] In one embodiment, the high-voltage source 630 includes a high-voltage fill metal layer 631 and a high-voltage lead metal layer 632. The high-voltage fill metal layer 631 extends from the upper surface of the barrier layer 500 to the channel layer 400. The high-voltage lead metal layer 632 is disposed above the barrier layer 500 and connected to the high-voltage fill metal layer 631. The thickness of the high-voltage fill metal layer 631 is greater than or equal to the thickness of the barrier layer 500. The high-voltage fill metal layer 631 is used to connect the high-voltage lead metal layer 632 and the two-dimensional electron gas, and the high-voltage lead metal layer 632 is used to connect to an external circuit.

[0061] In one embodiment, such as Figure 2 As shown, the thickness of the high-voltage filler metal layer 631 is equal to the thickness of the barrier layer 500, and the lower surface of the high-voltage filler metal layer 631 is in contact with the upper surface of the channel layer 400.

[0062] In one embodiment, such asFigure 3 As shown, the thickness of the high-voltage filler metal layer 631 is greater than the thickness of the barrier layer 500. The high-voltage filler metal layer 631 is inserted into the channel layer 400. Specifically, compared to the barrier layer 500, the increased thickness of the high-voltage filler metal layer 631 is equal to one-quarter of the thickness of the channel layer 400. By extending the high-voltage filler metal layer 631 downwards, the contact between the high-voltage filler metal layer 631 and the two-dimensional electron gas is made more sufficient, thereby improving the conductivity efficiency.

[0063] In one embodiment, the structures of the low-voltage source 810 and the low-voltage drain 820 are the same as those of the high-voltage source 630.

[0064] In one example, such as Figure 3 As shown, the low-voltage source 810 includes a source fill metal layer 811 and a source lead metal layer 812; the low-voltage drain 820 includes a drain fill metal layer 821 and a drain lead metal layer 822. The source fill metal layer 811 and the drain fill metal layer 821 correspond to the high-voltage fill metal layer 631, and the source lead metal layer 812 and the drain lead metal layer 822 correspond to the high-voltage lead metal layer 632. The specific structures of the source fill metal layer 811, the source lead metal layer 812, the drain fill metal layer 821, and the drain lead metal layer 822 will not be described in detail in this embodiment.

[0065] In one embodiment, the thickness of the semiconductor substrate 100 is 10 nm to 30 nm, the thickness of the drift layer 200 is 50 nm to 100 nm, the thickness of the buffer layer 300 is 3 nm to 30 nm, the thickness of the channel layer 400 is 3 nm to 30 nm, and the thickness of the barrier layer 500 is 3 nm to 30 nm.

[0066] In one example, the semiconductor substrate 100 has a thickness of 20 nm, the drift layer 200 has a thickness of 60 nm, the buffer layer 300 has a thickness of 20 nm, the channel layer 400 has a thickness of 20 nm, and the barrier layer 500 has a thickness of 20 nm. The fill metal layer 710 has a thickness of 25 nm, and correspondingly, the channel layer 400 below the fill metal layer 710 has a thickness of 15 nm.

[0067] In one embodiment, the thickness of the P-type capping layer 610 is 2 nm to 5 nm.

[0068] Figure 4 A flowchart illustrating the fabrication method of the high-voltage resistant switching device integrating low-voltage components according to the second embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are detailed below:

[0069] A method for fabricating a high-voltage resistant switch device integrating low-voltage devices, which can be used to fabricate a high-voltage resistant switch device integrating low-voltage devices in any of the above embodiments, the method for fabricating a high-voltage resistant switch device integrating low-voltage devices includes steps S100 to S700.

[0070] In step S100, a drift layer 200 is deposited on the front side of the N-type silicon carbide substrate 100.

[0071] In one embodiment, such as Figure 5 As shown, the drift layer 200 includes a first drift region 210 and a second drift region 220 arranged side by side, and the first drift region 210 is provided with a plurality of floating island structures 211 with different doping types than the drift layer 200. The width of the floating island structure 211 can be equal to the width of the first drift region 210.

[0072] Specifically, such as Figure 6 As shown, a first epitaxial layer 230 and a second epitaxial layer 240 can be sequentially and alternately deposited on the front side of an N-type silicon carbide substrate 100 to form a drift layer 200. After each formation of the first epitaxial layer 230, P-type ions can be implanted into the ion implantation region 250 of the first epitaxial layer 230 and heated to a high temperature to form a floating island structure 211, which, together with a corresponding portion of the second epitaxial layer 240, forms a first drift region 210. The portion of the first epitaxial layer 230 outside the ion implantation region 250 is used to form a second drift region 220 together with a corresponding portion of the second epitaxial layer 240.

[0073] In step S200, a buffer layer 300, a channel layer 400, a barrier layer 500 and a P-type capping layer 700 are sequentially deposited on the front side of the drift layer 200.

[0074] like Figure 7 As shown, the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap layer 700 are stacked sequentially on the upper side of the drift layer 200.

[0075] In step S300, the P-type capping layer 700 is etched to form a first P-type capping layer 710 and a second P-type capping layer 720. The number and position of the first P-type capping layer 710 and the second P-type capping layer 720 can be adjusted according to actual needs.

[0076] In one example, such as Figure 8 As shown, a first P-type capping layer 710 is formed above the second drift region 220, and a second P-type capping layer 720 is formed above the first drift region 210.

[0077] In step S400, the channel layer 400 and the barrier layer 500 are etched to form a first trench and a second trench, and insulating material is deposited in the first trench and the second trench to form a first shallow trench isolation layer 510 and a second shallow trench isolation layer 540. The first shallow trench isolation layer 510 extends to the buffer layer 300 to divide the barrier layer 500 and the channel layer 400 into a high-voltage device region 520 and a low-voltage device region 530. The second shallow trench isolation layer 540 extends to the buffer layer 300 and is located in the low-voltage device region 530 to divide the low-voltage device region 530 into a plurality of low-voltage device sub-regions 531.

[0078] In an example, as shown in FIG. 5, there is one first shallow trench isolation layer 510 and one second shallow trench isolation layer 540, and both are disposed between two first P-type cap layers 710, thereby forming a low-voltage device sub-region 531 provided with a second P-type cap layer 720, a low-voltage device sub-region 531 not provided with a second P-type cap layer 720, and a high-voltage device region 520 provided with a first P-type cap layer 710. Figure 9

[0079] In an embodiment, after step S400 is performed, the high-voltage device region 520 includes at most one first P-type cap layer 710, and each low-voltage device sub-region 531 includes at most one second P-type cap layer 720. Whether the high-voltage device region 520 and each low-voltage device sub-region 531 includes a first P-type cap layer 710 or a second P-type cap layer 720 is determined by actual needs.

[0080] In step S500, the channel layer 400 and the barrier layer 500 are etched to form a plurality of low-voltage electrode trenches 840 in the low-voltage device region 530, and a first high-voltage trench 650 and a second high-voltage trench 660 in the high-voltage device region 520. The first high-voltage trench 650 is located on a first side of the buffer layer 300, the channel layer 400, and the barrier layer 500 and extends to the second drift region 220, and the second high-voltage trench 660 is located on a second side of the barrier layer 500 in the high-voltage device region 520 and extends to the channel layer 400. The depths of the low-voltage electrode trenches 840 and the second high-voltage trench 660 can be greater than or equal to the thickness of the barrier layer 500. The low-voltage electrode trenches 840 are provided on both sides of each low-voltage device sub-region 531.

[0081] In an example, as shown in FIG. 6, the depths of the low-voltage electrode trenches 840 and the second high-voltage trench 660 are equal to the thickness of the barrier layer 500. Figure 10

[0082] In an example, as shown in FIG. 7, the depths of the low-voltage electrode trenches 840 and the second high-voltage trench 660 are greater than the thickness of the barrier layer 500. Figure 11 ​​As shown, the depths of the low-voltage electrode trench 840 and the second high-voltage trench 660 are both greater than the thickness of the barrier layer 500. Compared with the barrier layer 500, the increased depth of the low-voltage electrode trench 840 and the second high-voltage trench 660 is equal to one-quarter of the thickness of the channel layer 400.

[0083] In step S600, metal material is deposited in a plurality of low-voltage electrode trenches 840 to form a low-voltage source electrode 810 and a low-voltage drain electrode 820, and metal material is deposited in a first high-voltage trench 650 and a second high-voltage trench 660 to form an intermediate metal layer 620 and a high-voltage source electrode 630, respectively.

[0084] In one embodiment, step S600 specifically involves depositing metal material in a plurality of low-voltage electrode trenches 840 to form corresponding source-filled metal layers 811 and drain-filled metal layers 821, and depositing metal material in a first high-voltage trench 650 and a second high-voltage trench 660 to form an intermediate metal layer 620 and a high-voltage filled metal layer 631, respectively. The low-voltage source 810 includes a source-filled metal layer 811, the low-voltage drain 820 includes a drain-filled metal layer 821, and the high-voltage source 630 includes a high-voltage filled metal layer 631.

[0085] like Figure 12 As shown, each low-voltage device sub-region 531 is provided with a source-filled metal layer 811 and a drain-filled metal layer 821. The source-filled metal layer 811 and the drain-filled metal layer 821 in the same low-voltage device sub-region 531 are located on the left and right sides of the corresponding low-voltage device sub-region 531, respectively. A second P-type capping layer 720 is provided on the barrier layer 500 between the source-filled metal layer 811 and the drain-filled metal layer 821 in one of the low-voltage device sub-regions 531.

[0086] In step S700, a high-voltage gate 640 is formed on the barrier layer 500 or the first P-type capping layer 710 in the high-voltage device region 520, a low-voltage gate 830 is formed on the barrier layer 500 or the second P-type capping layer 720 in the low-voltage device region 530, and a high-voltage drain 610 is formed on the back side of the N-type silicon carbide substrate 100.

[0087] In an embodiment, step S700 is specifically forming the high-voltage gate 640 on the barrier layer 500 or the first P-type cap layer 710 in the high-voltage device region 520, forming the low-voltage gate 830 on the barrier layer 500 or the second P-type cap layer 720 in the low-voltage device region 530, and forming the high-voltage drain 610 on the back of the N-type silicon carbide substrate 100, while forming the high-voltage lead metal layer 632, the source lead metal layer 812, and the drain lead metal layer 822 on the barrier layer 500. The high-voltage lead metal layer 632 is in contact with the high-voltage filling metal layer 631, the source lead metal layer 812 is in contact with the source filling metal layer 811, and the drain lead metal layer 822 is in contact with the drain filling metal layer 821. The lead metal layers are used to connect with external circuits.

[0088] In an embodiment, each lead metal layer is not in contact with each other. The upper side of each filling metal layer is provided with a corresponding lead metal layer in contact with each other.

[0089] In an example, as shown in FIG. 6, there are two low-voltage device sub-regions 531, one of which is provided with the second P-type cap layer 720, and the low-voltage gate 830 of the low-voltage device sub-region 531 is formed on the second P-type cap layer 720. The other low-voltage device sub-region 531 is not provided with the second P-type cap layer 720, and the low-voltage gate 830 of the low-voltage device sub-region 531 is formed on the barrier layer 500. Figure 3 In an example, as shown in FIG. 6, there are two low-voltage device sub-regions 531, one of which is provided with the second P-type cap layer 720, and the low-voltage gate 830 of the low-voltage device sub-region 531 is formed on the second P-type cap layer 720. The other low-voltage device sub-region 531 is not provided with the second P-type cap layer 720, and the low-voltage gate 830 of the low-voltage device sub-region 531 is formed on the barrier layer 500.

[0090] Figure 3 In an example, as shown in FIG. 6, there are two low-voltage device sub-regions 531, one of which is provided with the second P-type cap layer 720, and the low-voltage gate 830 of the low-voltage device sub-region 531 is formed on the second P-type cap layer 720. The other low-voltage device sub-region 531 is not provided with the second P-type cap layer 720, and the low-voltage gate 830 of the low-voltage device sub-region 531 is formed on the barrier layer 500.

[0091] The number, position, and specific structure of the HEMT devices formed in the low-voltage device sub-regions 531 can be configured according to actual needs to form a low-voltage digital circuit, and the specific structure of the source, gate, and drain in the low-voltage device region 530 is not limited in the present embodiment.

[0092] In an embodiment, in steps S100 and S200, the drift layer 200, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 can be deposited by a known method such as chemical vapor deposition (CVD), and the deposition method of the drift layer 200, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 is not limited in the present embodiment.

[0093] ​In an embodiment, in steps S300, S400 and S500, the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap layer 610 can be etched by using a known method such as dry etching or wet etching, and the embodiment is not limited to the etching method of the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap layer 610. In an example, the buffer layer 300, the channel layer 400, the barrier layer 500 and the P-type cap layer 610 can be etched by using an inductive coupled plasma (ICP) etching method.

[0094] In an embodiment, in steps S600 and S700, the gate 600, the source 700, the intermediate metal layer 800 and the drain 900 can be constructed by using a known method such as vacuum evaporation or sputtering, and the embodiment is not limited to the specific construction method of the gate 600, the source 700, the intermediate metal layer 800 and the drain 900.

[0095] Figure 13 A structure schematic diagram of a chip provided by the third embodiment of the present application is shown, and only parts related to the embodiment are shown for the convenience of description, and the details are as follows:

[0096] A chip 10 includes the integrated low-voltage device high-voltage resistant switching device 20 according to any one of the above embodiments, or includes the integrated low-voltage device high-voltage resistant switching device 20 prepared by the preparation method according to any one of the above embodiments. Specifically, the chip 10 includes a switching circuit or a logic circuit composed of a plurality of integrated low-voltage device high-voltage resistant switching devices 20, and the integrated low-voltage device high-voltage resistant switching device 20 serves as a switching element therein. The embodiment is not limited to the type of the circuit, and the specific circuit can be an existing circuit, and the number and connection relationship of the integrated low-voltage device high-voltage resistant switching devices 20 can be set according to the specific requirements.

[0097] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0098] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit or module in the embodiment can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit, and the integrated unit can be realized in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit or module are only for the convenience of mutual distinction, and are not used to limit the protection scope of the application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, and will not be described here.

[0099] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0100] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A high-voltage resistant switching device integrating low-voltage components, characterized in that, include: N-type silicon carbide substrate; A drift layer, a buffer layer, a channel layer, and a barrier layer are sequentially stacked on the front side of the N-type silicon carbide substrate; wherein, the drift layer includes a first drift region and a second drift region arranged side by side, and the first drift region is provided with a plurality of floating island structures with different doping types from the drift layer. A first shallow trench isolation layer is disposed in the barrier layer and the channel layer and extends into the buffer layer to divide the barrier layer and the channel layer into a high-voltage device area and a low-voltage device area. The high-voltage drain is located on the back side of the N-type silicon carbide substrate; An intermediate metal layer is disposed on the second drift region and is in contact with the first side of the buffer layer, the channel layer and the barrier layer of the high voltage device region; A high-voltage source electrode is disposed on the second side of the barrier layer within the high-voltage device region and extends into the channel layer; A high-voltage gate is disposed on the barrier layer between the intermediate metal layer and the high-voltage source. The low-voltage source, low-voltage drain, and low-voltage gate are all located within the low-voltage device region to form a corresponding low-voltage HEMT device. The low-voltage source and the low-voltage drain are both disposed on the channel layer and in contact with the barrier layer, and the low-voltage gate is disposed on the barrier layer between the low-voltage source and the low-voltage drain.

2. The high-voltage resistant switching device integrating low-voltage components as described in claim 1, characterized in that, The drift layer is N-type silicon carbide, the floating island structure is P-type silicon carbide, the barrier layer is aluminum gallium nitride, and the channel layer is gallium nitride.

3. The high-voltage resistant switching device with integrated low-voltage components as described in claim 1, characterized in that, The multiple floating island structures are arranged parallel to the N-type silicon carbide substrate, and the distance between adjacent floating island structures is equal.

4. The high-voltage resistant switching device with integrated low-voltage components as described in claim 1, characterized in that, The width of each of the multiple floating island structures is not less than the width of the low-voltage device area.

5. The high-voltage resistant switching device with integrated low-voltage components as described in claim 1, characterized in that, The ion doping concentration of the multiple floating island structures is directly proportional to the distance from the N-type silicon carbide substrate.

6. The high-voltage resistant switching device with integrated low-voltage components as described in claim 1, characterized in that, It also includes a second shallow trench isolation layer, which is disposed in the barrier layer and the channel layer of the low-voltage device region and extends into the buffer layer to divide the low-voltage device region into multiple low-voltage device sub-regions, all of which are located above the first drift region; each low-voltage device is provided with a low-voltage source, a low-voltage drain and a low-voltage gate.

7. The high-voltage resistant switching device with integrated low-voltage components as described in claim 1, characterized in that, It also includes the first P-type cap layer; The first P-type capping layer is disposed between the barrier layer and the high-voltage gate.

8. A method for fabricating a high-voltage resistant switching device integrating low-voltage components, characterized in that, include: A drift layer is deposited on the front side of an N-type silicon carbide substrate; wherein the drift layer includes a first drift region and a second drift region arranged side by side, and the first drift region is provided with a plurality of floating island structures that are different from the doping type of the drift layer; A buffer layer, a channel layer, a barrier layer, and a P-type capping layer are sequentially deposited on the front side of the drift layer; The P-type capping layer is etched to form a first P-type capping layer and a second P-type capping layer; The channel layer and the barrier layer are etched to form a first trench and a second trench, and insulating material is deposited in the first trench and the second trench to form a first shallow trench isolation layer and a second shallow trench isolation layer; wherein, the first shallow trench isolation layer extends into the buffer layer to divide the barrier layer and the channel layer into a high-voltage device region and a low-voltage device region; the second shallow trench isolation layer extends into the buffer layer and is located within the low-voltage device region to divide the low-voltage device region into multiple low-voltage device sub-regions; The channel layer and the barrier layer are etched to form a plurality of low-voltage electrode trenches in the low-voltage device region, and a first high-voltage trench and a second high-voltage trench are formed in the high-voltage device region; the first high-voltage trench is located on a first side of the buffer layer, the channel layer and the barrier layer and extends into the second drift region, and the second high-voltage trench is located on a second side of the barrier layer in the high-voltage device region and extends into the channel layer; Metal materials are deposited in multiple low-voltage electrode trenches to form low-voltage source electrodes and low-voltage drain electrodes, and metal materials are deposited in the first high-voltage trench and the second high-voltage trench to form an intermediate metal layer and a high-voltage source electrode, respectively. A high-voltage gate is formed on the barrier layer or the first P-type capping layer in the high-voltage device region, a low-voltage gate is formed on the barrier layer or the second P-type capping layer in the low-voltage device region, and a high-voltage drain is formed on the back side of the N-type silicon carbide substrate.

9. A chip, characterized in that, The chip includes a high-voltage resistant switching device comprising an integrated low-voltage device as described in any one of claims 1-7; or the chip comprises a high-voltage resistant switching device comprising an integrated low-voltage device prepared by the preparation method described in claim 8.

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