An adaptive high-voltage and low-loss power device

Abstract

The present invention belongs to the field of power semiconductor technology and relates to an adaptive high-voltage and low-loss power device. Compared with the traditional LIGBT structure, the present invention introduces an adaptive PMOS structure at the anode end of the LIGBT, and the gate of the PMOS structure is controlled by an integrated diode. When forward-conducting, the PMOS channel is closed, and the electron extraction path is blocked, thereby eliminating the snapback effect. During the shutdown process, as the anode voltage rises, the LIGBT anode PMOS channel is adaptively turned on, and the electrons in the drift region are converted into holes by the electrode 11, and then extracted from the P+ collector region through the PMOS channel; at the same time, the P+ collector region and the N-type buffer layer are almost short-circuited at the same potential, which inhibits the P+ collector region from injecting holes into the drift region, and the two jointly accelerate the shutdown of the device to reduce the shutdown loss. During forward blocking, the hole current in the P+ collector region is converted from the electrode 11 to the electron current and injected into the drift region through the PMOS channel, forming a MOS-like breakdown mode, which increases the breakdown voltage. Therefore, the present invention has smaller shutdown losses and higher breakdown voltages.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors and relates to an adaptive SOI LIGBT (Lateral Insulated Gate Bipolar Transistor) integrated with a diode. Background Art

[0002] The insulated gate bipolar transistor (IGBT) is a gate-controlled bipolar conductive device. Its gate-controlled characteristics give it the advantages of high input impedance and easy driving. Its bipolar conductivity makes it easy to achieve low on-state voltage drop and high current density, making it very suitable for use in high-voltage and high-power power electronics technology fields such as smart grids, rail transportation, and industrial control. Semiconductor devices based on SOI technology are easy to achieve full dielectric isolation, with lower leakage current and smaller parasitic effects.

[0003] When the LIGBT device is forward-conducted, the conductivity modulation effect occurs in the drift region and a large number of excess carriers are stored, which is beneficial to reduce the forward on-state voltage drop (Von) of the device. However, this will lead to a longer tail current when it is turned off, resulting in a larger turning off loss (Eoff). At the same time, due to the conductivity modulation effect, the voltage divider of the channel resistance accounts for a larger proportion of the forward on-state voltage drop of the IGBT.

[0004] In order to improve the contradictory relationship between the turn-off loss and the conduction voltage drop of the LIGBT device, the literature (MR Simpson, PAGough, FIH shieh, et al. Anlysis of the lateral insulated gate transistor [C]. IEEE International Electron Devices Meeting, Washington, 1985, 740-743) proposed a short-circuit anode structure, that is, introducing a short-circuited anode N+ region next to the anode P+ region to accelerate the extraction of electrons stored in the drift region during the device shutdown process. However, the short-circuit anode structure causes the device to have a snapback effect caused by the conversion from the unipolar conduction mode to the bipolar conduction mode when it is turned on, which reduces the reliability of the device in parallel. The literature (NKUdugampola, RAMcMahon, F.Udrea, et al. Analysis and design of the dual-gate inversion layer emitter transistor [J]. IEEE Transactions on Electron Devices, 2005, 52 (1): 99-105) proposed a dual-gate inversion layer injection type LIGBT; when forward conducting, the anode gate of this structure is negatively potentialed relative to the anode, and the drift region below the anode gate and the surface of the N-buffer layer will form a hole inversion layer connected to the P+ anode, which is equivalent to increasing the length of the P+ anode and the anode distributed resistance, thereby suppressing the snapback phenomenon; during the shutdown process, the anode gate is short-circuited with the anode, and the hole inversion layer under the anode gate disappears. At this time, under the action of the short-circuited anode, the P+ anode will stop injecting holes into the drift region, while the N+ anode will quickly extract electrons in the drift region, thereby accelerating the device shutdown and significantly reducing the shutdown loss value. However, this structure requires the introduction of an additional gate drive control circuit, which increases the device design cost and control difficulty. Summary of the invention

[0005] In view of the above problems, the present invention proposes an adaptive high-voltage and low-loss power device.

[0006] The technical solution of the present invention is an adaptive high-voltage low-loss power device, comprising a P-type substrate 1, an insulating dielectric layer 2 and an N-type semiconductor layer stacked in sequence from bottom to top, wherein the N-type semiconductor is divided into a first N drift region 31 and a second N drift region 32 by isolation grooves Ι and Ⅱ, which are used to form a LIGBT part and a diode part respectively.

[0007] The isolation trench I is composed of a first isolation trench dielectric layer 92 and a first isolation trench polysilicon layer 91 located in the first isolation trench dielectric layer 92; the isolation trench II is composed of a second isolation trench dielectric layer 94 and a second isolation trench polysilicon layer 93 located in the second isolation trench dielectric layer 94; the isolation trench I and the isolation trench II are both in contact with the upper surface of the insulating dielectric layer 2;

[0008] The diode part forms a diode cathode structure, a top P-type region 101 and a diode anode structure on the surface of the second N drift region 32 along the lateral direction; the diode cathode structure includes a second P-type well region 42 and a second P+ body contact region 52 located on the upper layer of the second P-type well region 42; the diode anode structure includes a second N-type buffer layer 8 and an N+ collector region 62 located on the upper layer of the second N-type buffer layer 8; the top P-type region 101 is located between the diode cathode structure and the diode anode structure, and its side surfaces are in contact with the second N-type buffer layer 8 and the second P-well region 42 respectively; the lead-out end of the second P+ body contact region is the diode cathode, and the lead-out end of the N+ collector region 62 is the diode anode;

[0009] The LIGBT part forms a LIGBT cathode structure, a gate structure and a LIGBT anode structure on the surface of the first N drift region 31 along the lateral direction; the LIGBT cathode structure includes a first P-type well region 41 and a first P+ body contact region 51 and an N+ emitter region 61 located on the upper layer of the first P-type well region 41 and arranged in sequence; the gate structure is a planar gate structure, and the planar gate structure includes a gate dielectric layer 15 and a polysilicon material 16 covering the upper surface of the gate dielectric layer, and the gate dielectric layer 15 is located between the N+ emitter region 61 and the first N drift region 31. An upper layer of a P-type well region, one end of which contacts the upper surface of the N+ emitter region 61, and the other end of which contacts the first N drift region 31; the LIGBT anode structure comprises a first N-type buffer layer 71 and a P+ collector region 72, and the P+ collector region 72 is located on the upper surface of the first N-type buffer region 71; the common lead-out end of the first P+ body contact region 51 and the N+ emitter region 61 is the LIGBT cathode, and is short-circuited with the diode cathode, the lead-out end of the polysilicon material 16 is the gate, and the lead-out end of the P+ collector region 72 is the LIGBT anode, and is short-circuited with the diode anode;

[0010] Features:

[0011] The LIGBT anode structure also has a PMOS structure, including the first N-type buffer layer 71, the P+ collector region 72, the third P+ body contact region 73, the N+ body contact region 74, the electrode 11 and the gate electrode structure; the third P+ body contact region 73 and the N+ body contact region 74 are located on the upper surface of the first N-type buffer region 71, and are located on the side of the P+ collector region 72 away from the first N drift region 31; the N+ body contact region 74 is located on the side of the third P+ body contact region 73 away from the P+ collector region 72, and the common lead-out end of the third P+ body contact region 73 and the N+ body contact region 74 is the electrode 11; the gate electrode structure includes a gate oxide layer 14 and a gate electrode 13 located above the gate oxide layer 14, the gate oxide layer 14 is located on the upper layer of the first N-type buffer layer 71, one end of which is in contact with the upper surface of the P+ collector region 72, and the other end of which is in contact with the upper surface of the third P+ body contact region 73;

[0012] The surface of the top P-type region 101 in the diode part is provided with an electrode 12 near the N+ collector region 62, and the electrode 12 is short-circuited with the gate electrode 13 of the PMOS structure;

[0013] Furthermore, the LIGBT portion has a top P-type region 102 , which is located on the first N drift region 31 , between the LIGBT cathode structure and the LIGBT anode structure, and whose side surface does not contact the first P well region 41 .

[0014] Furthermore, the semiconductor material used in the device is one of Si, SiC, SiGe, GaAs, GaO and GaN.

[0015] The beneficial effects of the present invention are as follows: compared with the traditional LIGBT structure, the PMOS structure in the LIGBT anode of the present invention provides a carrier extraction path when shutting down, which can improve the shutdown speed of the device, reduce the shutdown loss, and will not introduce the snapback phenomenon; the breakdown mode of the present invention is a MOS-like breakdown mode, which improves the breakdown voltage of the device, and the breakdown voltage does not change with the change of the doping concentration of the P+ collector region 72; the integrated diode in the present invention provides a low potential to turn on the PMOS during the LIGBT shutdown process, which effectively improves the shutdown speed of the device and reduces the shutdown loss without the need for an additional control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a structural diagram of Example 1

[0017] Figure 2 The structural diagram of Example 2

[0018] Figure 3 Schematic diagram of the layout of Example 3

[0019] Figure 4 Schematic diagram of the layout of Example 4 DETAILED DESCRIPTION

[0020] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0021] Example 1

[0022] like Figure 1 As shown, an anode-adaptive SOI LIGBT with an integrated diode in this example.

[0023] This example works like this:

[0024] When the new device is forward-conducted, the potential difference between the anode and the diode electrode 12 is small, and an inversion layer cannot be formed on the upper surface of the first N-type buffer layer 71. The LIGBT anode PMOS structure is in an off state, resulting in the conductive path between the P+ collector region 72 and the third P+ body contact region 73 and the N+ body contact region 74 being blocked, and the device cannot enter the unipolar conductive mode, thereby eliminating the snapback effect.

[0025] During the shutdown process of the new device, the diode part enters the reverse blocking state, and the potential difference between the anode and the electrode 12 of the diode part increases as the anode voltage rises. When the anode voltage rises further, the potential difference between the anode and the electrode 12 is large enough, and the corresponding PMOS channel on the upper surface of the first N-type buffer layer 71 is turned on, so that the P+ collector area 72 is short-circuited with the third P+ body contact area 73, and the third P+ body contact area 73 is short-circuited with the N+ body contact area 74 through the electrode 11, and then the P+ collector area 72 and the first N-type buffer layer 71 are almost short-circuited with the same potential, causing the P+ collector area 72 to stop injecting holes into the drift region. At the same time, the electrons in the drift region are converted into holes through the N+ body contact area 74 and the electrode 11, and then are quickly extracted by the P+ collector area 72 through the PMOS channel, further accelerating the shutdown of the device and reducing the shutdown loss.

[0026] When the new device is in the forward blocking state, the potential difference between the anode and the electrode 12 is large enough, and the corresponding PMOS channel on the upper surface of the first N-type buffer layer 71 is opened, and the P+ collector region 72 and the first N-type buffer layer 71 are almost short-circuited at the same potential, causing the P+ collector region 72 to stop directly injecting holes into the drift region. The hole current flowing out through the P+ collector region 72 reaches the third P+ body contact region 73 through the PMOS channel, and is converted into an electron current through the electrode 11 and injected into the drift region. Therefore, the breakdown mode of the new device is MOS-like breakdown, which improves the breakdown voltage of the device, and the breakdown voltage of the new device does not change with the doping concentration of the P+ collector region 72.

[0027] The beneficial effect of the present invention is that, compared with the traditional LIGBT structure, the present invention can accelerate the device shutdown to reduce the shutdown loss, eliminate the snapback effect, and improve the device withstand voltage without the need for an additional control circuit.

[0028] Embodiment 2:

[0029] like Figure 2 As shown, the difference between this embodiment and embodiment 1 is that a top P-type region 102 is further provided on the upper layer of the first N drift region 31, between the LIGBT cathode structure and the LIGBT anode structure, and the side of the top P-type region 102 is not in contact with the first P well region 41. Compared with embodiment 1, the top P-type region 102 and the first N drift region 31 form a super junction, which improves the device withstand voltage, accelerates the depletion speed of the drift region of the LIGBT part during the device shutdown process, and reduces the device shutdown loss.

[0030] Embodiment 3:

[0031] like Figure 3 As shown, this example is a layout form of embodiment 1 and embodiment 2, the racetrack-shaped active area is the LIGBT part, and the diode part is located in the racetrack-shaped terminal area. At this time, the diode part is used to extract the potential to control the LIGBT anode PMOS structure. The diode part of this embodiment does not occupy the device active area, which improves the layout area utilization.

[0032] Embodiment 4:

[0033] like Figure 4 As shown, the difference between this embodiment and embodiment 3 is that, in terms of layout, the LIGBT part and the diode part of the device are symmetrically distributed in the active areas on both sides of the racetrack. Compared with embodiment 3, the diode part is not only used to control the LIGBT anode PMOS structure, but also used for reverse freewheeling. In the reverse freewheeling state, the super junction composed of the top P-type region 101 and the second N drift region 32 accelerates the depletion speed of the drift region of the diode part, shortens the reverse recovery time trr of the device, and reduces the reverse recovery loss of the device.

Claims

1. An adaptive high-voltage low-loss power device, comprising a P-type substrate (1), an insulating dielectric layer (2) and an N-type semiconductor layer stacked in sequence from bottom to top, wherein the N-type semiconductor is divided into a first N drift region (31) and a second N drift region (32) by a first isolation trench and a second isolation trench, which are used to form a LIGBT part and a diode part respectively; The first isolation trench is composed of a first isolation trench dielectric layer (92) and a first isolation trench polysilicon layer (91) located in the first isolation trench dielectric layer (92); the second isolation trench is composed of a second isolation trench dielectric layer (94) and a second isolation trench polysilicon layer (93) located in the second isolation trench dielectric layer (94); the first isolation trench and the second isolation trench are both in contact with the upper surface of the insulating dielectric layer (2); The diode portion forms a diode cathode structure, a top P-type region (101) and a diode anode structure on the surface of the second N-drift region (32) in the lateral direction; the diode cathode structure comprises a second P-type well region (42) and a second P+ body contact region (52) located on the upper layer of the second P-type well region (42); the diode anode structure comprises a second N-type buffer layer (8) and an N+ collector region (62) located on the upper layer of the second N-type buffer layer (8); the top P-type region (101) is located between the diode cathode structure and the diode anode structure, and its side surfaces are respectively in contact with the second N-type buffer layer (8) and the second P-type well region (42); the lead-out end of the second P+ body contact region is the diode cathode, and the lead-out end of the N+ collector region (62) is the diode anode; The LIGBT portion forms a LIGBT cathode structure, a gate structure and a LIGBT anode structure on the surface of the first N drift region (31) along a lateral direction; the LIGBT cathode structure comprises a first P-type well region (41) and a first P+ body contact region (51) and an N+ emitter region (61) located on an upper layer of the first P-type well region (41) and arranged in sequence; the gate structure is a planar gate structure, the planar gate structure comprises a gate dielectric layer (15) and a polysilicon material (16) covering the upper surface of the gate dielectric layer, the gate dielectric layer (15) being located between the N+ emitter region (61) and the first N drift region (31). The upper layer of the first P-type well region has one end in contact with the upper surface of the N+ emitter region (61) and the other end in contact with the first N drift region (31); the LIGBT anode structure comprises a first N-type buffer layer (71) and a P+ collector region (72), and the P+ collector region (72) is located on the upper surface of the first N-type buffer layer (71); the common lead-out end of the first P+ body contact region (51) and the N+ emitter region (61) is the LIGBT cathode and is short-circuited with the diode cathode, the lead-out end of the polysilicon material (16) is the gate, and the lead-out end of the P+ collector region (72) is the LIGBT anode and is short-circuited with the diode anode; Features: The LIGBT anode structure also has a PMOS structure, comprising the first N-type buffer layer (71), the P+ collector region (72), a third P+ body contact region (73), an N+ body contact region (74), an electrode (11), and a gate electrode structure; the third P+ body contact region (73) and the N+ body contact region (74) are located on the upper surface of the first N-type buffer layer (71), on a side of the P+ collector region (72) away from the first N drift region (31); the N+ body contact region (74) ) is located on a side of the third P+ body contact region (73) away from the P+ collector region (72), and the common lead-out end of the third P+ body contact region (73) and the N+ body contact region (74) is an electrode (11); the gate electrode structure comprises a gate oxide layer (14) and a gate electrode (13) located above the gate oxide layer (14), the gate oxide layer (14) is located on the upper layer of the first N-type buffer layer (71), one end of the gate oxide layer is in contact with the upper surface of the P+ collector region (72), and the other end of the gate oxide layer is in contact with the upper surface of the third P+ body contact region (73); A surface of the top P-type region (101) in the diode portion is provided with an electrode (12) on one side close to the N+ collector region (62), and the electrode (12) is short-circuited with a gate electrode (13) of the PMOS structure.

2. The adaptive high-voltage low-loss power device according to claim 1, characterized in that: The LIGBT portion has a top P-type region (102), the top P-type region (102) in the LIGBT is located on the upper layer of the first N drift region (31), between the LIGBT cathode structure and the LIGBT anode structure, and its side surface is not in contact with the first P-type well region (41).

3. The adaptive high-voltage low-loss power device according to claim 1, wherein the semiconductor material used in the device is one of Si, SiC, SiGe, GaAs, GaO and GaN.

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