Six-input dynamic comparator

Abstract

This disclosure provides a six-input dynamic comparator, comprising: a dynamic amplifier and a latch connected in sequence; the dynamic amplifier includes: a positive input unit, a negative input unit, a clock unit, and an output unit. The positive input unit includes: a first positive input terminal, a second positive input terminal, and a third positive input terminal; the negative input unit includes: a first negative input terminal, a second negative input terminal, and a third negative input terminal; the clock unit is used to output a square wave clock signal; the output unit includes a first output node and a second output node; the dynamic amplifier is used to sum and amplify the six input signals, and the first output node and the second output node respectively output a first output signal and a second output signal; the latch is used to amplify and invert the first output signal and the second output signal respectively to obtain a third output signal and a fourth output signal, and discharges the output signal based on the magnitude of the third output signal and the fourth output signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a low kickback noise six-input dynamic comparator for extremely low temperatures. Background Technology

[0002] Analog-to-digital converters (ADCs) convert continuous analog signals into discrete digital signals. With the continuous development of technologies such as quantum computing and deep space exploration, there is a growing demand for low-power, high-precision ADCs that can operate normally at extremely low temperatures. Cascaded integrator-feedforward noise-shaping successive approximation ADCs combine the advantages of DeltaSigma and SAR structures. Combined with oversampling techniques, they can significantly improve the signal-to-noise ratio. The core of this cascaded integrator-feedforward noise-shaping successive approximation ADC is a multi-input comparator. Currently, it is difficult to meet the low kickback noise requirements in extremely low-temperature environments. Therefore, how to provide a multi-input comparator that can operate at extremely low temperatures while achieving low kickback noise is a pressing technical challenge. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address the aforementioned issues, this disclosure provides a six-input dynamic comparator to alleviate the technical problems of existing multi-input comparators failing to meet the low kickback noise requirements in extremely low temperature environments.

[0005] (II) Technical Solution

[0006] This disclosure provides a six-input dynamic comparator, comprising: a dynamic amplifier and a latch connected in sequence; the dynamic amplifier includes: a positive input unit, a negative input unit, a clock unit, and an output unit. The positive input unit includes: a first positive input terminal Vp1 for inputting a first positive input signal; a second positive input terminal Vp2 for inputting a second positive input signal; and a third positive input terminal Vp3 for inputting a third positive input signal. The negative input unit includes: a first negative input terminal Vn1 for inputting a first negative input signal; a second negative input terminal Vn2 for inputting a second negative input signal; and a third negative input terminal Vn3 for inputting a third negative input signal. The clock unit outputs a square wave clock signal CLK. The output unit includes: a first output node A. P Second output node A N The dynamic amplifier is used to sum and amplify six input signals, and is output from the first output node A. P Second output node A NThe first output signal AP and the second output signal AN are output respectively; the latch is used to amplify and invert the first output signal and the second output signal respectively to obtain the third output signal AP′ and the fourth output signal AN′, and discharge the output based on the comparison of the magnitudes of the third output signal and the fourth output signal.

[0007] According to an embodiment of this disclosure, the dynamic amplifier further includes a footer transistor unit, which includes a first footer transistor MN7 and a second footer transistor MN8; wherein the gates of the first footer transistor MN7 and the second footer transistor MN8 are commonly connected to a clock unit, and the drain of the first footer transistor MN7 is connected to a second output node A. N The drain of the second footer tube MN8 is connected to the first output node AP.

[0008] According to an embodiment of this disclosure, the positive input unit further includes: a first core input transistor MN1 and a first capacitor MN1′ whose gates are both connected to the first positive input terminal Vp1; a second core input transistor MN2 and a second capacitor MN2′ whose gates are both connected to the second positive input terminal Vp2; and a third core input transistor MN3 and a third capacitor MN3′ whose gates are both connected to the third positive input terminal Vp3; wherein, the drains of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3 are respectively connected to the source of the first footer transistor MN7, and the source and drain of the first capacitor MN1′, the second capacitor MN2′, and the third capacitor MN3′ are short-circuited and then respectively connected to the source of the second footer transistor MN8, and the width-to-length ratio of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3 is 1:k:m, where k and m represent amplification factors, and k and m are integers.

[0009] According to an embodiment of this disclosure, the negative input unit further includes: a fourth core input transistor MN4 and a fourth capacitor MN4' whose gates are all connected to the first negative input terminal Vn1; a fifth core input transistor MN5 and a fifth capacitor MN5' whose gates are all connected to the second negative input terminal Vn2; and a sixth core input transistor MN6 and a sixth capacitor MN6' whose gates are all connected to the third negative input terminal Vn3; wherein, the drains of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 are respectively connected to the source of the second footer transistor MN8, and the source and drain of the fourth capacitor MN4', the fifth capacitor MN5', and the sixth capacitor MN6' are short-circuited and then connected to the source of the first footer transistor MN7, and the width-to-length ratio of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 is 1:k:m, where k and m represent amplification factors, and k and m are integers.

[0010] According to an embodiment of this disclosure, the dynamic amplifier further includes: a first reset transistor MP1, a second reset transistor MP2, a third reset transistor MP3, and a wake transistor MN9; the drain of the first reset transistor MP1 is connected to the second output node A. N The source of the second reset transistor MP2 is connected to the power supply terminal VDD; the drain of the second reset transistor MP2 is connected to the first output node A. P The source of the second reset transistor MP2 is connected to the power supply terminal VDD. The gate of the second reset transistor MP2 and the gate of the first reset transistor MP1 are connected to the clock unit. The source of the third reset transistor MP3 is connected to the source of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3. The drain of the third reset transistor MP3 is connected to the power supply terminal VDD. The drain of the wake transistor MN9 is connected to the source of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 and is connected to the source of the third reset transistor MP3. The source of the wake transistor MN9 is grounded. The gate of the wake transistor MN9 and the gate of the third reset transistor MP3 are connected to the clock unit.

[0011] According to an embodiment of this disclosure, the six-input dynamic comparator further includes: a first capacitor C1 and a second capacitor C2. One end of the first capacitor C1 is connected to the second output node A. N One end of the capacitor is grounded; one end of the second capacitor C2 is connected to the first output node A. P The other end is grounded.

[0012] According to an embodiment of this disclosure, the latch includes: a first inverter pair and a second inverter pair. The first inverter pair is connected to the second output node A. N Connected to the first output node A, it amplifies and inverts the second output signal AN to obtain the fourth output signal AN′; the second inverter is connected to the first output node A. P Connected, it is used to amplify and invert the first output signal AP to obtain the third output signal AP′.

[0013] According to an embodiment of this disclosure, the first inverter pair includes: a fourth PMOS transistor MP4 and a tenth NMOS transistor MN10. The gate of the fourth PMOS transistor MP4 is connected to the second output node A. N The source of the tenth NMOS transistor MN10 is connected to the power supply terminal VDD; the source of the tenth NMOS transistor MN10 is grounded, and its gate is connected to the first output node A. P The drain is connected to the drain of the fourth PMOS transistor MP4, and then outputs through the fourth output node A. N The fourth output signal AN is output. The second inverter pair includes the eleventh PMOS transistor MP11 and the thirteenth NMOS transistor MN13; the gate of the eleventh PMOS transistor MP11 is connected to the first output node A. PThe source of the thirteenth NMOS transistor MN13 is connected to the power supply terminal VDD; the source of MN13 is grounded, and the gate is connected to the first output node A. P The drain is connected to the drain of the eleventh PMOS transistor MP11, and then output to the third output node A. P Output the third output signal AP.

[0014] According to embodiments of this disclosure, the latch further includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor MN15.

[0015] The gate of the fifth PMOS transistor MP5 is connected to the fourth output node A. N The source is connected to the power supply terminal, and the drain terminal is provided with a first discharge node A.

[0016] The gate of the sixth PMOS transistor MP6 is connected to the fourth output node A. N The source is connected to the power supply terminal, and the drain is connected to the fifth output node VOUTN;

[0017] The gate of the fourteenth NMOS transistor MN14 is connected to the fourth output node A. N The drain is connected to the first discharge node A, and the source is grounded.

[0018] The gate of the tenth PMOS transistor MP10 is connected to the third output node A. P The source is connected to the power supply terminal, and the drain terminal is provided with a second discharge node B.

[0019] The gate of the ninth PMOS transistor MP9 is connected to the third output node A. P The source is connected to the power supply terminal, and the drain is connected to the sixth output node VOUTP.

[0020] The gate of the fifteenth NMOS transistor MN15 is connected to the third output node A. P The drain is connected to the second discharge node B, and the source is grounded.

[0021] According to embodiments of this disclosure, the latch further includes: a third inverter pair and a fourth inverter pair.

[0022] The third inverter pair includes a seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11. The source of the seventh PMOS transistor MP7 is connected to the power supply terminal, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP. The source of the eleventh NMOS transistor MN11 is connected to the first discharge node A, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP. The fourth inverter pair includes an eighth PMOS transistor MP8 and a twelfth NMOS transistor MN12. The source of the eighth PMOS transistor MP8 is connected to the power supply terminal, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN. The source of the twelfth NMOS transistor MN12 is connected to the second discharge node B, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN.

[0023] (III) Beneficial Effects

[0024] As can be seen from the above technical solution, the six-input dynamic comparator of this disclosure has at least one or a part of the following beneficial effects:

[0025] (1) Reduced kickback noise;

[0026] (2) It achieves amplification gain, reduces the offset voltage of the second-stage latch equivalent to the input, and reduces the equivalent input noise.

[0027] (3) Only one external clock CLK is needed. This structure reduces clock error and reduces the load on CLK.

[0028] (4) By setting different width-to-length ratios, the six core input transistors achieve different amplification factors for different signal paths;

[0029] (5) Fast latching is achieved. Attached Figure Description

[0030] Figure 1 This is a schematic diagram illustrating the composition and principle of a six-input dynamic comparator according to an embodiment of the present disclosure;

[0031] Figure 2 This is a schematic diagram of the time-domain response of a dynamic comparator;

[0032] Figure 3 This is a schematic diagram of the circuit structure of a six-input dynamic comparator according to an embodiment of the present disclosure;

[0033] Figure 4 This is a schematic diagram of the circuit structure of a multi-input dynamic amplifier for a six-input dynamic comparator according to an embodiment of the present disclosure;

[0034] Figure 5This is a schematic diagram of the circuit structure of the latch of the six-input dynamic comparator according to an embodiment of the present disclosure;

[0035] Figure 6 This is a schematic diagram of the transient simulation waveform of the six-input dynamic comparator according to an embodiment of the present disclosure;

[0036] Figure 7 This is a simulation diagram of the equivalent input noise of a six-input dynamic comparator according to an embodiment of the present disclosure;

[0037] Figure 8 This is a simulation diagram of the offset voltage of a six-input dynamic comparator according to an embodiment of the present disclosure.

[0038] Figure 9a This is a schematic diagram comparing the kickback noise voltage of a six-input dynamic comparator according to an embodiment of the present disclosure with that of a conventional dual-tailed current-type comparator under normal temperature (300K).

[0039] Figure 9b This is a schematic diagram comparing the kickback noise voltage of a six-input dynamic comparator according to an embodiment of this disclosure with that of a conventional dual-tailed current-type comparator at a low temperature of 4.2K. Detailed Implementation

[0040] This disclosure provides a six-input dynamic comparator that solves the design problem of multi-input comparator circuits in cascaded integrator-type feedforward noise-shaping successive approximation ADCs by cascading a pre-stage dynamic amplifier and a secondary latch circuit. It can realize six input voltage signals, reducing offset voltage and kickback noise while ensuring fast comparison speed. Furthermore, this six-input dynamic comparator can operate at extremely low temperatures (4.2K) to amplify signals and compare multiple input voltages, while reducing input offset voltage and achieving low kickback noise, thus meeting the requirements of high precision and high resolution.

[0041] In developing this disclosure, the inventors discovered that a multi-input comparator requires amplifying and comparing six input signals from a capacitor DAC: the differential residual voltage signals Vres+ and Vres-, the first-order residual integral signals Vint1+ and Vint1-, and the second-order residual integral signals Vint2+ and Vint2-. Typically, Vres+ and Vres- are not amplified according to actual needs, while the first-order residual integral signals Vint1+ and Vint1-, and the second-order residual integral signals Vint2+ and Vint2-, require amplification factors of k times and m times, respectively. Then, the six signals are added and compared. Open-loop comparators lack feedback loops and have high power consumption. For low-power design requirements, dynamic latch comparators are needed, whose basic principle is amplification and positive feedback. Traditional StrongArm dynamic comparators cannot operate at advanced process nodes (lower power supply voltages) because the latch structure has a large input offset voltage V. offsetThis results in a relatively large equivalent input offset voltage for the comparator. Simultaneously, the rail-to-rail voltage variation at the input transistor drain introduces significant kickback noise. In high-resolution scenarios, input differences in the µV range may lead to bit errors and metastability issues. Dual-tailed current-type dynamic comparators separate the gain stage and latch stage, but at the cost of increased current consumption and additional power consumption. They also require an additional CLKB clock, which is inversely proportional to CLK, necessitating precise timing for both CLK and CLKB. Implementing CLKB using an inverter introduces a significant capacitive load on CLK. Both dual-tailed current-type and Elzakker-type dynamic comparators, due to the presence of gate-drain capacitance in the input transistors, cause drain voltage variations to couple to the input, resulting in significant kickback noise. Therefore, this disclosure provides a superior, low-kickback-noise six-input dynamic comparator suitable for extremely low temperatures.

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0043] In this embodiment of the disclosure, a six-input dynamic comparator is provided, combined with Figure 1 , Figures 3-5 As shown, the six-input dynamic comparator includes: a dynamic amplifier and a latch connected in sequence;

[0044] The dynamic amplifier, as an amplification stage, includes: a positive input unit, a negative input unit, a clock unit, and an output unit.

[0045] The positive input unit includes: a first positive input terminal Vp1, used to input a first positive input signal Vip; a second positive input terminal Vp2, used to input a second positive input signal Vint1p; and a third positive input terminal Vp3, used to input a third positive input signal Vint2p.

[0046] The negative input unit includes: a first negative input terminal Vn1, used to input a first negative input signal Vin; a second negative input terminal Vn2, used to input a second negative input signal Vintln; and a third negative input terminal Vn3, used to input a third negative input signal Vint2n.

[0047] The clock unit is used to emit a square wave clock signal CLK;

[0048] The output unit includes: a first output node A P Second output node A N The dynamic amplifier is used to sum and amplify six input signals, and is output from the first output node A. P Second output node A N Output the first output signal AP and the second output signal AN respectively;

[0049] The latch, as a latching stage, amplifies and inverts the first and second output signals to obtain the third output signal AP′ and the fourth output signal AN′, respectively, and discharges the signal based on the magnitudes of the third and fourth output signals to obtain the final output signals Voutp and Voutn.

[0050] According to an embodiment of this disclosure, the dynamic amplifier further includes a footer transistor unit, which includes a first footer transistor MN7 and a second footer transistor MN8; wherein the gates of the first footer transistor MN7 and the second footer transistor MN8 are commonly connected to a clock unit, and the drain of the first footer transistor MN7 is connected to a second output node A. N The drain of the second footer tube MN8 is connected to the first output node A. P .

[0051] According to an embodiment of this disclosure, the positive input unit further includes: a first core input transistor MN1 and a first capacitor MN1′ whose gates are both connected to the first positive input terminal Vp1; a second core input transistor MN2 and a second capacitor MN2′ whose gates are both connected to the second positive input terminal Vp2; and a third core input transistor MN3 and a third capacitor MN3′ whose gates are both connected to the third positive input terminal Vp3; wherein, the drains of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3 are respectively connected to the source of the first footer transistor MN7, and the source and drain of the first capacitor MN1′, the second capacitor MN2′, and the third capacitor MN3′ are short-circuited and then respectively connected to the source of the second footer transistor MN8, and the width-to-length ratio of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3 is 1:k:m, where k and m represent amplification factors, and k and m are integers.

[0052] According to an embodiment of this disclosure, the negative input unit further includes: a fourth core input transistor MN4 and a fourth capacitor MN4′ whose gates are all connected to the first negative input terminal Vn1; a fifth core input transistor MN5 and a fifth capacitor MN5′ whose gates are all connected to the second negative input terminal Vn2; and a sixth core input transistor MN6 and a sixth capacitor MN6′ whose gates are all connected to the third negative input terminal Vn3. The drains of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 are respectively connected to the source of the second footer transistor MN8. The sources and drains of the fourth capacitor MN4′, the fifth capacitor MN5′, and the sixth capacitor MN6′ are short-circuited and then connected to the source of the first footer transistor MN7. The width-to-length ratio of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 is 1:k:m, where k and m represent amplification coefficients. k and m are integers, but it should be noted that k and m can also be non-integers. The specific values ​​are adjusted according to the actual application.

[0053] According to an embodiment of this disclosure, the dynamic amplifier further includes: a first reset transistor MP1, the drain of which is connected to the second output node A. N The source of the second reset transistor (MP2) is connected to the power supply terminal VDD; the drain of MP2 is connected to the first output node A. P The source of the first reset transistor MP2 is connected to the power supply terminal VDD. The gate of the second reset transistor MP2 and the gate of the first reset transistor MP1 are connected to the clock unit. The source of the third reset transistor MP3 is connected to the source of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3. The drain of the third reset transistor MP3 is connected to the power supply terminal VDD. The drain of the wake transistor MN9 is connected to the source of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 and is connected to the source of the third reset transistor MP3. The source of the wake transistor MN9 is grounded. The gate of the wake transistor MN9 and the gate of the third reset transistor MP3 are connected to the clock unit.

[0054] According to an embodiment of this disclosure, the dynamic amplifier further includes: a first capacitor C1, one end of which is connected to the second output node A. N One end is grounded; and the other end is a second capacitor C2, one end of which is connected to the first output node A. P The other end is grounded.

[0055] According to an embodiment of this disclosure, the latch includes: a first inverter pair and a second inverter pair.

[0056] The first inverter is paired with the second output node A. N Connected to the first output node A, it amplifies and inverts the second output signal AN to obtain the fourth output signal AN′; the second inverter is connected to the first output node A. PConnected, it is used to amplify and invert the first output signal AP to obtain the third output signal AP′.

[0057] According to an embodiment of this disclosure, the first inverter pair includes: a fourth PMOS transistor MP4, whose gate is connected to a second output node A. N Connected, with its source connected to the power supply terminal VDD; the tenth NMOS transistor MN10 has its source grounded and its gate connected to the first output node A. P The drain is connected to the drain of the fourth PMOS transistor MP4, and then outputs through the fourth output node A. N Output the fourth output signal AN.

[0058] The second inverter pair includes: the eleventh PMOS transistor MP11, whose gate is connected to the first output node A. P Connected, with its source connected to the power supply terminal VDD; the thirteenth NMOS transistor MN13 has its source grounded and its gate connected to the first output node A. P The drain is connected to the drain of the eleventh PMOS transistor MP11, and then output to the third output node A. P Output the third output signal AP.

[0059] According to an embodiment of this disclosure, the capacitance value CL of the first capacitor C1 is the first output node A. P The gate capacitance value of the fourth PMOS transistor MP4 in the connected latch, and the capacitance value CL+ΔC of the second capacitor C2 are the gate capacitance value of the tenth NMOS transistor MN10 in the latch. The closer ΔC is to zero, the better, reflecting the capacitance difference caused by the process difference between the tenth NMOS transistor MN10 and the fourth PMOS transistor MP4.

[0060] According to an embodiment of this disclosure, the latch further includes: a fifth PMOS transistor MP5, the gate of which is connected to the fourth output node A. N The source of the PMOS transistor is connected to the power supply terminal, and the drain terminal is provided with the first discharge node A; the sixth PMOS transistor, MP6, has its gate connected to the fourth output node A. N The source of the fourteenth NMOS transistor MN14 is connected to the power supply terminal, and the drain is connected to the fifth output node VOUTN; the gate of the fourteenth NMOS transistor MN14 is connected to the fourth output node A. N The drain of the tenth PMOS transistor (MP10) is connected to the first discharge node A, and its source is grounded. The gate of the tenth PMOS transistor (MP10) is connected to the third output node A. P The source of the PMOS transistor is connected to the power supply terminal, and the drain terminal is provided with a second discharge node B; the ninth PMOS transistor MP9 has its gate connected to the third output node A. P The source of the NMOS transistor is connected to the power supply, and the drain is connected to the sixth output node VOUTP; the gate of the fifteenth NMOS transistor MN15 is connected to the third output node A. P The drain is connected to the second discharge node B, and the source is grounded.

[0061] According to an embodiment of this disclosure, the latch further includes: a third inverter pair, comprising a seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11, wherein the source of the seventh PMOS transistor MP7 is connected to a power supply terminal, its drain is connected to a fifth output node VOUTN, and its gate is connected to a sixth output node VOUTP; the source of the eleventh NMOS transistor MN11 is connected to a first discharge node A, its drain is connected to a fifth output node VOUTN, and its gate is connected to a sixth output node VOUTP; and a fourth inverter pair, comprising an eighth PMOS transistor MP8 and a twelfth NMOS transistor MN12, wherein the source of the eighth PMOS transistor MP8 is connected to a power supply terminal, its drain is connected to a sixth output node VOUTP, and its gate is connected to a fifth output node VOUTN; the source of the twelfth NMOS transistor MN12 is connected to a second discharge node B, its drain is connected to a sixth output node VOUTP, and its gate is connected to a fifth output node VOUTN. Finally, the final output signals Voutn and Voutp are output through the fifth output node VOUTN and the sixth output node VOUTP, respectively.

[0062] More specifically, such as Figure 1 The six-input dynamic comparator shown consists of a first-stage dynamic amplifier and a second-stage latch. It implements the comparison and fast latching functions of six input signals under power supply and a square wave clock signal CLK with a duty cycle of 50%.

[0063] Figure 2 This is a schematic diagram of the time-domain response of a dynamic comparator; for example... Figure 2 As shown, open-loop amplifiers have high gain but low bandwidth, resulting in longer settling times t1 for high and low levels. Assuming a single-pole amplifier has a gain of A, a settling time of τ, and a dominant pole frequency of p(ω), then... GBW is the gain-bandwidth product, GBW = A*p(ω). The amplification speed of the latch signal increases exponentially with time. The larger the initial signal, the faster the comparator latches (e.g., t2). The input signal is first rapidly amplified to a certain value by an open-loop comparator, and then used as the input of the latch comparator for positive feedback amplification, thus obtaining the comparison result quickly.

[0064] Figure 3This is a schematic diagram of the circuit structure of a six-input dynamic comparator according to an embodiment of the present disclosure. The circuit of the six-input dynamic comparator includes a first-stage dynamic amplifier and a second-stage latch. The first-stage dynamic amplifier requires a CLK clock signal and uses six core input transistors MN1, MN4, MN2, MN5, MN3, and MN6, whose width-to-length ratio is 1:1:k:k:m:m, where k and m represent the amplification factor. Simultaneously, six cross-coupled transistors MN1', MN4', MN2', MN5', MN3', and MN6' are used to reduce kickback noise; their width-to-length ratio is 3 / 5 of the corresponding core input transistor. This complementary cross-coupling method achieves lower kickback noise. It also implements the summation and amplification function of the six input signals. The second stage is the latch stage. During the comparison stage, two inverters, MN10, MN13, MP4, and MP11, further amplify the signal amplified by the first stage, increasing the gain. Simultaneously, MN14, MN15 and two back-to-back inverters MN11, MN12, MP7, and MP8 are used to achieve the functions of comparing voltage signal magnitudes and fast latching.

[0065] Figure 4 This is a schematic diagram of the circuit structure of a multi-input dynamic amplifier based on a six-input dynamic comparator according to an embodiment of this disclosure. The sampling differential pair structure reduces input common-mode interference and suppresses common-mode noise. MN1, MN2, MN3, MN4, MN5, and MN6 are core input transistors, and MN1', MN2', MN3', MN4', MN5', and MN6' are source-drain shorted capacitors. The width-to-length ratio of these capacitors is 3 / 5 of the corresponding core input transistor, and kickback noise is reduced through cross-coupling. Output node A N A N A footer pair of transistors MN7 and MN8 is added below to increase the overdrive voltage of the input transistors, which can reduce kickback noise. The core input transistors MN1, MN2, MN3, MN4, MN5, and MN6 convert the voltage of the six input signals to current, and achieve dynamic amplification when CLK is high.

[0066] Figure 5 This is a schematic diagram of the circuit structure of the latch of the six-input dynamic comparator according to an embodiment of the present disclosure; compared with the traditional two-stage dynamic comparator, MP4, MN10 and MP11, MN10 are used as inverter pairs to respectively convert A N A N The signals AN and AP emitted by the node are amplified into inverted signals AN' and AP', and then further amplified and transmitted to the output latch stage using MP6, MN14, MP9, and MN15. This achieves a relatively high amplification gain, reduces the offset voltage of the second-stage latch equivalent to the input, and also reduces the equivalent input noise.

[0067] The working principle is as follows:

[0068] Reset stage: When CLK is at low level (GND), MP1, MP2, and MP3 are turned on. MP1 and MP2 set the first output node A P and the second output node A N to VDD. The footer transistors MN7 and MN8 are turned off. By turning on MP3, the sources of the input transistors MN1, MN2, MN3, MN4, MN5, and MN6 are connected to VDD, achieving fast turn-off of the input transistors and accelerating the comparison speed. The first output node A P and the second output node A N are charged to the high level VDD. The third output node A P ' and the fourth output node A N ' become low level GND. MP5, MP6, MP9, and MP10 are turned on, pulling the signals of the fifth output node VOUTN, the sixth output node VOUTP, the first discharge node A, and the second discharge node B to the high level VDD, realizing the reset function of the amplification stage and the Latch stage (latch stage).

[0069] Comparison stage: CLK is at high level. The reset transistors MP1, MP2, and MP3 are turned off, and MN7, MN8, and MN9 are turned on. The first output node A P and the second output node A N start discharging from VDD. The discharging speed depends on the amplitude of the input voltage. When A N or A P node drops to VDD - |V thp |, MP4 and MP11 are turned on. MP4, MN10, MP11, and MN13 act as an inverter pair to amplify the first output signal AP and the second output signal AN output from the A N and A P nodes into the reverse signals the third output signal AP' and the fourth output signal AN'. Then AN' and AP` are further amplified and transmitted to the output latch stage by MP6, MN14, MP9, and MN15. MN14 and MN15 are successively turned on according to the magnitudes of AN` and AP`, discharging the first discharge node A and the second discharge node B to GND,

[0070] Let AP,(t) be the voltage value of the third output node A P ', and AN'(t) be the voltage value of the fourth output node A N '. If AP`(t) < AN`(t), MN14 will be turned on first, and the first discharge node A will be discharged first. When the voltage of the first discharge node A is lower than (VDD - V thnIf MN11 is turned on first, the output node VOUTN is discharged. At the same time, through the positive feedback latches of MP7, MN11, MP8, and MN12, VOUTN is locked at the low level GND, and VOUTP is locked at the logic high level VDD. Conversely, if AP'(t) > AN`(t), VOUTN is locked at the high level VDD, and VOUTP is locked at the logic low level GND.

[0071] Considering that the preamplifier is the main contributor to noise, the noise generated by the latch can be ignored.

[0072] Then the equivalent input noise for

[0073]

[0074] Where A(t) is the magnification factor, C L Where C1 or C2 is the load capacitance, K is the Boltzmann constant, T is the temperature, γ is the thermal noise figure of the MOSFET, and g is the load capacitance of the capacitor. m t is the transconductance of the six core input transistors, and t is the dynamic amplification time.

[0075] A(t)=g m t / C L

[0076] t = 2C L ΔV / I b

[0077] Among them, g m It is the transconductance value of the six input transistors, ΔV is the voltage difference between the first output signal AP and the second output signal AN during the comparison stage, and I b This is the current value of the tail current transistor MN9.

[0078] Increasing the aspect ratio of the differential input pair can increase the amplification factor and reduce the equivalent input noise. Simultaneously, reducing the aspect ratio of the tail current transistor allows for a smaller source-drain current I of the tail current transistor MN9. b This achieves a longer dynamic amplification time t, further reducing input noise.

[0079] Compared to traditional dynamic comparators that require a clock signal CLK and a clock inversion signal CLKB, this new comparator only requires one external clock CLK. This structure reduces clock error and the load on CLK. The six core input transistors are configured with different aspect ratios (1:1:k:k:m:m), where k and m represent amplification factors, achieving different amplification factors for different signal paths. The introduction of footer transistors MN4 and MN5 reduces kickback noise and increases the overdrive voltage V of the input transistors. Gs -V THThe complementary use of six cross-coupled transistors further reduces the impact of kickback noise. The MP3 transistor speeds up the reset process during the reset phase. The signal amplified in the first stage is further amplified by the inverter and MP6, MN14, MP9, and MN15 in the second-stage latch, achieving a relatively high amplification gain, reducing the offset voltage equivalent to the input in the second-stage latch, and simultaneously decreasing the equivalent input noise. Fast latching is achieved through a back-to-back latch stage.

[0080] Using the Spectre simulation tool at a 180nm process node, with VDD = 1.8V and the clock signal frequency f... clk =1GHz, first output node A P Second output node A N The capacitance C of the connected load capacitors (C1, C2) L =500fF, simulations were performed at Temp = 27℃ and Temp = -269℃ respectively. The input common-mode voltage was Vcm = 0.9mV, where Vcm is the common-mode voltage of the input signal, a constant DC level to ensure normal operation of the MOSFET. The transient characteristics of the comparator were simulated using the Cadence cryogenic library at an input voltage Vp1-Vn1 = -50mV, and the waveform is shown below. Figure 6 As shown, it can be seen that each node of the comparator works normally during the clock reset and comparison phases, and can realize all the functions of the design. The transient noise simulation method is used at room temperature (Temp = 27℃) as follows: Figure 7 As shown, the X-axis ΔVin represents Vp1-Vn1, indicating the magnitude of the input differential voltage when Vp2, Vp3, Vn2, and Vn3 are equal to the common-mode voltage. The Y-axis P represents the probability of the comparator output being correct. It is found that when the input voltage difference is 400μV, the probability of the correct output signals at the output terminals VOUTP and VOUTN is 84%. Therefore, the standard deviation of the comparator noise is 400μV, and the noise power is the square of the standard deviation, which is 0.16μV. 2 At low temperatures, the transient noise decreases by approximately 1 / 71 of its original value due to the reduced temperature. Further Monte Carlo simulations are used to obtain the comparator's offset voltage, such as... Figure 8 As shown, the horizontal axis Values ​​represents the magnitude of the offset voltage, and the vertical axis represents the number of samples. It can be seen that the average offset voltage is 0.65mV and the standard deviation is 5.44mV. Figure 9a and Figure 9b Simulations of the kickback noise of the six-input dynamic comparator of this disclosure and a traditional dual-tailed current-type comparator are presented under two conditions: a low temperature of 4.2K and a normal temperature of 300K. Figure 9a and Figure 9bAs shown, the six-input dynamic comparator of this disclosure has lower kickback noise compared to conventional dual-tailed current-type comparators.

[0081] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0082] Based on the above description, those skilled in the art should have a clear understanding of the six-input dynamic comparator of this disclosure.

[0083] In summary, this disclosure provides a six-input dynamic comparator. The fabrication process used in this circuit has been tested, characterized, and modeled at extremely low temperatures, and the dynamic comparator circuit has also passed functional simulation verification in an extremely low temperature environment. Quantum computing readout systems require low-power, high-precision analog-to-digital converters to operate normally at extremely low temperatures. Cascaded integrator-feedforward noise-shaping successive approximation ADCs combine the advantages of DeltaSigma and SAR structures, and can significantly improve the signal-to-noise ratio by incorporating oversampling techniques. The core of this ADC structure is a low-power dynamic comparator, and there is an urgent need for a new multi-input comparator technology that can operate at extremely low temperatures while achieving low kickback noise. To address the above issues, a low-kickback-noise six-input dynamic comparator capable of operating at extremely low temperatures (4K) is designed. Compared to traditional dynamic comparators that require two clock signals, this new comparator only requires a single clock signal, reducing the requirement for clock accuracy. The complementary use of six cross-coupled transistors reduces the impact of kickback noise. By adding an inverter and an amplifying transistor in the second stage, a relatively high amplification gain was achieved, reducing the offset voltage equivalent to the input of the second-stage latch and decreasing the equivalent input noise. Its functionality and noise characteristics were simulated and verified based on an ultra-low temperature model library, while also achieving low power consumption.

[0084] It should also be noted that the above are different embodiments provided by this disclosure. These embodiments are used to illustrate the technical content of this disclosure and are not intended to limit the scope of protection of this disclosure. A feature of one embodiment can be applied to other embodiments through suitable modifications, substitutions, combinations, or separations.

[0085] It should be noted that, unless otherwise specified herein, having "a" element is not limited to having a single element, but may include one or more of the element.

[0086] Furthermore, unless otherwise specified, the ordinal numbers such as "first," "second," etc., used herein are merely for distinguishing multiple elements with the same name and do not indicate any hierarchy, order of execution, or process sequence among them. A "first" element and a "second" element may appear together in the same component or separately in different components. The presence of an element with a higher ordinal number does not necessarily indicate the presence of another element with a lower ordinal number.

[0087] In this document, unless otherwise specified, the term "characteristic A" or "and / or" and "characteristic B" means that A exists alone, B exists alone, or A and B exist simultaneously; the term "characteristic A" and "and" or "and" and "and" and "characteristic B" means that A and B exist simultaneously; the terms "including", "containing", "having", and "containing" refer to, but are not limited to, these.

[0088] Furthermore, in this document, terms such as "up," "down," "left," "right," "front," "back," or "between" are used only to describe the relative positions of multiple elements and can be extended to include translation, rotation, or mirroring. Additionally, unless otherwise specified, the statement "one element is on another element" or similar statements do not necessarily indicate that the element is in contact with the other element.

[0089] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0090] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A six-input dynamic comparator, comprising: A dynamic amplifier and a latch connected in sequence; The dynamic amplifier includes: Positive input unit, including: The first positive input terminal Vp1 is used to input the first positive input signal; The second positive input terminal Vp2 is used to input the second positive input signal; The third positive input terminal Vp3 is used to input the third positive input signal; The negative input unit includes: The first negative input terminal Vn1 is used to input the first negative input signal; The second negative input terminal Vn2 is used to input the second negative input signal; The third negative input terminal Vn3 is used to input the third negative input signal; The clock unit is used to emit a square wave clock signal CLK; The output unit includes: a first output node A P Second output node A N The dynamic amplifier is used to sum and amplify six input signals, and is output from the first output node A. P Second output node A N The first output signal AP and the second output signal AN are output respectively; and The footer transistor unit includes a first footer transistor MN7 and a second footer transistor MN8; wherein the gates of the first footer transistor MN7 and the second footer transistor MN8 are connected to the clock unit, and the drain of the first footer transistor MN7 is connected to the second output node A. N The drain of the second footer tube MN8 is connected to the first output node A. P ; The latch is used to amplify and invert the first output signal and the second output signal to obtain the third output signal AP′ and the fourth output signal AN′, respectively, and discharge the output signal based on the comparison of the magnitudes of the third output signal and the fourth output signal. The positive input unit further includes: a first core input transistor MN1 and a first capacitor MN1′, both with their gates connected to the first positive input terminal Vp1; a second core input transistor MN2 and a second capacitor MN2′, both with their gates connected to the second positive input terminal Vp2; and a third core input transistor MN3 and a third capacitor MN3′, both with their gates connected to the third positive input terminal Vp3. The drains of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3 are respectively connected to the source of the first footer transistor MN7. The sources and drains of the first capacitor MN1′, the second capacitor MN2′, and the third capacitor MN3′ are short-circuited and then connected to the source of the second footer transistor MN8. The width-to-length ratio of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3 is 1:k:m, where k and m represent amplification factors, and k and m are integers. The negative input unit further includes a fourth core input transistor MN4 and a fourth capacitor MN4′ whose gates are all connected to the first negative input terminal Vn1; a fifth core input transistor MN5 and a fifth capacitor MN5′ whose gates are all connected to the second negative input terminal Vn2; and a sixth core input transistor MN6 and a sixth capacitor MN6′ whose gates are all connected to the third negative input terminal Vn3. The drains of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 are respectively connected to the source of the second footer transistor MN8. The sources and drains of the fourth capacitor MN4′, the fifth capacitor MN5′, and the sixth capacitor MN6′ are short-circuited and then connected to the source of the first footer transistor MN7. The width-to-length ratio of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6 is 1:k:m, where k and m represent amplification factors, and k and m are integers.

2. The six-input dynamic comparator according to claim 1, wherein the dynamic amplifier further comprises: The drain of the first reset transistor MP1 is connected to the second output node A. N The source is connected to the power supply terminal VDD; The drain of the second reset transistor MP2 is connected to the first output node A. P The source is connected to the power supply terminal VDD, and the gate of the second reset transistor MP2 and the gate of the first reset transistor MP1 are connected to the clock unit. The source of the third reset transistor MP3 is connected to the source of the first core input transistor MN1, the second core input transistor MN2, and the third core input transistor MN3, and the drain of the third reset transistor MP3 is connected to the power supply terminal VDD. The drain of the stray transistor MN9 is connected to the source of the fourth core input transistor MN4, the fifth core input transistor MN5, and the sixth core input transistor MN6, and is also connected to the source of the third reset transistor MP3. The source of the stray transistor MN9 is grounded, and the gate of the stray transistor MN9 and the gate of the third reset transistor MP3 are connected to the clock unit.

3. The six-input dynamic comparator according to claim 1, further comprising: The first capacitor C1 is connected at one end to the second output node A. N The other end is grounded; as well as The second capacitor C2 is connected at one end to the first output node A. P The other end is grounded.

4. The six-input dynamic comparator according to claim 1, wherein the latch comprises: The first inverter pair, and the second output node A N Connected together, it is used to amplify and invert the second output signal AN to obtain the fourth output signal AN′; as well as The second inverter pair, with the first output node A P Connected, it is used to amplify and invert the first output signal AP to obtain the third output signal AP′.

5. The six-input dynamic comparator according to claim 4, wherein: The first inverter pair includes: The fourth PMOS transistor MP4 has its gate connected to the second output node A. N Connected, with the source terminal connected to the power supply terminal VDD; The tenth NMOS transistor MN10 has its source grounded and its gate connected to the first output node A. P The drain is connected to the drain of the fourth PMOS transistor MP4, and then outputs through the fourth output node A. N Output the fourth output signal AN. The second inverter pair includes: The eleventh PMOS transistor MP11, its gate is connected to the first output node A. P Connected, with the source terminal connected to the power supply terminal VDD; The thirteenth NMOS transistor MN13 has its source grounded and its gate connected to the first output node A. P The drain is connected to the drain of the eleventh PMOS transistor MP11, and then output to the third output node A. P Output the third output signal AP.

6. The six-input dynamic comparator according to claim 5, wherein the latch further comprises: The fifth PMOS transistor, MP5, has its gate connected to the fourth output node A. N The source is connected to the power supply terminal, and the drain terminal is provided with a first discharge node A. The sixth PMOS transistor, MP6, has its gate connected to the fourth output node A. N The source is connected to the power supply terminal, and the drain is connected to the fifth output node VOUTN; The fourteenth NMOS transistor MN14 has its gate connected to the fourth output node A. N The drain is connected to the first discharge node A, and the source is grounded. The tenth PMOS transistor, MP10, has its gate connected to the third output node A. P The source is connected to the power supply terminal, and the drain terminal is provided with a second discharge node B. The ninth PMOS transistor, MP9, has its gate connected to the third output node A. P The source is connected to the power supply terminal, and the drain is connected to the sixth output node VOUTP. The fifteenth NMOS transistor MN15 has its gate connected to the third output node A. P The drain is connected to the second discharge node B, and the source is grounded.

7. The six-input dynamic comparator according to claim 5, wherein the latch further comprises: The third inverter pair includes a seventh PMOS transistor MP7 and an eleventh NMOS transistor MN11. The source of the seventh PMOS transistor MP7 is connected to the power supply terminal, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP. The source of the eleventh NMOS transistor MN11 is connected to the first discharge node A, the drain is connected to the fifth output node VOUTN, and the gate is connected to the sixth output node VOUTP. The fourth inverter pair includes an eighth PMOS transistor MP8 and a twelfth NMOS transistor MN12. The source of the eighth PMOS transistor MP8 is connected to the power supply terminal, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN. The source of the twelfth NMOS transistor MN12 is connected to the second discharge node B, the drain is connected to the sixth output node VOUTP, and the gate is connected to the fifth output node VOUTN.

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