High-isolation T-type analog switch and control circuit thereof
By using a delay module and an inverting circuit to combine control signals in a T-type analog switch, the leakage problem caused by the non-simultaneous change of control signals is solved, achieving high isolation and low power consumption switching.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-16
- Publication Date
- 2026-04-07
AI Technical Summary
Existing high-isolation T-type analog switches are prone to leakage between power supply and channel or between channel and ground when the control signals CLK and CLK_B do not change simultaneously, which increases circuit power consumption and may damage the chip.
By using a combination of several delay modules and inverting circuits, the delay difference of the control signal of the MOSFET is controlled to avoid the MOSFET from closing or opening at the same time, thus preventing the formation of leakage paths.
It effectively avoids leakage current during the switching process, reduces dynamic power consumption, and lowers the risk of chip damage.
Smart Images
Figure CN115833810B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, specifically but not limited to a high-isolation T-type analog switch and its control circuit. Background Technology
[0002] Existing high-isolation T-type analog switches and their control circuits, such as Figure 1 , 2 As shown, ideally, the closing or opening of MOSFETs P1 and P2 should occur simultaneously with the opening or closing of MOSFET P3, and the closing or opening of MOSFETs N1 and N2 should occur simultaneously with the opening or closing of MOSFET N3. That is, control signals CLK and CLK_B should change simultaneously. However, since the loads corresponding to control signals CLK and CLK_B are different, and considering the influence of PVT (Process, Voltage, Temperature), control signals CLK and CLK_B may not change simultaneously; that is, the changes in control signals CLK and CLK_B may have a sequential relationship.
[0003] When, under certain circumstances, the change in control signal CLK precedes the change in control signal CLK_B, the timing diagrams for control signals CLK and CLK_B are as follows: Figure 3 As shown, the MOSFETs P1 and P2 are turned off later than the MOSFET P3 is turned on. At this time, the equivalent circuit of the PMOS portion of the T-type analog switch is as follows: Figure 4 As shown, a path will be formed between the power supply and the channel, causing leakage. When MOSFETs N1 and N2 close before MOSFET N3 opens, the equivalent circuit of the NMOS portion of the T-type analog switch is as follows: Figure 5 As shown, a path is formed between the channel and ground, causing leakage current from the channel to ground. Similarly, when the change in control signal CLK lags behind the change in control signal CLK_B, it will also cause leakage current from the power supply to the channel and leakage current from the channel to ground.
[0004] Leakage current not only increases circuit power consumption but can also damage chips. Therefore, a new structure or control method is needed to address at least some of these problems. Summary of the Invention
[0005] To address one or more problems in the prior art, this invention proposes a high-isolation T-type analog switch and its control circuit, wherein the control circuit alters the control signals of some MOSFETs in the T-type analog switch, thereby preventing leakage current during the switching process of the T-type analog switch.
[0006] The technical solution to achieve the purpose of this invention is as follows:
[0007] According to one aspect of the present invention, a control circuit for a high-isolation T-type analog switch includes several delay modules, several sets of inverting circuits, and an OR circuit, wherein:
[0008] The input of the first-stage delay module is coupled to the system's control signal, and the output is coupled to the input of the second-stage delay module and the input of the third set of inverting circuits. The output of the third set of inverting circuits is coupled to the first input of the OR circuit. The output of the OR circuit outputs a first control signal, and the first control signal outputs a second control signal after passing through the first set of inverting circuits.
[0009] The output of the second-stage delay module is coupled to the input of the third-stage delay module and the input of the fourth inverting circuit, respectively; the output of the third-stage delay module is coupled to the input of the second inverting circuit, and the output of the third-stage delay module outputs a third control signal; the second inverting circuit is coupled to the second input of the OR circuit; the output of the fourth inverting circuit outputs a fourth control signal.
[0010] Furthermore, in the control circuit of the high isolation T-type analog switch of the present invention, the first-stage delay module, the second-stage delay module, and the third-stage delay module each include 2n inverters, and the 2n inverters are connected in series in sequence, where n is a positive integer.
[0011] Furthermore, in the control circuit of the high isolation T-type analog switch of the present invention, the first group of inverter circuits, the second group of inverter circuits, the third group of inverter circuits, and the fourth group of inverter circuits each include 2m-1 inverters, and the 2m-1 inverters are connected in series in sequence, where m is a positive integer.
[0012] Furthermore, the control circuit of the high isolation T-type analog switch of the present invention includes a fifth set of inverting circuits, wherein the third control signal is output as a fifth control signal after passing through the second set of inverting circuits, and the fourth control signal is output as a sixth control signal after passing through the fifth set of inverting circuits.
[0013] Furthermore, in the control circuit of the high isolation T-type analog switch of the present invention, the fifth group of inverter circuits includes 2p-1 inverters, which are connected in series in sequence, where p is a positive integer.
[0014] According to another aspect of the present invention, a high-isolation T-type analog switch includes any of the above-described control circuits and a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein:
[0015] The source of the first PMOS transistor and the source of the first NMOS transistor are used together as the input terminal, and the source of the second PMOS transistor and the source of the second NMOS transistor are used together as the output terminal.
[0016] The drains of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the third control signal of the control circuit. The source of the third PMOS transistor is coupled to the power supply voltage, and the gate of the third PMOS transistor is connected to the first control signal of the control circuit.
[0017] The drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected together. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the fourth control signal of the control circuit. The source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to the second control signal of the control circuit.
[0018] According to another aspect of the present invention, a high-isolation T-type analog switch includes any of the above-described control circuits and a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein:
[0019] The source and drain of the fourth PMOS transistor are shorted together, the source and drain of the fifth PMOS transistor are shorted together, the source and drain of the fourth NMOS transistor are shorted together, and the source and drain of the fifth NMOS transistor are shorted together; the source of the first PMOS transistor, the source of the fourth PMOS transistor, the source of the first NMOS transistor, and the source of the fourth NMOS transistor together serve as the input terminal, and the source of the second PMOS transistor, the source of the fifth PMOS transistor, the source of the second NMOS transistor, and the source of the fifth NMOS transistor together serve as the output terminal;
[0020] The drains of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together; the gates of the first PMOS transistor and the second PMOS transistor are both connected to the third control signal of the control circuit, and the gates of the fourth PMOS transistor and the fifth PMOS transistor are both connected to the fifth control signal of the control circuit; the source of the third PMOS transistor is coupled to the power supply voltage, and the gate of the third PMOS transistor is connected to the first control signal of the control circuit.
[0021] The drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected together; the gates of the first NMOS transistor and the second NMOS transistor are both connected to the fourth control signal of the control circuit, and the gates of the fourth NMOS transistor and the fifth NMOS transistor are both connected to the sixth control signal of the control circuit; the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to the second control signal of the control circuit.
[0022] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:
[0023] 1. The control circuit of the high isolation T-type analog switch of the present invention, through the delay effect of the inverter, prevents the MOS transistors in the T-type isolation switch from closing simultaneously during the switching process, thereby avoiding the existence of a path between the power supply and the output, or between the ground and the output, and avoiding the impact on the output signal.
[0024] 2. The control circuit of the high isolation T-type analog switch of the present invention avoids power leakage to the input / output or input / output to ground during the switching process, thereby reducing dynamic power consumption and reducing the risk of chip damage. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 A schematic diagram of a prior art high-isolation T-type analog switch is shown.
[0027] Figure 2 A schematic diagram of the control circuit for a prior art high-isolation T-type analog switch is shown.
[0028] Figure 3 A timing diagram is shown for a prior art high-isolation T-type analog switch, where the change in control signal CLK precedes the change in control signal CLK_B.
[0029] Figure 4 A schematic diagram of the PMOS portion of a prior art high-isolation T-type analog switch is shown.
[0030] Figure 5 A schematic diagram of the NMOS equivalent circuit of a prior art high-isolation T-type analog switch is shown.
[0031] Figure 6 A circuit diagram of a high-isolation T-type analog switch according to an embodiment of the present invention is shown.
[0032] Figure 7 A schematic diagram of the control circuit for a high-isolation T-type analog switch according to an embodiment of the present invention is shown.
[0033] Figure 8 The control signal timing diagram of the control circuit of a high isolation T-type analog switch according to an embodiment of the present invention is shown.
[0034] Figure 9 A circuit diagram of a high-isolation T-type analog switch according to another embodiment of the present invention is shown.
[0035] Figure 10 A schematic diagram of the control circuit for a high-isolation T-type analog switch according to another embodiment of the present invention is shown.
[0036] Figure 11 A timing diagram of the control signals for a control circuit of a high-isolation T-type analog switch according to another embodiment of the present invention is shown. Detailed Implementation
[0037] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.
[0038] The description in this section pertains only to typical embodiments, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of similar or identical prior art with some technical features in the embodiments are also within the scope of the description and protection of the present invention.
[0039] Example 1:
[0040] A control circuit for a high-isolation T-type analog switch, such as Figure 7 As shown, it includes several stages of delay modules, several sets of inverting circuits, and an OR circuit. Among them:
[0041] The input of the first-stage delay module is coupled to the system's control signal CS, and its output is coupled to the input of the second-stage delay module and the input of the third set of inverter circuits. The output of the third set of inverter circuits is coupled to the first input of the OR circuit. The output of the OR circuit outputs a first control signal CLK1_B, which, after passing through the first set of inverter circuits, outputs a second control signal CLK1. Preferably, the first-stage delay module includes inverters INV1 and INV2, which are connected in series. More preferably, the first set of inverter circuits includes inverter INV10, and the third set of inverter circuits includes inverter INV9.
[0042] The output of the second-stage delay module is coupled to the input of the third-stage delay module and the input of the fourth set of inverter circuits. Preferably, the second-stage delay module includes inverters INV3 and INV4, which are connected in series.
[0043] The output of the third-stage delay module is coupled to the input of the second set of inverting circuits. The output of the third-stage delay module outputs a third control signal CLK_B. The second set of inverting circuits is coupled to the second input of the OR circuit. Preferably, the third-stage delay module includes inverters INV5 and INV6, which are connected in series. More preferably, the second set of inverting circuits includes inverter INV7.
[0044] The output of the fourth inverting circuit outputs the fourth control signal CLK. Preferably, the fourth inverting circuit includes an inverter INV8.
[0045] A high-isolation T-type analog switch, such as Figure 6 As shown, it includes the aforementioned control circuit, as well as a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3. Wherein:
[0046] The source of the first PMOS transistor P1 and the source of the first NMOS transistor N1 are used together as the input terminal, and the source of the second PMOS transistor P2 and the source of the second NMOS transistor N2 are used together as the output terminal.
[0047] The drains of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are connected. The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the third control signal CLK_B of the control circuit. The source of the third PMOS transistor P3 is coupled to the power supply voltage, and the gate of the third PMOS transistor P3 is connected to the first control signal CLK1_B of the control circuit.
[0048] The drains of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are connected. The gates of the first NMOS transistor N1 and the second NMOS transistor N2 are both connected to the fourth control signal CLK of the control circuit. The source of the third NMOS transistor N3 is grounded, and the gate of the third NMOS transistor N3 is connected to the second control signal CLK1 of the control circuit.
[0049] Based on the control circuit of the high-isolation T-type analog switch described above, the following can be achieved: the closing of the first PMOS transistor P1 and the second PMOS transistor P2 is later than the opening of the third PMOS transistor P3, while the opening of the first PMOS transistor P1 and the second PMOS transistor P2 is earlier than the closing of the third PMOS transistor P3; the closing of the first NMOS transistor N1 and the second NMOS transistor N2 is later than the opening of the third NMOS transistor N3, while the opening of the first NMOS transistor N1 and the second NMOS transistor N2 is earlier than the closing of the third NMOS transistor N3. The timing diagrams of the first control signal CLK1_B, the second control signal CLK1, the third control signal CLK_B, and the fourth control signal CLK output by the control circuit of the high-isolation T-type analog switch are as follows: Figure 8 As shown.
[0050] Assuming the control signal CS at the input of inverter INV1 is 0, the input IN and output OUT of this channel are connected, that is, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 are closed, and the third PMOS transistor P3 and the third NMOS transistor N3 are open; when the control signal CS is 0, this channel is open, that is, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 are open, and the third PMOS transistor P3 and the third NMOS transistor N3 are closed.
[0051] When the system input control signal CS changes from 0 to 1, such as Figure 7-8 As shown, the output A of inverter INV2 changes from 0 to 1, and then splits into two branches to transmit to inverters INV3 and INV9 respectively. Due to the large delay of the second-stage delay module, when one input B of the OR circuit changes from 1 to 0, the other input remains 1, so its output will remain unchanged at 1. Only when the output of inverter INV7 also becomes 0, the output of the OR circuit, i.e., the first control signal CLK1_B, becomes 0. Therefore, the changes of the fourth control signal CLK and the third control signal CLK_B occur earlier than the changes of the second control signal CLK1 and the first control signal CLK1_B. After passing through inverter INV10, the second control signal CLK1 becomes 1. Thus, the disconnection of the first PMOS transistor P1 and the second PMOS transistor P2 occurs earlier than the closing of the third PMOS transistor P3, and the disconnection of the first NMOS transistor N1 and the second NMOS transistor N2 occurs earlier than the closing of the third NMOS transistor N3.
[0052] When the system input control signal CS changes from 1 to 0, such as Figure 7-8As shown, the output A of inverter INV2 changes from 1 to 0, and then splits into two branches to transmit the data to inverters INV3 and INV9 respectively. When one input B of the OR gate becomes 1, its output will quickly change from 0 to 1 as well. However, the change in A requires a delay of several inverters before it reaches the fourth control signal CLK and the third control signal CLK_B. Therefore, the changes in the second control signal CLK1 and the first control signal CLK1_B occur earlier than the changes in the fourth control signal CLK and the third control signal CLK_B. Thus, the closing of the first PMOS transistor P1 and the second PMOS transistor P2 occurs later than the opening of the third PMOS transistor P3, and the closing of the first NMOS transistor N1 and the second NMOS transistor N2 occurs later than the opening of the third NMOS transistor N3.
[0053] In summary, the control circuit of this scheme allows the closing of the first PMOS transistor P1 and the second PMOS transistor P2 to be later than the opening of the third PMOS transistor P3, while the opening of the first PMOS transistor P1 and the second PMOS transistor P2 to be earlier than the closing of the third PMOS transistor P3; the closing of the first NMOS transistor N1 and the second NMOS transistor N2 to be later than the opening of the third NMOS transistor N3, while the opening of the first NMOS transistor N1 and the second NMOS transistor N2 to be earlier than the closing of the third NMOS transistor N3, thereby avoiding leakage during circuit switching.
[0054] Example 2:
[0055] A control circuit for a high-isolation T-type analog switch, such as Figure 10 As shown, it includes several stages of delay modules, several sets of inverting circuits, and an OR circuit. Among them:
[0056] The input of the first-stage delay module is coupled to the system's control signal CS, and its output is coupled to the input of the second-stage delay module and the input of the third set of inverter circuits. The output of the third set of inverter circuits is coupled to the first input of the OR circuit. The output of the OR circuit outputs a first control signal CLK1_B, which, after passing through the first set of inverter circuits, outputs a second control signal CLK1. Preferably, the first-stage delay module includes inverters INV1 and INV2, which are connected in series. More preferably, the first set of inverter circuits includes inverter INV10, and the third set of inverter circuits includes inverter INV9.
[0057] The output of the second-stage delay module is coupled to the input of the third-stage delay module and the input of the fourth set of inverter circuits. Preferably, the second-stage delay module includes inverters INV3 and INV4, which are connected in series.
[0058] The output of the third-stage delay module is coupled to the input of the second inverting circuit. The output of the third-stage delay module outputs a third control signal CLK_B. The second inverting circuit is coupled to the second input of an OR circuit. After passing through the second inverting circuit, the third control signal CLK_B outputs a fifth control signal CLK2_B. Preferably, the third-stage delay module includes inverters INV5 and INV6, which are connected in series. More preferably, the second inverting circuit includes inverter INV7.
[0059] The output of the fourth inverting circuit outputs a fourth control signal CLK. The fourth control signal CLK, after passing through the fifth inverting circuit, outputs a sixth control signal CLK2. Preferably, the fourth inverting circuit includes an inverter INV8. More preferably, the fifth inverting circuit includes an inverter INV11.
[0060] A high-isolation T-type analog switch, such as Figure 9 As shown, the circuit includes the aforementioned control circuit, as well as a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. Wherein:
[0061] The source and drain of the fourth PMOS transistor P4 are shorted, the source and drain of the fifth PMOS transistor P5 are shorted, the source and drain of the fourth NMOS transistor N4 are shorted, and the source and drain of the fifth NMOS transistor N5 are shorted. The sources of the first PMOS transistor P1, the fourth PMOS transistor P4, the first NMOS transistor N1, and the fourth NMOS transistor N4 are used together as the input terminals, and the sources of the second PMOS transistor P2, the fifth PMOS transistor P5, the second NMOS transistor N2, and the fifth NMOS transistor N5 are used together as the output terminals.
[0062] The drains of the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 are connected together; the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the third control signal CLK_B of the control circuit, and the gates of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both connected to the fifth control signal CLK2_B of the control circuit; the source of the third PMOS transistor P3 is coupled to the power supply voltage, and the gate of the third PMOS transistor P3 is connected to the first control signal CLK1_B of the control circuit.
[0063] The drains of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are connected together; the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are both connected to the fourth control signal CLK of the control circuit, and the gates of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are both connected to the sixth control signal CLK2 of the control circuit; the source of the third NMOS transistor N3 is grounded, and the gate of the third NMOS transistor N3 is connected to the second control signal CLK1 of the control circuit.
[0064] Based on the control circuit of the high-isolation T-type analog switch described above, the charge injection of the high-isolation analog switch can be reduced. The timing diagrams of its output first control signal CLK1_B, second control signal CLK1, third control signal CLK_B, fourth control signal CLK, fifth control signal CLK2_B, and sixth control signal CLK2 are as follows: Figure 11 As shown.
[0065] The working principle of its control circuit is the same as that of Implementation Case 1, and will not be repeated here.
[0066] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. The effects or advantages described in the specification may not be apparent in actual experimental cases due to uncertainties in specific conditions or other factors, and such descriptions are not intended to limit the scope of the invention. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be understood by those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.
Claims
1. A control circuit for a high-isolation T-type analog switch, characterized in that, It includes several delay modules, several sets of inverting circuits, and an OR circuit, wherein: The input of the first-stage delay module is coupled to the system's control signal, and the output is coupled to the input of the second-stage delay module and the input of the third set of inverting circuits. The output of the third set of inverting circuits is coupled to the first input of the OR circuit. The output of the OR circuit outputs a first control signal, and the first control signal outputs a second control signal after passing through the first set of inverting circuits. The output of the second-stage delay module is coupled to the input of the third-stage delay module and the input of the fourth inverting circuit, respectively; the output of the third-stage delay module is coupled to the input of the second inverting circuit, and the output of the third-stage delay module outputs a third control signal; the second inverting circuit is coupled to the second input of the OR circuit; the output of the fourth inverting circuit outputs a fourth control signal.
2. The control circuit for the high isolation T-type analog switch according to claim 1, characterized in that, The first-level delay module, the second-level delay module, and the third-level delay module each include 2n inverters, and the 2n inverters in each delay module are connected in series in sequence, where n is a positive integer.
3. The control circuit for the high isolation T-type analog switch according to claim 1, characterized in that, The first, second, third, and fourth inverting circuits each include 2m-1 inverters, and the 2m-1 inverters in each inverting circuit are connected in series, where m is a positive integer.
4. The control circuit for the high isolation T-type analog switch according to any one of claims 1-3, characterized in that, It includes a fifth set of inverting circuits, wherein the third control signal is output as the fifth control signal after passing through the second set of inverting circuits, and the fourth control signal is output as the sixth control signal after passing through the fifth set of inverting circuits.
5. The control circuit for the high isolation T-type analog switch according to claim 4, characterized in that, The fifth inverting circuit includes 2p-1 inverters, which are connected in series in sequence, where p is a positive integer.
6. A high-isolation T-type analog switch, characterized in that, Includes the control circuit as described in any one of claims 1-3, and a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein: The source of the first PMOS transistor and the source of the first NMOS transistor are used together as the input terminal, and the source of the second PMOS transistor and the source of the second NMOS transistor are used together as the output terminal. The drains of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the third control signal of the control circuit. The source of the third PMOS transistor is coupled to the power supply voltage, and the gate of the third PMOS transistor is connected to the first control signal of the control circuit. The drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected together. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the fourth control signal of the control circuit. The source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to the second control signal of the control circuit.
7. A high-isolation T-type analog switch, characterized in that, Includes the control circuit as described in any one of claims 4-5, and a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein: The source and drain of the fourth PMOS transistor are shorted together, the source and drain of the fifth PMOS transistor are shorted together, the source and drain of the fourth NMOS transistor are shorted together, and the source and drain of the fifth NMOS transistor are shorted together; the source of the first PMOS transistor, the source of the fourth PMOS transistor, the source of the first NMOS transistor, and the source of the fourth NMOS transistor together serve as the input terminal, and the source of the second PMOS transistor, the source of the fifth PMOS transistor, the source of the second NMOS transistor, and the source of the fifth NMOS transistor together serve as the output terminal; The drains of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the third control signal of the control circuit. The gates of the fourth PMOS transistor and the fifth PMOS transistor are both connected to the fifth control signal of the control circuit. The source of the third PMOS transistor is coupled to the power supply voltage, and the gate of the third PMOS transistor is connected to the first control signal of the control circuit. The drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected together. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the fourth control signal of the control circuit. The gates of the fourth NMOS transistor and the fifth NMOS transistor are both connected to the sixth control signal of the control circuit. The source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to the second control signal of the control circuit.
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