A Manchester decoding method with error correction for cross-time domain communication

Abstract

The present invention provides a Manchester decoding method for cross-time domain communication with correctable errors, including: a decoding unit, a data storage unit, an error detection unit and a CRC check unit; the decoding unit samples the serially-incoming Manchester code, and decodes it using the level edge and detection time method, and after decoding, sends a flag bit and data to the storage unit for storage; the error detection unit detects the frame header data stored in the storage data unit, and sends the flag bit to the decoding unit when the data is inconsistent, and performs decoding adjustment. Compared with detecting a single level or level jump edge, the method of the present application combines the level edge and detection time method, effectively solves the problem of cross-time domain clock data width compression, can quickly correct errors when powering on, find the correct start bit for decoding, and realizes rapid error correction when powering on; and through the dual judgment of the frame header and CRC, the correctness of the decoded binary code is guaranteed.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronic equipment communication, and in particular relates to an error-correctable Manchester code decoding method based on cross-time domain communication. Background Art

[0002] Manchester encoding is a synchronous clock encoding technology, also called phase encoding (PE), which transmits synchronous clock information by jumping level, does not require a separate clock synchronization signal, does not contain a DC component, has good anti-interference ability, and is more suitable for channel transmission in Ethernet media systems. In this patent document, there is no special description that "Manchester encoding signal" is used to specifically refer to data encoded using Manchester encoding rules and then transmitted.

[0003] In the Manchester coding rule, there is a transition in the middle of each bit of data in the Manchester coding signal. The transition from high level to low level represents the data bit "1", and the transition from low level to high level represents the data bit "0". However, since Manchester code has no special level to determine the start bit, it is very easy to find the wrong start bit and decode the wrong data. Therefore, it is necessary to provide an improved technical solution to address the shortcomings of the existing technology.

[0004] Prior art CN 105281776 A is a Manchester decoding device and method capable of error correction, which does not take into account the problem of the change in the high and low level width of the Manchester code when crossing clock domains, and only judges the bit errors. The method for judging the bit errors in this article is CRC check.

[0005] Prior art CN 105162471 A is a differential Manchester decoding circuit and method, which does not take into account the problem of the change in the high and low level width of the Manchester code when crossing clock domains, and does not judge the bit error. Summary of the invention

[0006] In order to solve the problems existing in the above background technology, the purpose of the present invention is to provide an asynchronous communication error-correctable Manchester decoding method, which belongs to an asynchronous communication Manchester decoding method for correctly parsing Manchester code data.

[0007] To achieve the above purpose, the technical solution of the present invention is as follows.

[0008] A Manchester decoding method capable of correcting errors in cross-time domain communication, wherein a frame of Manchester code data includes a frame header, a data segment and a CRC check code;

[0009] Each 16-bit Manchester code is defined as a group of data, and each 14 groups of data constitute a data segment of a frame of data. A frame header is added in front of the data segment, and the frame header includes 2 groups of data (the frame header information includes 2 groups of Manchester codes). A CRC check bit is added after the data segment, and the length of the CRC check bit is the length of two groups of data, forming a total of 18 groups of data, and the 18 groups of data constitute a frame of Manchester code data;

[0010] The present application discloses a Manchester decoding method for cross-time domain communication with correctable errors, including a decoding unit, a data storage unit, an error detection unit and a CRC check unit:

[0011] The decoding unit decodes the serially transmitted Manchester code, and decodes each 16-bit Manchester code as a group of data to obtain decoded data; after a group of data is decoded, a first high-level square wave signal is generated, and the first high-level square wave signal is a trigger condition for storing the data unit;

[0012] The data storage unit stores the decoded data after receiving the first high level square wave signal;

[0013] The error detection unit detects the frame header data stored in the storage data unit. The frame header data is the start character of two fixed eight-bit bytes defined according to the FT3 protocol. If it is determined that the received frame header data is not a fixed value, the storage unit data is inconsistent. When the storage unit data is inconsistent, cumulative counting is performed. When the cumulative number reaches the error detection limit value, a second high-level square wave signal is generated and sent to the decoding unit. The decoding unit accumulates the count after receiving the second high-level square wave signal.

[0014] The CRC check unit performs CRC check on the binary code converted from the Manchester code.

[0015] The decoding unit includes counter 1, counter 2, counter 3 and counter 4, and the error detection unit includes counter 5;

[0016] Counter one is used to parse the Manchester code; counter two counts and outputs the first high-level square wave signal after a set of data is parsed; if the second high-level square wave signal is received, counter three adds one; counter four counts the data during the decoding process, and is used to reach the initial position of the next Manchester code after decoding two bits of Manchester code.

[0017] The counting range of counter one is 0-5, the counting range of counter two is 0-7, the counting range of counter three is 0-7, the cumulative counting amount of counter four is greater than 8, and the cumulative counting amount of counter five is greater than the error judgment limit value (the error judgment limit value in this embodiment is 78);

[0018] The counter one is used for state machine counting. The counter one has 6 states, and the 6 states are respectively the values ​​of the counter one. The values ​​of the counter one are 0, 1, 2, 3, 4 and 5 respectively. The current decoding state is judged according to the value of the counter one. When the value of the counter one is 0, the values ​​of the counter two and the counter three are judged. A group of Manchester codes is 16 bits, which constitute an 8-bit binary code. The ranges of the two counters of the counter two and the counter three are both 0-7. When the cumulative count values ​​of the counter two and the counter three are equal, it means that a group of data parsing is completed, and a first high-level square wave signal is generated to trigger the storage data unit to store data. When the counter one is in 1, 2, 3 and state 4, it is a decoding state. When the counter one is in state 5, the 1-bit binary code is parsed, the counter two is increased by 1, and the initial value of the counter three is 0. When the storage unit data is detected to be inconsistent, the error judgment unit triggers the counter five to increase by 1. When the cumulative number of times of the counter five reaches a limit value, a second high-level square wave signal is generated and sent to the decoding unit. After the decoding unit receives the second high-level square wave signal, the counter three is increased by 1.

[0019] Whenever the accumulated counts of counter 2 and counter 3 are the same, it indicates that a set of data has been parsed, and a first high-level square wave signal with a small width is generated. The width of the first high-level square wave signal is one clock cycle of the parsed data clock. The width of the first high-level square wave signal and the second high-level square wave signal is one clock cycle of the parsed data clock.

[0020] When counter one is in the 0 state, determine the initial level state at this time. When the initial level is 0, enter state 3. After finding the rising edge, output decoding 0 and enter state 4. Counter four is cleared after counting to 6, and counter one enters state 5; when the initial level is 1, enter state 1. After the falling edge is triggered, output decoding 1 and enter state 2. Counter four accumulates to 8 (counter four accumulates 8) and then is cleared, and counter one enters state 5.

[0021] After the error judgment unit receives the first high-level square wave signal from the decoding unit, it compares whether the stored frame header value is the frame header data specified by the FT3 protocol. If it is inconsistent, counter five increases by 1 and continues to judge when the next set of data arrives. When counter five reaches the specified time length, counter three increases by 1.

[0022] During asynchronous transmission, at t1, counter 1 is in state 0, and it is determined that the initial state of the start bit is 0. Counter 1 enters state 3, and after finding the rising edge, the data is decoded to be 0. At t2, counter 1 enters state 4, and counter 4 starts counting. When counting to 6, it reaches t3, and counter 4 is cleared; counter 1 enters state 5, and counter 2 adds 1; the decoding of the 1-bit binary code is completed from t1 to t3; after counter 2 completes adding 1, counter 1 returns to state 0 again to determine the start bit, and the start bit is 1. After detecting that counter 1 enters state 1, it finds the falling edge and decodes the data to be 1. At t4, counter 1 enters state 2, and counter 4 starts counting. When counting to 8, it reaches t5, and counter 4 is cleared; at this time, counter 1 enters state 5, and counter 2 adds 1;

[0023] When counter one is at 0, determine the level state. If the level is 1, enter state 1, find the falling edge of the data, and then enter state 2. Counter four starts counting. When the cumulative count value of counter four is 8, enter state 5, clear counter four, and add 1 to counter two.

[0024] When the accumulated values ​​of counter three and counter two are equal, the first high-level square wave signal is generated, and the storage unit stores the data; when a frame of data comes in, the frame header is judged after the frame header is parsed. If the frame header is the same as the fixed frame header data in the protocol, the decoding continues. When a frame of data is transmitted, the CRC check code is calculated, and the calculated CRC check code is compared with the transmitted CRC check code to determine whether the frame data is wrong; if the calculated CRC check code is different from the CRC check code in the transmitted data, the data is wrong, and the third high-level square wave signal is sent to the host computer to discard the frame data. The width of the third high-level square wave signal is one clock cycle of the parsed data clock.

[0025] The range of counter two and counter three is 0~7. The value of counter three changes only when there is a fault. Counter two increases by one every time the state of counter one is 5. Each increase by one represents the decoding of one bit of binary code. When the values ​​of counter two and counter three are equal, the decoding of 8-bit binary code (a set of data) is completed.

[0026] The beneficial effects of the present invention include:

[0027] The present application discloses a Manchester decoding method for cross-time domain communication with correctable errors, which combines level edge and detection time methods to effectively solve the problem of cross-time domain clock data width compression;

[0028] The present invention discloses a Manchester decoding method for cross-time domain communication with correctable errors. The method can quickly correct errors and find the correct starting bit for decoding when powered on. The present application adds an error correction unit, which includes a counter five. When the counter five receives erroneous frame header data (which also indicates a starting bit error), the counter five will add one by itself. When the value of the counter five reaches an error judgment limit value, a second high-level signal is triggered. The second high-level signal is transmitted to a decoding unit. When the decoding unit receives the second high-level signal, the counter three will add one by itself. At this time, the starting bit position of the decoding is modified, thereby realizing rapid error correction when powered on. Furthermore, through the dual judgment of the frame header and CRC, the correctness of the decoded binary code is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a flow chart of a Manchester decoding method capable of correcting errors in cross-time domain communication according to the present invention;

[0030] Figure 2 It is a schematic diagram of the Manchester code data protocol of the present invention;

[0031] Figure 3 It is a flow chart of an embodiment of the Manchester code parsing method of the present invention;

[0032] Figure 4 It is a schematic diagram of the start position detection method of the present invention. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0034] like Figure 2 The data protocol diagram of the present invention is shown. The present invention adopts the FT3 communication protocol specified in GB / T 18657.1-2002. Every 16-bit Manchester code is defined as a group of data, and every 18 groups of data are defined as a frame of data, which contains 2 groups of frame header information and adds CRC check bits.

[0035] A Manchester decoding method capable of correcting errors in cross-time domain communication, wherein a frame of Manchester code data includes a frame header, a data segment and a CRC check code;

[0036] Each 16-bit Manchester code is defined as a group of data, and each 14 groups of data constitute a data segment of a frame of data. A frame header is added in front of the data segment, and the frame header includes 2 groups of frame header information. A CRC check bit is added after the data segment. The length of the CRC check bit is the length of two groups of data, forming a total of 18 groups of data, and the 18 groups of data constitute a frame of Manchester code data;

[0037] like Figure 1As shown, the present embodiment provides a Manchester decoding method for cross-time domain communication with correctable errors, including a decoding unit, a data storage unit, an error detection unit and a CRC check unit:

[0038] The decoding unit decodes the serially transmitted Manchester code. Each 32-bit Manchester code represents the value of a parameter (mode, power). Each 16-bit Manchester code is decoded as a group of data to obtain decoded data. After a group of data is decoded, a first high-level square wave signal with a small width is generated. The first high-level square wave signal serves as a trigger condition for the storage data unit.

[0039] The data storage unit stores the decoded data after receiving the first high level square wave signal.

[0040] The error detection unit detects the frame header data stored in the storage data unit. The frame header data is the start character of two fixed eight-bit bytes determined according to the FT3 protocol. If it is determined that the received frame header data is not a fixed value, the storage unit data is inconsistent. When the storage unit data is inconsistent, cumulative counting is performed. When the cumulative number reaches the error detection limit value, a second high-level square wave signal with a small width is generated and sent to the decoding unit. The decoding unit accumulates the count after receiving the second high-level square wave signal.

[0041] The CRC check unit performs CRC check on the binary code converted from the Manchester code.

[0042] The frame header is the first data in the entire frame. It consists of 2 groups of data and is decoded like other data. When the frame header data is decoded, the data has been stored.

[0043] The CRC check unit checks the data in the storage unit. After the calculation is completed, the CRC value is sent back to the storage unit for comparison with the CRC value sent by the data.

[0044] The decoding unit includes counter 1, counter 2, counter 3 and counter 4, and the error detection unit includes counter 5;

[0045] Counter 1 is used to parse Manchester code; Counter 2 counts and outputs the first high-level square wave signal (decoding completion flag) after a group of data is parsed; the initial value of Counter 3 is 0. If there is a decoding error flag (the second high-level square wave signal), Counter 3 is incremented by one, which affects the position of a group of data parsed; Counter 4 counts the data during the decoding process, and is used to reach the initial position of the next Manchester code after decoding two bits of Manchester code.

[0046] The counting range of counter one is 0-5, the counting range of counter two is 0-7, the counting range of counter three is 0-7, the cumulative counting amount of counter four is greater than 8, and the cumulative counting amount of counter five is greater than the error judgment limit value (the error judgment limit value in this embodiment is 78).

[0047] The counter 1 is used for state machine counting, and has 6 states (the 6 states are respectively the values ​​of the counter 1, and the values ​​of the counter 1 are 0, 1, 2, 3, 4 and 5 respectively). The current decoding state is judged according to the value of the counter 1; when the value of the counter 1 is 0, the values ​​of the counter 2 and the counter 3 are judged. A set of Manchester codes is 16 bits, which constitute an 8-bit binary code. The ranges of the two counters of the counter 2 and the counter 3 are both 0-7. When the cumulative count values ​​of the counter 2 and the counter 3 are equal, it means that a set of data parsing is completed, and a first high-level square wave signal is generated to trigger the storage data unit to store data. When the counter 1 is in the state 1, 2, 3 and state 4, it is a decoding state. When the counter 1 is in the state 5, the 1-bit binary code is parsed, and the counter 2 is increased by 1. The initial value of the counter 3 is 0. When the storage unit data is detected to be inconsistent, the error judgment unit triggers the counter 5 to increase by 1. When the cumulative number of times of the counter 5 reaches the error judgment limit value, a second high-level square wave signal with a small width is generated and sent to the decoding unit. After the decoding unit receives the second high-level square wave signal, the counter 3 is increased by 1.

[0048] When counter one is in state 0, determine the initial level state at this time. When the initial level is 0, enter state 3. After the rising edge is triggered, the output decoding 0 is entered, and state 4 is entered. Counter four starts counting. After counting to 6, the counter is cleared and enters state 5; when the initial level is 1, enter state 1. After the falling edge is triggered, the output decoding 1 is output; counter one enters state 2, counter four counts to 8 (the range of counter four is 0-7, counter four counts to 8, which means the cumulative count is 8, and the value of counter four is 7) and then is cleared, and enters state 5.

[0049] Counter one is used to parse the Manchester code, counter two is used to count, so that after a group of data is parsed, the first high-level square wave signal (decoding completion flag) is output, counter three is the initial count value (fixed value, if there is a decoding error flag, counter three is added by one, which affects the position of a group of data parsed), and counter four is the data count during the decoding process, so that when two Manchester codes are decoded, the initial position of the next Manchester code can be reached.

[0050] When the storage unit receives the first high-level square wave signal (trigger mark), it stores the current data.

[0051] The error judgment unit includes counter five. After receiving the first high-level square wave signal from the decoding unit, it first compares whether the stored frame header value is the frame header data specified by the FT3 protocol. If it is inconsistent, counter five adds 1 and continues to judge when the next frame data arrives. When counter five reaches the specified time length, counter three adds 1.

[0052] The frame header is the first data in the entire frame data. The frame header includes 2 groups of Manchester code data. Each 16-bit Manchester code is defined as a group of data, which is decoded like other data. When the frame header data is decoded, the data has been stored.

[0053] The CRC check unit checks the data in the storage unit, and after the calculation is completed, it is sent back to the storage unit for comparison with the CRC value sent by the data.

[0054] During asynchronous transmission, at time t1, when counter one is in the 0 state, an initial level state is obtained. When the initial level is 0, it enters state 3. After the rising edge is triggered, the output is decoded 0, and then enters state 4. Counter four counts to 6 and is cleared; when the initial level is 1, it enters state 1. After the falling edge is triggered, the output is decoded 1, counter one enters state 2, and counter four counts to 8 and is cleared.

[0055] like Figure 3 The flowchart of the embodiment of the Manchester code analysis method of the present invention is shown. There are 4 cases. This article takes one case as an example for discussion. During asynchronous transmission, due to the difference in clock domains and hardware loss, the high level width of the Manchester code will be compressed, and the rising edge and the falling edge will be judged to occupy time, such as Figure 2 As shown in the figure, at time t1 in the figure, counter 1 is in state 0, and the initial state of the start bit is judged to be 0. Counter 1 enters state 3, and after finding the rising edge, the decoded data is 0. At t2, counter 1 enters state 4, and counter 4 starts counting. When counting to 6, it reaches time t3, and counter 4 is cleared. At this time, counter 1 enters state 5, and counter 2 adds 1. The process from t1 to t3 has completed the decoding of the 1-bit binary code. After counter 2 completes adding 1, counter 1 returns to state 0 again to judge the start bit. At this time, the start bit is 1. It is detected that counter 1 enters state 1. After finding the falling edge, the decoded data is 1. At t4, counter 1 enters state 2, and counter 4 starts counting. When counting to 8, it reaches time t5, and counter 4 is cleared. At this time, counter 1 enters state 5, and counter 2 adds 1. t1, t2, t3, and t4 are the starting times of clock cycle timing.

[0056] When the counter is at 0, determine the level state before data analysis (corresponding to Figure 3If the level is 0, it will enter state 3, find the rising edge of the data, counter 1 will enter state 4, counter 4 will start counting, when the count value is 6, it will enter state 5, counter 4 will be cleared. Counter 2 plus 1

[0057] When counter one is at 0, determine the level state of the start bit. If the start state is 1, counter one enters state 1, finds the falling edge of the data, enters state 2, counter four starts counting, and when the cumulative count value of counter four is 8, it enters state 5, counter four is cleared, and counter two is incremented by 1.

[0058] The width of the first high-level square wave signal, the second high-level square wave signal, and the third high-level square wave signal is one clock cycle of the parsed data clock.

[0059] like Figure 4 The figure shows a schematic diagram of the start bit detection method of the present invention. At this time, the signal shown in the figure is the first high-level square wave signal sent by the decoding unit.

[0060] At this time, the positions indicated by 0 to 7 in the figure are the positions where the first high-level square wave signal may exist.

[0061] Since counter two is equal to counter three, counter three can only transmit the first high-level square wave signal when it is initially 0. Figure 3 As the high-level flag bit, if the correct decoding is 01010101 as shown in the figure, but the decoding position just falls at the position 0 at the beginning, the decoded data is 10101010 and sent to the storage unit. Due to incorrect data, the storage unit will always make mistakes when receiving and detecting. Counter five accumulates until the second high-level square wave signal is triggered. At this time, counter three adds 1 by itself, and the storage unit receives the correct value 01010101. This method can quickly solve the problem of unstable decoding position error at startup.

[0062] The error flag is not located in the data information, but is just a value passed from the storage unit to the decoding unit.

[0063] When counter one is at 0, determine the level state. If the level is 0, enter state 3, find the rising edge of the data, enter state 4, counter four starts counting, and when the count value is 6, enter state 5, counter four is cleared, and counter two is increased by 1.

[0064] When counter one is at 0, determine the level state. If the level is 1, enter state 1, find the falling edge of the data, enter state 2, counter four starts counting, the value of counter four is 8, enter state 5, counter four is cleared, and counter two is increased by 1.

[0065] When the value of counter three is equal to that of counter two, the first high-level square wave signal is generated, and the storage unit stores the data. When a frame of data comes in, the frame header is judged after the frame header is parsed. If the frame header is the same as the fixed frame header data in the protocol, the decoding continues. When a frame of data is transmitted, the CRC check code is calculated, and the calculated check code is compared with the transmitted check code to determine whether the frame data is incorrect. If the value is different from the fixed frame header data in the protocol, counter five is triggered to add 1. When counter five accumulates to a certain value, the second high-level square wave signal is sent to the decoding unit, counter five is cleared, and counter three is incremented by 1. The range of counter two and counter three is 0~7. Counter three will only change its value when there is a fault, and counter two will add one every time the state of counter one is 5. Each addition indicates that a binary code is decoded. Therefore, when the values ​​of the two counters are equal, the decoding of the 8-bit binary code (a set of data) is completed. Figure 3 , counter three represents 0~7, that is, the first high level can be at different positions.

[0066] In summary, the control method of the present invention realizes the parsing of Manchester code and solves the problem of quickly recovering the parsing error of the start bit when power is turned on, thereby obtaining and outputting the correct binary code.

[0067] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

[0068] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in less than all of the features of the individual embodiments previously disclosed. Therefore, the claims that follow the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present invention.

[0069] Those skilled in the art will appreciate that the modules or units or groups of the devices in the examples disclosed herein may be arranged in the device as described in the embodiment, or alternatively may be located in one or more devices different from the devices in the example. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0070] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or groups in the embodiments may be combined into one module or unit or group, and further may be divided into multiple submodules or subunits or subgroups. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0071] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0072] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0073] The various techniques described herein may be implemented in combination with hardware or software, or a combination thereof. Thus, the method and apparatus of the present invention, or some aspects or portions of the method and apparatus of the present invention may be in the form of program codes (i.e., instructions) embedded in a tangible medium, such as a floppy disk, a CD-ROM, a hard disk drive, or any other machine-readable storage medium, wherein when the program is loaded into a machine such as a computer and executed by the machine, the machine becomes a device for practicing the present invention.

[0074] In the case where the program code is executed on a programmable computer, the computing device generally includes a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store the program code; the processor is configured to execute the method of the present invention according to the instructions in the program code stored in the memory.

[0075] By way of example and not limitation, computer readable media include computer storage media and communication media. Computer readable media include computer storage media and communication media. Computer storage media stores information such as computer readable instructions, data structures, program modules or other data. Communication media generally embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and includes any information delivery medium. Any combination of the above is also included within the scope of computer readable media.

[0076] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0077] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A Manchester decoding method with error correction for cross-time domain communication, wherein a frame of Manchester code data includes a frame header, a data segment and a CRC check code; Each 16-bit Manchester code is defined as a group of data, and each 14 groups of data constitute a data segment of a frame of data. A frame header is added in front of the data segment, and the frame header includes 2 groups of data. A CRC check bit is added after the data segment, and the length of the CRC check bit is the length of two groups of data, forming a total of 18 groups of data, and the 18 groups of data constitute a frame of Manchester code data; It is characterized in that Including decoding unit, data storage unit, error detection unit and CRC check unit: The decoding unit decodes the serially transmitted Manchester code, and decodes each 16-bit Manchester code as a group of data to obtain decoded data; after a group of data is decoded, a first high-level square wave signal is generated, and the first high-level square wave signal is a trigger condition for storing a data unit; The data storage unit stores the decoded data after receiving the first high-level square wave signal; The error detection unit detects the frame header data stored in the storage data unit. The frame header data is a start character of two fixed values ​​of eight bits determined according to the FT3 protocol. If it is determined that the received frame header data is not a fixed value, the storage unit data is inconsistent. When the storage unit data is inconsistent, the counter 5 performs cumulative counting. When the cumulative number reaches the error detection limit value, a second high-level square wave signal is generated and sent to the decoding unit. The decoding unit accumulates the count after receiving the second high-level square wave signal. The CRC check unit performs CRC check on the binary code converted from the Manchester code.

2. The Manchester decoding method for cross-time domain communication with error correction according to claim 1, characterized in that: The decoding unit includes counter 1, counter 2, counter 3 and counter 4, and the error detection unit includes counter 5; The counter one is used for state machine counting, and the counter two counts for outputting the first high-level square wave signal after a set of data is parsed; if the second high-level square wave signal is received, the counter three is incremented by one; the counter four counts the data during the decoding process, and is used to reach the initial position of the next Manchester code after decoding two bits of Manchester code.

3. The Manchester decoding method for cross-time domain communication with error correction according to claim 2, characterized in that: The counting range of counter one is 0-5, the counting range of counter two is 0-7, the counting range of counter three is 0-7, the cumulative counting amount of counter four is greater than 8, and the cumulative counting amount of counter five is greater than the error judgment limit value.

4. The Manchester decoding method for cross-time domain communication with error correction according to claim 2, characterized in that: The counter one is used for state machine counting. The counter one has 6 states, and the 6 states are respectively the values ​​of the counter one. The current decoding state is judged according to the value of the counter one; when the value of the counter one is 0, the values ​​of the counter two and the counter three are judged. A group of Manchester codes is 16 bits, which constitute an 8-bit binary code. When the cumulative count values ​​of the counter two and the counter three are equal, it means that a group of data parsing is completed, and a first high-level square wave signal is generated to trigger the storage data unit to store data; when the counter one is in states 1, 2, 3 and 4, it is a decoding state. When the counter one is in state 5, the 1-bit binary code is parsed, the counter two is increased by 1, and the initial value of the counter three is 0. When the storage unit data is detected to be inconsistent, the error judgment unit triggers the counter five to increase by 1. When the cumulative number of counter five reaches the error judgment limit value, a second high-level square wave signal is generated and sent to the decoding unit. After the decoding unit receives the second high-level square wave signal, the counter three is increased by 1.

5. The Manchester decoding method for cross-time domain communication with error correction according to claim 1, characterized in that: The width of the first high-level square wave signal and the second high-level square wave signal is one clock cycle of the parsed data clock.

6. The Manchester decoding method for cross-time domain communication with error correction according to claim 2, characterized in that: When counter one is in state 0, determine the initial level state at this time. When the initial level is 0, enter state 3, find the rising edge, and decode the binary code at this time to be 0; then counter one enters state 4, counter four counts to 6, after counter four is cleared, counter one enters state 5; when the initial level is 1, counter one enters state 1, finds the falling edge, and decodes the binary code at this time to be 1; then counter one enters state 2, counter four counts cumulatively to 8, after counter four is cleared, counter one is in state 5.

7. The Manchester decoding method for cross-time domain communication with error correction according to claim 2, characterized in that: After the error judgment unit receives the first high-level square wave signal from the decoding unit, it compares whether the stored frame header value is the frame header data specified by the FT3 protocol. If it is inconsistent, counter five increases by 1 and continues to judge when the next set of Manchester decoding data arrives. When counter five reaches the specified time length, counter three increases by 1.

8. The Manchester decoding method for cross-time domain communication with error correction according to claim 2, characterized in that: During asynchronous transmission, at t1, counter 1 is in state 0 and determines the start bit. When the level of the start bit is 0, counter 1 enters state 3 and finds the rising edge to decode the data as 0. At t2, counter 1 enters state 4 and counter 4 starts counting. When the count reaches 6, it reaches t3 and counter 4 is cleared. Counter 1 enters state 5 and counter 2 adds 1. The decoding of 1-bit binary code is completed from t1 to t3. After counter 2 completes adding 1, counter 1 returns to the 0 state again to determine the start bit. The start bit is 1, and counter 1 is detected to enter state 1. After finding the falling edge, the decoded data is 1. At t4, counter 1 enters state 2, and counter 4 starts counting. When counting to 8, it reaches t5, and counter 4 is cleared. At this time, counter 1 enters state 5, and counter 2 adds 1. At time t1, counter one is in state 0. If the starting level is 1, counter one enters state 1, finds the falling edge of the data, enters state 2, counter four starts counting, and when the cumulative count value of counter four is 8, it enters state 5, counter four is cleared, and counter two is incremented by 1.

9. The Manchester decoding method for cross-time domain communication with error correction according to claim 2, characterized in that: When a frame of data comes in for decoding, the frame header is judged after the frame header is parsed. If the frame header is the same as the fixed frame header data in the protocol, the decoding continues. When a frame of data is transmitted, the CRC check code is calculated, and the calculated CRC check code is compared with the transmitted CRC check code to determine whether the frame data is incorrect; if the calculated CRC check code is different from the CRC check code transmitted in the protocol, the data is incorrect, and a third high-level square wave signal is sent to the host computer to discard the frame data.

10. The Manchester decoding method for cross-time domain communication with correctable errors according to claim 9, characterized in that: The width of the third high-level square wave signal is one clock cycle of the analysis data clock.

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