Analog-to-digital conversion circuit, image sensing device and operation method thereof

Abstract

The present application relates to an analog-to-digital conversion circuit, an image sensing device and an operation method thereof. An analog-to-digital conversion circuit includes: an analog-to-digital converter, which is adapted to perform analog-to-digital conversion on pixel signals of a plurality of pixels arranged in a pixel array; a ramp signal generator, which is adapted to provide a ramp signal to the analog-to-digital converter; and an auto-zero controller, which is adapted to provide an auto-zero reference voltage to the analog-to-digital converter by using row pixels on which a readout operation has been performed by the analog-to-digital converter, so as to perform an auto-zero operation.

Description

Technical Field

[0001] Various embodiments of the present invention relate to semiconductor design technology, and more particularly, to an analog-to-digital conversion circuit, an image sensing device, and a method for operating the image sensing device. Background Art

[0002] Recently, the paradigm of computer environment is shifting towards ubiquitous computing, which allows users to access computer systems anytime and anywhere. The paradigm shift has rapidly increased the use of portable electronic devices such as mobile phones, digital cameras, laptop computers, etc.

[0003] Specifically, with the rapid development of imaging devices, the development of image capture devices such as cameras and camcorders equipped with image sensors is accelerating. Since image capture devices can not only capture images and record them in recording media, but also reproduce images at any time, the number of users is rapidly increasing. This has also gradually increased users' requirements for performance and functions, and high performance and multi-functions are pursued while miniaturization, light weight, and low power consumption are being pursued.

[0004] In such an image capture device, an auto-zero operation needs to be performed before analog-to-digital conversion to compensate for the offset of the analog-to-digital converter (ADC). When the pixel operates in a 4-T (including 4 transistors) scheme, the pixel can be refreshed during the readout time, and then the output of the pixel can be used as an auto-zero reference voltage. However, when the pixel operates in a 3-T (including three transistors) scheme, the auto-zero reference voltage must be applied separately because the pixel cannot be refreshed during the pixel readout time. This requires more area due to the addition of separate row pixels. Summary of the invention

[0005] Embodiments of the present invention are directed to providing an analog-to-digital conversion circuit for generating a reference voltage for an auto-zero operation by using a preceding pixel that has completed a readout operation, an image sensing device including the analog-to-digital conversion circuit, and a method for operating the image sensing device.

[0006] The technical problems that are expected to be solved in the embodiments of the present invention are not limited to the above-mentioned technical problems, and ordinary technicians in the field to which the present invention belongs can also clearly understand other technical problems not mentioned above from the following description.

[0007] According to an embodiment of the present invention, an analog-to-digital conversion circuit includes: an analog-to-digital converter, which is suitable for performing analog-to-digital conversion on pixel signals of multiple pixels arranged in a pixel array; a ramp signal generator, which is suitable for providing a ramp signal to the analog-to-digital converter; and an automatic zeroing controller, which is suitable for providing a reference voltage to the analog-to-digital converter by using row pixels on which a readout operation has been performed by the analog-to-digital converter to perform an automatic zeroing operation.

[0008] The auto-zero controller can also block the auto-zero signal provided to the analog-to-digital converter, so that the pixel signal of the row pixel that has completed the readout operation is applied to the analog-to-digital converter as an input signal, and the ramp signal generator can provide the auto-zero reference voltage to another input terminal of the analog-to-digital converter.

[0009] The auto-zero controller may generate an initialization signal to initialize the auto-zero operation.

[0010] Each pixel may be formed of a three-transistor structure.

[0011] The analog-to-digital converter may include: a comparing unit adapted to compare each pixel signal provided from the pixel array with a ramp signal provided from the ramp signal generator according to an auto-zero signal provided from the auto-zero controller; and a counting unit adapted to count clocks according to each output signal from the comparing unit.

[0012] According to another embodiment of the present invention, an image sensing device includes: a pixel array having a plurality of pixels for outputting pixel signals corresponding to incident light; a row decoder adapted to select and control pixels in the pixel array for each row line; an analog-to-digital converter adapted to perform analog-to-digital conversion on pixel signals of a plurality of pixels arranged in the pixel array; a ramp signal generator adapted to provide a ramp signal to the analog-to-digital converter; an auto-zero controller adapted to provide a reference voltage to the analog-to-digital converter by using row pixels on which a readout operation has been performed by the analog-to-digital converter to perform an auto-zero operation; a controller adapted to control the operations of the row decoder, the ramp signal generator, the analog-to-digital converter, and a column readout circuit; and a column readout circuit adapted to output pixel data under the control of the controller.

[0013] The analog-to-digital converter may include: a comparing unit adapted to compare each pixel signal provided from the pixel array with a ramp signal provided from the ramp signal generator according to an auto-zero signal provided from the auto-zero controller; and a counting unit adapted to count clocks according to each output signal from the comparing unit.

[0014] The auto-zero controller may also block the auto-zero signal provided to the comparison unit so that the pixel signal of the row pixel is applied as the input signal of the comparison unit, and the ramp signal generator provides the auto-zero reference voltage to another input terminal of the comparator.

[0015] The auto-zero controller may generate an initialization signal to initialize the auto-zero operation.

[0016] The controller may increase the voltage of the ramp signal generator by a preset offset to convert the output of the comparison unit into a “+” state.

[0017] The controller may operate the analog-to-digital converter to store a conversion result of a reset voltage of a reset transistor of each pixel.

[0018] When a first row of pixels among the pixels are dummy row pixels, the auto-zero controller may block the auto-zero signal and perform the auto-zero operation on the first row of pixels instead of the row pixels for which the readout operation is completed.

[0019] Each pixel may be formed of a three-transistor structure.

[0020] According to another embodiment of the present invention, a method for operating an image sensing device in which a pixel signal provided from a pixel array including a plurality of pixels is converted by an analog-to-digital converter and output as pixel data includes: performing a refresh operation of clearing a photodiode (PD) and a floating node (FD) by closing a switch of a reset transistor provided in each pixel; performing an integration operation of accumulating charges generated during exposure in a floating node by opening a switch of the reset transistor; and performing an auto-zero operation of providing a reference voltage by using a row of pixels among the pixels for which a readout operation has been completed by the analog-to-digital converter.

[0021] The step of performing an auto-zero operation may include: applying a pixel signal of a row of pixels that has completed a readout operation as a reference voltage to an input terminal of the analog-to-digital converter by blocking an auto-zero signal provided to the analog-to-digital converter, and providing a ramp signal to another input terminal of the analog-to-digital converter.

[0022] The step of performing the auto-zero operation may further include clearing the floating node by closing the switch of the reset transistor of the row pixel that has completed the readout operation while the switch of the select transistor of the row pixel that has completed the readout operation is closed.

[0023] The method may further include generating an initialization signal to initialize the auto-zero operation.

[0024] The method may further include increasing the voltage of the ramp signal by a preset offset to convert the output of the comparison unit into a “+” state. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram illustrating an image sensing device according to an embodiment of the present invention.

[0026] Figure 2 is an example of an embodiment according to the present invention Figure 1 The pixel shown in FIG. 1 is a circuit diagram of a circuit having a 3T structure.

[0027] Figure 3 is an example of an embodiment according to the present invention. Figure 1 A circuit diagram showing a pixel array in which a previous pixel that completes a readout operation provides a reference voltage to an analog-to-digital converter.

[0028] Figure 4 is a flowchart describing the operation of an image sensing device according to another embodiment of the present invention.

[0029] Figure 5 is a block diagram illustrating an embodiment of a system to which an image sensing device according to an embodiment of the present invention is applied. DETAILED DESCRIPTION

[0030] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, similar reference numerals refer to similar parts in each of the drawings and throughout the embodiments of the present invention.

[0031] It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it may mean that the two are directly coupled to each other or electrically connected to each other with another circuit interposed therebetween. In the present disclosure, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0032] In the following, reference will be made to Figures 1 to 3 An image sensing device according to an embodiment of the present invention is described. Figure 1 is a block diagram illustrating an image sensing device 100 according to an embodiment of the present invention. Figure 2 is an example of an embodiment according to the present invention Figure 1 The pixel shown in FIG. 1 is a circuit diagram of a circuit having a 3T structure. Figure 3 is an example of an embodiment according to the present invention. Figure 1 A circuit diagram showing a pixel array in which a previous pixel that completes a readout operation provides a reference voltage to an analog-to-digital converter.

[0033] Figure 1 The image sensing device 100 shown may include a pixel array 10, a row decoder 20, an auto-zero controller 25, a ramp signal generator 30, a comparator 40, a counter 50, a column readout circuit 70, and a controller 80. In this case, the comparator 40 and the counter 50 may be included in the analog-to-digital converter 90.

[0034] The pixel array 10 may include a plurality of pixels 11 that output pixel signals corresponding to incident light.

[0035] In this embodiment of the invention, Figure 2 As shown, as an example, a 3T-type pixel structure including three transistors may be adopted.

[0036] exist Figure 2 In the 3T pixel structure shown, the pixel 11 may include a photodiode PD, a reset transistor RX, an amplifier transistor DX, and a selection transistor SX.

[0037] After the reset transistor RX is activated in response to the reset signal RST to reset the floating node FD, light may be accumulated in the floating node FD through the photodiode PD, and a pixel signal may be output through the line 42 according to the selection signal SEL provided to the selection transistor SX.

[0038] Since the 3T pixel structure is a well-known technology well known to those skilled in the art to which the present invention belongs, a detailed operational description of the 3T pixel structure will be omitted.

[0039] The row decoder 20 may select a plurality of pixels in the pixel array 10 for each row line and control the operation thereof according to the control of the controller 80. For example, a readout operation may be performed on the pixels on a row-by-row basis. That is, when a previous readout operation is completed on pixels in a preceding row, a current readout operation may be performed on pixels in a row subsequent to the preceding row.

[0040] The ramp signal Vramp generated by the ramp signal generator 30 is provided to the analog-to-digital converter 90 as an auto-zero reference voltage under the control of the controller 80, so that the comparator 40 of the analog-to-digital converter 90 performs an auto-zero operation by using a preceding pixel among the pixels that has completed the readout operation. That is, the pixel output from the preceding pixel is provided to one input terminal of the comparator 40 as a reference voltage, while the ramp signal Vramp is provided to the other input terminal of the comparator 40 as an auto-zero reference voltage.

[0041] After performing the auto-zero operation, the auto-zero controller 25 may block the auto-zero signal supplied to the comparator 40 to apply a pixel signal of a preceding pixel that has completed the readout operation as a reference signal to one terminal of the comparator 40 .

[0042] Here, the auto-zero signal may be an operation signal for finely adjusting an offset value of the ramp signal Vramp when a voltage level of the ramp signal Vramp generated by the ramp signal generator 30 matches a voltage level of the pixel signal Vp provided from the pixel array 10 .

[0043] In addition, the auto-zero controller 25 may generate an initialization signal for initializing the auto-zero operation of the comparator 40 under the control of the controller 80 , and provide the initialization signal to the comparator 40 .

[0044] The ramp signal generator 30 may generate a ramp signal Vramp and provide it to the comparator 40. Specifically, the ramp signal generator 30 may provide the ramp signal Vramp to the comparator 40 as an auto-zero reference voltage for an auto-zero operation.

[0045] Since the voltage level of the ramp signal Vramp decreases (or increases) with the lapse of time, there is a time when the values ​​of the two signals input to the comparator 40 coincide with each other. As the coincidence time passes, the value of the comparison signal output from the comparator 40 may be inverted.

[0046] After completing the auto-zero operation according to the auto-zero signal provided from the auto-zero controller 25, the comparator 40 may be provided with a plurality of comparison units 41, and the comparator 40 may compare each pixel signal provided from the pixel array 10 with the ramp signal provided by the ramp signal generator to generate a comparison result, and output the comparison result as a logic high value or a logic low value.

[0047] Specifically, the comparator 40 may receive a pixel signal of a preceding pixel that has completed the readout operation under the control of the auto-zero controller 25, and compare it with the ramp signal provided from the ramp signal generator 30. The counter 50 may be provided with a plurality of counting units 51, and may count clocks according to each output signal from the comparator 40.

[0048] The counter 50 can count the clock from the controller 80 to output the count information from the time when the ramp signal Vramp falls (or rises) to the time when the comparison signal output from the comparator 40 is inverted. Here, each counting unit can be initialized according to the reset signal from the controller 80.

[0049] The column readout circuit 70 may sequentially output the output signal of the counter 50 as pixel data PXDATA under the control of the controller 80 .

[0050] The controller 80 may control operations of the row decoder 20 , the auto-zero controller 25 , the ramp signal generator 30 , the analog-to-digital converter 90 , and the column readout circuit 70 .

[0051] In addition, the controller 80 may increase the ramp signal voltage of the ramp signal generator 30 by a preset offset, and control the comparator 40 to compare the ramp signal Vramp and the pixel signal Vp with each other to switch the output of the comparator 40 to a logic high state.

[0052] In addition, the controller 80 may operate the analog-to-digital converter 90 to store a conversion result of the voltage of the reset signal RST of the reset transistor RX of each pixel in a memory (not shown).

[0053] When the first row of pixels among the pixels is a dummy row of pixels, the auto-zero controller 25 can block the auto-zero signal and directly perform the auto-zero operation on the first row of pixels of the pixel array instead of the preceding row of pixels. In this case, the dummy row of pixels can be preset to have a preset value.

[0054] In the following, reference will be made to Figure 4 A method for operating an image sensing device according to an embodiment of the present invention is described. Figure 4 is a flowchart describing the operation of an image sensing device according to another embodiment of the present invention.

[0055] like Figure 4 As shown, the operation of the image sensing device according to the embodiment of the present invention may include operation S410 for performing a refresh operation on a plurality of pixels, operation S420 for performing an integration operation, and operations S430 to S470 for performing a readout operation.

[0056] In operation S410 , a refresh operation of refreshing the photodiode PD and the floating node FD by closing the reset transistor RX provided in each pixel included in the pixel array 10 may be performed.

[0057] In operation S420 , when the photodiode PD is exposed to light, generated charges may be accumulated in the floating node FD by turning on the reset transistor RX.

[0058] In the readout operation of operations S430 to S470 , the reference voltage may be provided by using a preceding pixel for which the readout operation by the analog-to-digital converter 90 is completed.

[0059] In operation S430 , when the switch of the selection transistor SX at the preceding pixel is closed, the charge of the floating node FD may be refreshed by closing the reset transistor RX at the preceding pixel.

[0060] In operation S440, by opening the switch of the preceding reset transistor RX and blocking the auto-zero signal, the pixel output output from the preceding pixel can be applied as a reference voltage to one input terminal of the comparator 40 of the analog-to-digital converter 90, and the ramp signal generator 30 can apply the ramp signal as the auto-zero reference voltage to another input terminal of the comparator 40.

[0061] In operation S450, an initialization signal may be generated by the auto-zero controller to initialize the auto-zero operation.

[0062] In operation S460 , the output of the comparator 40 may be switched to a logic high state by increasing the voltage of the ramp signal by a preset offset.

[0063] In operation S470 , a conversion result of the voltage of the reset signal RST of the pixel 11 may be stored through the operation of the analog-to-digital converter.

[0064] When the first row of pixels among the pixels are dummy row pixels, the auto-zero signal may be blocked, and the auto-zero operation of the first row of pixels of the pixel array may be directly performed instead of the auto-zero operation of the preceding row of pixels.

[0065] In the following, reference is made to Figure 5 , an embodiment of a system to which an image sensing device according to an embodiment of the present invention is applied will be described. Figure 5 is a block diagram illustrating an embodiment of a system to which an image sensing device according to an embodiment of the present invention is applied.

[0066] Figure 5 The system shown may be one of the following: a personal computer system, a desktop computer, a laptop computer, a mainframe computer system, a handheld computing device, a cellular phone, a smart phone, a mobile phone, a workstation, a network computer, a consumer device, an application server, a storage device, an intelligent display, a peripheral device (such as a switch, a modem, a router, etc.), and a general type of computing device, but the present invention is not limited thereto, and Figure 5 The system shown may be one of several types of computing devices.

[0067] Figure 5 The system shown may represent a system on a chip (SOC). As the name implies, the components of SOC 1000 may be integrated on a single semiconductor substrate, such as an integrated circuit "chip". According to some embodiments of the present invention, the components in the system may be implemented on two or more separate chips. Here, SOC 1000 will be used as an example.

[0068] According to the illustrated embodiment of the present invention, components of SOC 1000 may include a central processing unit (CPU) complex 1020, on-chip peripheral device components 1040A and 1040B (which may be simply referred to as “peripherals”), a memory controller (MC) 1030, an image signal processor 400, and a communication structure 1010.

[0069] SOC 1000 may also be coupled to additional components, such as memory 1800 and image sensors. Components 1020, 1030, 1040A and 1040B and 400 may all be coupled to communication fabric 1010. Memory controller 1030 may be coupled to memory 1800 when used, and peripheral device 1040B may be coupled to external interface 1900 when used.

[0070] In an embodiment of the present invention, the CPU complex 1020 may include one or more processors 1024 and a secondary cache L2 1022. The peripheral devices 1040A and 1040B may be a collection of additional hardware functions included in the SOC 1000. For example, the peripheral devices 1040A and 1040B may include a display controller formed to display video data on one or more display devices, a graphics processing unit (GPU), a video encoder / decoder, a scaler, a rotator, a mixer, etc.

[0071] The image signal processor 400 can process image capture data from the image sensor (or another image sensor). As for the structure and operation of the image sensor, please refer to Figures 1 to 4 The structure and operation of the image sensing device 100 shown in FIG. For example, the image sensor may provide a reference voltage to the analog-to-digital converter by using a preceding pixel that has completed a readout operation by the analog-to-digital converter to perform an auto-zero operation.

[0072] The peripheral devices may also include audio peripheral devices such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. The peripheral devices may include a peripheral device interface controller (e.g., peripheral device 1040B) for various interfaces 1900 external to the SOC 1000, including a universal serial bus (USB), a peripheral component interconnect (PCI) including PCI-Express (PCIe), serial and parallel ports, etc. The peripheral devices may also include networking peripheral devices such as a media access controller (MAC).

[0073] The CPU complex 1020 may include one or more CPU processors 1024 that serve as the CPU of the SOC 1000. The CPU of the system may include (multiple) processors that execute the main control software of the system (e.g., an operating system). Typically, the software executed by the CPU during operation can control other components of the system to achieve the intended functions of the system. The processor 1024 may also execute other software such as application programs. The application program may provide functionality to the user and may depend on the operating system for low-level device control. Therefore, the processor 1024 may also be referred to as an application processor.

[0074] The CPU complex 1020 may also include other hardware, such as an L2 cache 1022 and / or interfaces for other components of the system (eg, an interface for the communications fabric 1010 ).

[0075] Typically, the processor may include any circuit and / or microcode formed to execute commands defined in a command set architecture implemented by the processor. Although commands and data executed by the processor may generally be stored in the memory 1800 in response to the execution of commands, predetermined commands may also be defined as for the processor to directly access peripheral devices. The processor may include a processor core and other components implemented on an integrated circuit, such as a system on a chip (SOC 1000), or other levels of integration. The processor may also include a separate microprocessor, a microprocessor integrated in a processor core and / or a multi-chip module implementation, a processor implemented as a plurality of integrated circuits, and the like.

[0076] The memory controller 1030 may include circuits that typically receive memory operation commands from other components of the SOC 1000 and access the memory 1800 to complete the memory operation. The memory controller 1030 may be formed to access any type of memory 1800. For example, the memory 1800 may be a static random access memory (SRAM), or a synchronous dynamic random access memory (SDRAM) including DRAMs such as double data rate (DDR, DDR2, DDR3, etc.) DRAMs. Low power / mobile versions of DDR DRAMs (e.g., LPDDR, mDDR, etc.) may be supported. The memory controller 1030 may include a queue for directing (and potentially redirecting) and presenting memory operations to the memory 1800. The memory controller 1030 may also include a data buffer that stores write data waiting to be written into the memory and read data waiting to be returned to the source of the memory operation.

[0077] According to some embodiments of the present invention, the memory controller 1030 may include a memory cache that stores recently accessed memory data. In the implementation of the SOC, the memory cache can reduce the power ratio in the SOC by avoiding re-accessing data from the memory 1800 when the data is expected to be accessed again soon. In some cases, the memory cache may be referred to as a system cache, such as a private cache that only supports predetermined components, for example, the L2 cache 1022 of the processor 1024. According to some embodiments of the present invention, the system cache may not necessarily be located inside the memory controller 1030.

[0078] According to an embodiment of the present invention, the memory 1800 may be packaged in the form of a chip stack or a package stack together with the SOC 1000. A multi-chip module structure of the SOC 1000 and the memory 1800 may also be used.

[0079] Therefore, although the protection data may be stored in the memory 1800 unencrypted, the protection data may be encrypted to be exchanged between the SOC 1000 and an external endpoint.

[0080] The communication fabric 1010 may be any communication interconnect and protocol for communicating between components of the SOC 1000. The communication fabric 1010 may be bus based including a layered bus with shared bus elements, crossbar elements, and bridges. The communication fabric 1010 may also be packet based and it may be a layer with bridges, crossbars, point-to-point connections, or other interconnects.

[0081] The methods described in this specification may be implemented by a computer program product or software. According to some embodiments of the present invention, a non-transitory computer-readable storage medium may program a computer system (or other electronic device) and may store commands that may be used to perform some or all of the techniques described herein. A computer-readable storage medium may include any mechanism for storing information in a machine (e.g., computer) readable form (e.g., software and processing applications). Machine-readable media may include magnetic storage media (e.g., floppy disks); optical storage media (e.g., CD-ROMs); magneto-optical storage media; read-only memory (ROM); random access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory; and other types of media suitable for storing electrical or programming commands, but the concept and spirit of the present invention are not limited thereto. In addition, program commands may be communicated using light, sound, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.).

[0082] Computer system 1000 may include one or more modules, such as processor unit 1020 (which may be multiple processors, a single-threaded processor, a multi-threaded processor, a multi-core processor, etc.), that may exist in program commands stored in memory 1800 of the same computer system or in program commands stored in a memory of a system similar to or different from computer system 1000 to perform some or all of the techniques described herein.

[0083] According to an embodiment of the present invention, an auto-zero operation may be performed by supplying a reference voltage to an analog-to-digital converter using a preceding pixel that has completed a readout operation by an analog-to-digital converter included in an analog-to-digital conversion circuit.

[0084] Therefore, the auto-zero operation does not require an additional separate row of pixels, and thus the area within the analog-to-digital conversion circuit can be reduced.

[0085] In addition, since the pixels in the preceding row that have completed readout and are adjacent to the row pixels currently being read may be used for the auto-zero operation, the analog-to-digital conversion circuit may be less affected by the IR drop.

[0086] The effects expected to be obtained by the embodiments of the present invention are not limited to the effects mentioned above, and a person skilled in the art to which the present invention belongs may also clearly understand other effects not mentioned above from the following description.

[0087] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.

[0088] CROSS-REFERENCE TO RELATED APPLICATIONS

[0089] This application claims priority to Korean Patent Application No. 10-2021-0061502, filed on May 12, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. An analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: an analog-to-digital converter that performs analog-to-digital conversion on pixel signals of a plurality of pixels disposed in a pixel array; A ramp signal generator, which provides a ramp signal to the analog-to-digital converter; as well as an auto-zero controller for performing an auto-zero operation by supplying a reference voltage to the analog-to-digital converter using a row of pixels for which a readout operation by the analog-to-digital converter has been completed among the plurality of pixels, The auto-zero controller blocks the auto-zero signal provided to the analog-to-digital converter, so that the pixel signal of the row of pixels that has completed the readout operation is applied to the analog-to-digital converter as the reference voltage.

2. The analog-to-digital conversion circuit according to claim 1, in, The pixel signal is applied to one input terminal of the analog-to-digital converter, and The ramp signal generator provides the ramp signal as an automatic zero reference voltage to another input terminal of the analog-to-digital converter.

3. The analog-to-digital conversion circuit according to claim 2, wherein: The auto-zero controller also generates an initialization signal to initialize the auto-zero operation.

4. The analog-to-digital conversion circuit according to claim 1, wherein: Each of the pixels is formed of a three-transistor structure.

5. The analog-to-digital conversion circuit according to claim 1, wherein: The analog-to-digital converter comprises: a comparator that compares each pixel signal provided from the pixel array with the ramp signal provided from the ramp signal generator according to the auto-zero signal provided from the auto-zero controller; and A counter counts clocks according to each output signal from the comparator.

6. An image sensing device, comprising: a pixel array having a plurality of pixels for outputting pixel signals corresponding to incident light; an analog-to-digital converter that performs analog-to-digital conversion on pixel signals of the plurality of pixels on a row-by-row basis; A ramp signal generator, which provides a ramp signal to the analog-to-digital converter; an auto-zero controller that performs an auto-zero operation by supplying a reference voltage to the analog-to-digital converter using a row of pixels for which a readout operation has been completed by the analog-to-digital converter; and a column readout circuit, which outputs pixel data under the control of the controller, The auto-zero controller blocks the auto-zero signal provided to the analog-to-digital converter, so that the pixel signal of the row of pixels that has completed the readout operation is applied to the analog-to-digital converter as the reference voltage.

7. The image sensing device according to claim 6, wherein: The analog-to-digital converter comprises: a comparator that compares each pixel signal provided from the pixel array with the ramp signal provided from the ramp signal generator according to the auto-zero signal provided from the auto-zero controller; and A counter counts clocks according to each output signal from the comparator.

8. The image sensing device according to claim 7, in, The pixel signal is applied to one input terminal of the comparator, and The ramp signal generator provides the ramp signal as an automatic zero reference voltage to another input terminal of the comparator.

9. The image sensing device according to claim 7, wherein: The auto-zero controller also generates an initialization signal to initialize the auto-zero operation. 10 . The image sensing device of claim 9 , further comprising a controller which increases the voltage of the ramp signal generator by a preset offset to convert the output of the comparator into a logic high state. 11 . The image sensing device according to claim 9 , further comprising a controller which operates the analog-to-digital converter to store a conversion result of the reset voltage of the reset transistor of each pixel in a memory.

12. The image sensing device according to claim 6, wherein: When a first row of pixels among the pixels are dummy row pixels, the auto-zero controller blocks an auto-zero signal and performs an auto-zero operation on the first row of pixels instead of the row of pixels on which the readout operation is completed.

13. The image sensing device according to claim 6, wherein: Each of the pixels is formed of a three-transistor structure.

14. A method of operating an image sensing device in which a pixel signal provided from a pixel array including a plurality of pixels is converted by an analog-to-digital converter and output as pixel data, the method comprising the steps of: performing a refresh operation of refreshing a photodiode and a floating node in each of the pixels by closing a reset transistor provided in each of the pixels; performing an integration operation of accumulating charges generated during exposure in the floating node by turning on a reset transistor; as well as performing an auto-zero operation of providing a reference voltage by using a row of pixels of the plurality of pixels for which a readout operation by the analog-to-digital converter has been completed, The step of performing the auto-zero operation includes the following steps: applying the pixel signal of the row of pixels that has completed the readout operation as the reference voltage to the analog-to-digital converter by blocking the auto-zero signal provided to the analog-to-digital converter.

15. The method according to claim 14, in, The pixel signal is applied to one input terminal of the analog-to-digital converter, and The step of performing the automatic zeroing operation further includes the following steps: providing a ramp signal as an automatic zeroing reference signal to another input terminal of the analog-to-digital converter.

16. The method according to claim 15, wherein: The step of performing the automatic zeroing operation also includes the following step: refreshing the floating node of the row of pixels that have completed the readout operation by closing the reset transistor of the row of pixels that have completed the readout operation while the selection transistor of the row of pixels that have completed the readout operation is closed.

17. The method according to claim 16, further comprising the steps of: An initialization signal is generated to initialize the auto-zero operation.

18. The method according to claim 16, further comprising the steps of: The voltage of the ramp signal is increased by a preset offset to convert the output of the comparator into a logic high state.

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