Semiconductor memory device

Abstract

A semiconductor storage device having a capacitor insulating film with small leakage current is provided. The semiconductor storage device of the present embodiment includes a first oxide semiconductor layer between a first conductive layer and a second conductive layer; a first gate electrode surrounding the first oxide semiconductor layer; a first electrode electrically connected to the second conductive layer, containing Ti; a second electrode surrounding the first electrode, containing Ti; a first capacitor insulating film between the first electrode and the second electrode; a third conductive layer electrically connected to the first conductive layer; a second oxide semiconductor layer between the third conductive layer and a fourth conductive layer; a second gate electrode surrounding the second oxide semiconductor layer; a third electrode electrically connected to the fourth conductive layer, containing Ti; a fourth electrode surrounding the third electrode, containing Ti; and a second capacitor insulating film between the third electrode and the fourth electrode.

Description

[0001] Related Application

[0002] This application claims priority from Japanese Patent Application No. 2021-151984 (filing date: September 17, 2021) as a basic application, and the entire contents of the basic application are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Art

[0004] Oxide semiconductor transistors, which form a channel in an oxide semiconductor layer, have excellent characteristics such as extremely low channel leakage current during the off-state operation, i.e., off-leakage current. Therefore, for example, studies have been conducted on the use of oxide semiconductor transistors as switching transistors in memory cells of dynamic random access memory (DRAM). By using oxide semiconductor transistors as switching transistors in DRAM, it is expected that the charge retention characteristics of the memory cells will be improved.

[0005] When an oxide semiconductor transistor is used as a switching transistor in a memory cell, it is preferable to also reduce leakage current of the capacitor insulating film of the memory cell capacitor. By reducing leakage current of the capacitor insulating film, the charge retention characteristics of the memory cell are improved. Summary of the Invention

[0006] An embodiment of the present invention provides a semiconductor memory device including a capacitor insulating film with low leakage current.

[0007] The semiconductor storage device of the embodiment includes a first conductive layer, a second conductive layer, a first oxide semiconductor layer provided between the first conductive layer and the second conductive layer, a first gate electrode surrounding the first oxide semiconductor layer, a first gate insulating film provided between the first oxide semiconductor layer and the first gate electrode, a first electrode provided in a first direction from the first conductive layer toward the second conductive layer with respect to the second conductive layer, electrically connected to the second conductive layer, and containing titanium (Ti), a second electrode surrounding the first electrode and containing titanium (Ti), a first capacitor insulating film provided between the first electrode and the second electrode, containing a first region and a second region between the first region and the second electrode, the atomic concentration of titanium (Ti) in the second region being higher than the atomic concentration of titanium (Ti) in the first region, a third conductive layer electrically connected to the first conductive layer, a fourth conductive layer provided in the first direction with respect to the third conductive layer, a second oxide semiconductor layer provided between the third conductive layer and the fourth conductive layer, a second gate electrode surrounding the second oxide semiconductor layer, a second gate insulating film provided between the second oxide semiconductor layer and the second gate electrode, a third electrode provided in the first direction with respect to the fourth conductive layer, electrically connected to the fourth conductive layer, and containing titanium (Ti), a fourth electrode surrounding the third electrode and containing titanium (Ti), and a second capacitor insulating film provided between the third electrode and the fourth electrode, containing a third region and a fourth region between the third region and the fourth electrode, the atomic concentration of titanium (Ti) in the fourth region being higher than the atomic concentration of titanium (Ti) in the third region. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of the semiconductor storage device of the first embodiment.

[0009] Figure 2 is a schematic cross-sectional view of an array of memory cells of the semiconductor storage device of the first embodiment.

[0010] Figure 3 is a schematic cross-sectional view of an array of memory cells of the semiconductor storage device of the first embodiment.

[0011] Figure 4 is an enlarged schematic cross-sectional view of an array of memory cells of the semiconductor storage device of the first embodiment.

[0012] Figure 5 (a), (b) are enlarged schematic cross-sectional views of an array of memory cells of the semiconductor storage device of the first embodiment.

[0013] Figure 6(a) and (b) are enlarged schematic cross-sectional views of the memory cell array of the semiconductor memory device according to the first embodiment.

[0014] Figures 7-23 It is a schematic cross-sectional view showing a method for manufacturing the memory cell array according to the first embodiment.

[0015] Figure 24 It is an enlarged schematic cross-sectional view of a memory cell array of a semiconductor memory device according to a comparative example.

[0016] Figure 25 (a) and (b) are diagrams for explaining the operation and effects of the semiconductor memory device according to the first embodiment.

[0017] Figure 26 It is an enlarged schematic cross-sectional view of a memory cell array of a semiconductor memory device according to a second embodiment.

[0018] Explanation of symbols

[0019] 11. First source electrode (first conductive layer)

[0020] 12. First drain electrode (second conductive layer)

[0021] 13. First oxide semiconductor layer

[0022] 14 first gate electrode

[0023] 15. First gate insulating film

[0024] 16. First storage node electrode (first electrode)

[0025] 17. First plate electrode (second electrode)

[0026] 18. First capacitor insulating film

[0027] 18a First low concentration region (first region)

[0028] 18b First high concentration region (second region)

[0029] 21 second source electrode (third conductive layer)

[0030] 22 second drain electrode (fourth conductive layer)

[0031] 23. Second oxide semiconductor layer

[0032] 24 second gate electrode

[0033] 25 second gate insulating film

[0034] 26 Second storage node electrode (third electrode)

[0035] 27. Second plate electrode (fourth electrode)

[0036] 28 Second capacitor insulating film

[0037] 28a Second low concentration area (third area)

[0038] 28b Second highest concentration area (fourth area)

[0039] 29 Insulation layer

[0040] 30 silicon substrate (substrate)

[0041] 32 wiring layers

[0042] 100 Semiconductor memory (semiconductor storage device) DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or similar components are denoted by the same reference numerals, and description of components that have been described once will be omitted as appropriate.

[0044] In addition, in this specification, the terms "upper" and "lower" are sometimes used for convenience. However, "upper" and "lower" are terms that indicate relative positional relationships within the drawings and do not define positional relationships with respect to gravity.

[0045] In this specification, qualitative and quantitative analysis of the chemical composition of components constituting a semiconductor memory device can be performed, for example, using secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford back-scattering spectroscopy (RBS). Furthermore, measurement of the thickness of components constituting a semiconductor memory device, the distance between components, and the like can be performed, for example, using a transmission electron microscope (TEM).

[0046] (First embodiment)

[0047] A semiconductor memory device according to a first embodiment includes: a first conductive layer; a second conductive layer; a first oxide semiconductor layer provided between the first conductive layer and the second conductive layer; a first gate electrode surrounding the first oxide semiconductor layer; a first gate insulating film provided between the first oxide semiconductor layer and the first gate electrode; a first electrode provided along a first direction from the first conductive layer toward the second conductive layer relative to the second conductive layer, electrically connected to the second conductive layer, and comprising titanium (Ti); a second electrode surrounding the first electrode and comprising titanium (Ti); a first capacitor insulating film provided between the first electrode and the second electrode, comprising a first region and a second region between the first region and the second electrode, the atomic concentration of titanium (Ti) in the second region being higher than the atomic concentration of titanium (Ti) in the first region. degree; a third conductive layer electrically connected to the first conductive layer; a fourth conductive layer arranged along the first direction relative to the third conductive layer; a second oxide semiconductor layer arranged between the third conductive layer and the fourth conductive layer; a second gate electrode surrounding the second oxide semiconductor layer; a second gate insulating film arranged between the second oxide semiconductor layer and the second gate electrode; a third electrode arranged along the first direction relative to the fourth conductive layer, electrically connected to the fourth conductive layer, and containing titanium (Ti); a fourth electrode surrounding the third electrode and containing titanium (Ti); and a second capacitor insulating film arranged between the third electrode and the fourth electrode, including a third region and a fourth region between the third region and the fourth electrode, the atomic concentration of titanium (Ti) in the fourth region being higher than the atomic concentration of titanium (Ti) in the third region.

[0048] The semiconductor memory device of the first embodiment is a semiconductor memory 100. The semiconductor memory device of the first embodiment is a DRAM. The semiconductor memory 100 uses an oxide semiconductor transistor as a switching transistor of a memory cell.

[0049] Figure 1 This is a block diagram of the semiconductor memory device according to the first embodiment.

[0050] like Figure 1 As shown in FIG, the semiconductor memory 100 includes a memory cell array 110, a word line driver circuit 111, a row decoder circuit 112, a sense amplifier circuit 113, a column decoder circuit 114, and a control circuit 115.

[0051] Figure 2 and Figure 3 This is a schematic cross-sectional view of a memory cell array of the semiconductor memory device according to the first embodiment. Figure 2 is a cross-sectional view of a surface including the first direction and the second direction, Figure 3 It is a cross-sectional view of a surface including a first direction and a third direction. Figure 2 and Figure 3The second direction intersects the first direction. The second direction is, for example, Figure 2 and Figure 3 The first direction is perpendicular to the second direction, for example. The third direction intersects the first direction and the second direction, for example. The third direction is perpendicular to the first direction and the second direction, for example.

[0052] The memory cell array 110 of the first embodiment has a three-dimensional structure in which memory cells are three-dimensionally arranged. The memory cell array 110 includes a first memory cell MC1 and a second memory cell MC2.

[0053] Figure 4 、 Figure 5 and Figure 6 It is an enlarged schematic cross-sectional view of the memory cell array of the semiconductor memory device according to the first embodiment. Figure 4 It is a cross-sectional view including the first memory cell MC1 and the second memory cell MC2.

[0054] Figure 5 is a cross-sectional view of the first memory cell MC1. Figure 5 (a) Yes Figure 4 AA' section. Figure 5 (b) Yes Figure 4 BB' section.

[0055] Figure 6 is a cross-sectional view of the second memory cell MC2. Figure 6 (a) Yes Figure 4 CC' section. Figure 6 (b) Yes Figure 4 DD' section.

[0056] The first memory cell MC1 includes a first source electrode 11, a first drain electrode 12, a first oxide semiconductor layer 13, a first gate electrode 14, a first gate insulating film 15, a first storage node electrode 16, a first plate electrode 17, and a first capacitor insulating film 18. The first capacitor insulating film 18 includes a first low-concentration region 18a and a first high-concentration region 18b.

[0057] The first source electrode 11 is an example of a first conductive layer. The first drain electrode 12 is an example of a second conductive layer. The first storage node electrode 16 is an example of a first electrode. The first plate electrode 17 is an example of a second electrode. The first low-concentration region 18a is an example of a first region. The first high-concentration region 18b is an example of a second region.

[0058] The second memory cell MC2 includes a second source electrode 21, a second drain electrode 22, a second oxide semiconductor layer 23, a second gate electrode 24, a second gate insulating film 25, a second storage node electrode 26, a second plate electrode 27, a second capacitor insulating film 28, and an insulating layer 29. The second capacitor insulating film 28 includes a second low-concentration region 28a and a second high-concentration region 28b.

[0059] The second source electrode 21 is an example of a third conductive layer. The second drain electrode 22 is an example of a fourth conductive layer. The second storage node electrode 26 is an example of a third electrode. The second plate electrode 27 is an example of a fourth electrode. The second low-concentration region 28a is an example of a third region. The second high-concentration region 28b is an example of a fourth region.

[0060] The memory cell array 110 includes a silicon substrate 30, a wiring layer 32, and an interlayer insulating layer 34. The silicon substrate 30 is an example of a substrate.

[0061] The memory cell array 110 includes a plurality of wiring layers 32, a plurality of first gate electrodes 14, and a plurality of second gate electrodes 24 on a silicon substrate 30. The wiring layers 32 extend in the second direction, and the first gate electrodes 14 and the second gate electrodes 24 extend in the third direction.

[0062] The plurality of wiring layers 32 function as bit lines of the semiconductor memory 100. The plurality of first gate electrodes 14 and the plurality of second gate electrodes 24 function as word lines of the semiconductor memory 100.

[0063] The plurality of first gate electrodes 14 and the plurality of second gate electrodes 24 are electrically connected to the row decoder circuit 112. The plurality of wiring layers 32 are electrically connected to the sense amplifier circuit 113.

[0064] The row decoder circuit 112 selects the first gate electrode 14 or the second gate electrode 24 according to an input row address signal. The word line drive circuit 111 applies a predetermined voltage to the first gate electrode 14 or the second gate electrode 24 selected by the row decoder circuit 112 .

[0065] The column decoder circuit 114 has a function of selecting a wiring layer 32 according to an input column address signal. The sense amplifier circuit 113 has a function of applying a predetermined voltage to the wiring layer 32 selected by the column decoder circuit 114. It also has a function of detecting and amplifying the potential of the selected wiring layer 32.

[0066] The control circuit 115 has a function of controlling the word line driving circuit 111 , the row decoder circuit 112 , the sense amplifier circuit 113 , the column decoder circuit 114 , and other circuits not shown.

[0067] The word line driver circuit 111 , row decoder circuit 112 , sense amplifier circuit 113 , column decoder circuit 114 , and control circuit 115 are formed of, for example, transistors and wiring (not shown).

[0068] The first memory cell MC1 is disposed on the silicon substrate 30. The first memory cell MC1 is disposed between the silicon substrate 30 and the second memory cell MC2.

[0069] The first memory cell MC1 includes a first source electrode 11, a first drain electrode 12, a first oxide semiconductor layer 13, a first gate electrode 14, a first gate insulating film 15, a first storage node electrode 16, a first plate electrode 17, and a first capacitor insulating film 18. The first capacitor insulating film 18 includes a first low-concentration region 18a and a first high-concentration region 18b.

[0070] The first source electrode 11 , the first drain electrode 12 , the first oxide semiconductor layer 13 , the first gate electrode 14 , and the first gate insulating film 15 constitute a switching transistor of the first memory cell MC1 .

[0071] A direction from the first source electrode 11 toward the first drain electrode 12 is a first direction.

[0072] The first source electrode 11 is a conductive layer. The first source electrode 11 is, for example, a metal or a metal compound. The first source electrode 11 includes, for example, indium (In), tin (Sn), and oxygen (O). The first source electrode 11 includes, for example, indium tin oxide.

[0073] The first drain electrode 12 is a conductive layer. The first drain electrode 12 is, for example, a metal or a metal compound. The first drain electrode 12 includes, for example, indium (In), tin (Sn), and oxygen (O). The first drain electrode 12 includes, for example, indium tin oxide.

[0074] The first oxide semiconductor layer 13 is provided between the first source electrode 11 and the first drain electrode 12 .

[0075] When the switching transistor is turned on, a channel serving as a current path is formed in the first oxide semiconductor layer 13. The first oxide semiconductor layer 13 extends in a first direction. When the switching transistor is turned on, current flows in the first oxide semiconductor layer 13 in the first direction.

[0076] The first oxide semiconductor layer 13 is an oxide semiconductor. For example, the first oxide semiconductor layer 13 includes indium (In) and zinc (Zn). For example, the first oxide semiconductor layer 13 includes indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

[0077] The first oxide semiconductor layer 13 has, for example, a cylindrical shape.

[0078] The first gate electrode 14 is provided to face the first oxide semiconductor layer 13. The first gate electrode 14 surrounds the first oxide semiconductor layer 13. The first gate electrode 14 is provided around the first oxide semiconductor layer 13.

[0079] The first gate electrode 14 is, for example, a metal, a metal compound, or a semiconductor, and includes, for example, tungsten (W).

[0080] The length of the first gate electrode 14 in the first direction is, for example, 20 nm to 100 nm.

[0081] The first gate insulating film 15 is provided between the first oxide semiconductor layer 13 and the first gate electrode 14. The first gate insulating film 15 surrounds the first oxide semiconductor layer 13.

[0082] The first gate insulating film 15 is made of, for example, oxide or oxynitride, silicon oxide or aluminum oxide, and has a thickness of, for example, 2 nm to 10 nm.

[0083] The first storage node electrode 16 , the first plate electrode 17 , and the first capacitor insulating film 18 constitute a capacitor of the first memory cell MC1 .

[0084] The first storage node electrode 16 is disposed along a first direction relative to the first drain electrode 12. The first storage node electrode 16 is disposed between the first drain electrode 12 and the silicon substrate 30. The first storage node electrode 16 is electrically connected to the first drain electrode 12.

[0085] The first storage node electrode 16 is a conductor, such as a metal or a metal compound.

[0086] First storage node electrode 16 includes titanium (Ti). For example, first storage node electrode 16 includes titanium (Ti) and nitrogen (N). For example, first storage node electrode 16 primarily comprises titanium (Ti) and nitrogen (N). First storage node electrode 16 primarily comprises titanium (Ti) and nitrogen (N) meaning that first storage node electrode 16 does not contain any element with a higher atomic concentration than titanium (Ti) or nitrogen (N). For example, first storage node electrode 16 includes titanium nitride. First storage node electrode 16 is, for example, titanium nitride.

[0087] The first storage node electrode 16 is, for example, in a pillar shape. The first storage node electrode 16 is, for example, in a cylindrical shape.

[0088] The first plate electrode 17 is disposed along a first direction of the first storage node electrode 16. The first plate electrode 17 is disposed between the first storage node electrode 16 and the silicon substrate 30. The first plate electrode 17 surrounds the first storage node electrode 16. The first storage node electrode 16 is disposed inside the first plate electrode 17.

[0089] The first plate-shaped electrode 17 is a conductor, such as a metal or a metal compound.

[0090] The first plate electrode 17 includes titanium (Ti). For example, the first plate electrode 17 includes titanium (Ti) and nitrogen (N). For example, the first plate electrode 17 primarily includes titanium (Ti) and nitrogen (N). The first plate electrode 17 primarily includes titanium (Ti) and nitrogen (N) meaning that no element with a higher atomic concentration than titanium (Ti) or nitrogen (N) is present in the first plate electrode 17. For example, the first plate electrode 17 includes titanium nitride. For example, the first plate electrode 17 is titanium nitride.

[0091] The first plate electrode 17 is, for example, cylindrical.

[0092] The first capacitor insulating film 18 is provided between the first storage node electrode 16 and the first plate electrode 17. The first capacitor insulating film 18 includes a first low concentration region 18a and a first high concentration region 18b. The first high concentration region 18b is provided between the first low concentration region 18a and the first plate electrode 17.

[0093] The atomic concentration of titanium (Ti) in the first high concentration region 18b is higher than the atomic concentration of titanium (Ti) in the first low concentration region 18a. The atomic concentration of titanium (Ti) in the first high concentration region 18b is, for example, 10 times or more the atomic concentration of titanium (Ti) in the first low concentration region 18a. The atomic concentration of titanium (Ti) in the first high concentration region 18b is, for example, 1×10 17 cm -3 ~1×10 20 cm -3 .

[0094] The first capacitor insulating film 18 is, for example, a metal oxide and contains at least one metal element selected from the group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), yttrium (Y), lanthanum (La), and tantalum (Ta), and oxygen (O).

[0095] The first capacitor insulating film 18 includes, for example, zirconium oxide, hafnium oxide, hafnium silicate, aluminum oxide, yttrium oxide, lanthanum oxide, or tantalum oxide. The first capacitor insulating film 18 is, for example, a laminated film formed by sequentially laminating zirconium oxide, aluminum oxide, and zirconium oxide.

[0096] The thickness of the first capacitor insulating film 18 is, for example, 1 nm to 20 nm. The thickness of the first capacitor insulating film 18 in the second direction is, for example, 1 nm to 20 nm. The thickness of the first capacitor insulating film 18 in the first direction is, for example, 1 nm to 20 nm.

[0097] The second memory cell MC2 is provided on the silicon substrate 30. The second memory cell MC2 is provided on the first memory cell MC1. The second memory cell MC2 and the silicon substrate 30 sandwich the first memory cell MC1.

[0098] The second memory cell MC2 includes a second source electrode 21, a second drain electrode 22, a second oxide semiconductor layer 23, a second gate electrode 24, a second gate insulating film 25, a second storage node electrode 26, a second plate electrode 27, a second capacitor insulating film 28, and an insulating layer 29. The second capacitor insulating film 28 includes a second low-concentration region 28a and a second high-concentration region 28b.

[0099] The second source electrode 21 , the second drain electrode 22 , the second oxide semiconductor layer 23 , the second gate electrode 24 , and the second gate insulating film 25 constitute a switching transistor of the second memory cell MC2 .

[0100] A direction from the second source electrode 21 toward the second drain electrode 22 is a first direction.

[0101] The second source electrode 21 is a conductive layer. The second source electrode 21 is, for example, a metal or a metal compound. The second source electrode 21 includes, for example, indium (In), tin (Sn), and oxygen (O). The second source electrode 21 includes, for example, indium tin oxide.

[0102] The second drain electrode 22 is a conductive layer. The second drain electrode 22 is, for example, a metal or a metal compound. The second drain electrode 22 includes, for example, indium (In), tin (Sn), and oxygen (O). The second drain electrode 22 includes, for example, indium tin oxide.

[0103] The second oxide semiconductor layer 23 is provided between the second source electrode 21 and the second drain electrode 22 .

[0104] In the second oxide semiconductor layer 23, a channel serving as a current path is formed when the switching transistor is turned on. The second oxide semiconductor layer 23 extends in the first direction. When the switching transistor is turned on, current flows in the second oxide semiconductor layer 23 in the first direction.

[0105] The second oxide semiconductor layer 23 is an oxide semiconductor. The second oxide semiconductor layer 23 contains, for example, indium (In) and zinc (Zn). The second oxide semiconductor layer 23 contains, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

[0106] The second oxide semiconductor layer 23 is, for example, cylindrical.

[0107] The second gate electrode 24 is provided facing the second oxide semiconductor layer 23. The second gate electrode 24 surrounds the second oxide semiconductor layer 23. The second gate electrode 24 is provided around the second oxide semiconductor layer 23.

[0108] The second gate electrode 24 is, for example, a metal, a metal compound, or a semiconductor. The second gate electrode 24 contains, for example, tungsten (W).

[0109] The length of the second gate electrode 24 in the first direction is, for example, 20 nm to 100 nm.

[0110] The second gate insulating film 25 is provided between the second oxide semiconductor layer 23 and the second gate electrode 24. The second gate insulating film 25 surrounds the second oxide semiconductor layer 23.

[0111] The second gate insulating film 25 is, for example, an oxide or an oxynitride. The second gate insulating film 25 contains, for example, silicon oxide or aluminum oxide. The thickness of the second gate insulating film 25 is, for example, 2 nm to 10 nm.

[0112] The second storage node electrode 26, the second plate electrode 27, and the second capacitor insulating film 28 constitute a capacitor of the second memory cell MC2.

[0113] The second storage node electrode 26 is provided in the first direction with respect to the second drain electrode 22. The second storage node electrode 26 is electrically connected to the second drain electrode 22.

[0114] The second storage node electrode 26 is a conductor. The second storage node electrode 26 is, for example, a metal or a metal compound.

[0115] The second storage node electrode 26 contains titanium (Ti). The second storage node electrode 26 contains, for example, titanium (Ti) and nitrogen (N). The second storage node electrode 26 contains, for example, titanium (Ti) and nitrogen (N) as main components. The second storage node electrode 26 contains titanium (Ti) and nitrogen (N) as main components means that there is no element having a higher atomic concentration than titanium (Ti) or nitrogen (N) in the second storage node electrode 26. The second storage node electrode 26 contains, for example, titanium nitride. The second storage node electrode 26 is, for example, titanium nitride.

[0116] The second storage node electrode 26 is, for example, columnar. The second storage node electrode 26 is, for example, cylindrical.

[0117] The second plate electrode 27 is disposed along the first direction of the second storage node electrode 26. The second plate electrode 27 sandwiches the second storage node electrode 26 with the silicon substrate 30. The second plate electrode 27 surrounds the second storage node electrode 26. The second storage node electrode 26 is disposed inside the second plate electrode 27.

[0118] The second plate-type electrode 27 is a conductor, such as a metal or a metal compound.

[0119] The second plate electrode 27 includes titanium (Ti). For example, the second plate electrode 27 includes titanium (Ti) and nitrogen (N). For example, the second plate electrode 27 primarily includes titanium (Ti) and nitrogen (N). The fact that the second plate electrode 27 primarily includes titanium (Ti) and nitrogen (N) means that no element with a higher atomic concentration than titanium (Ti) or nitrogen (N) is present in the second plate electrode 27. For example, the second plate electrode 27 includes titanium nitride. For example, the first plate electrode 17 is titanium nitride.

[0120] The second plate electrode 27 has, for example, a cylindrical shape.

[0121] The second capacitor insulating film 28 is provided between the second storage node electrode 26 and the second plate electrode 27. Between the silicon substrate 30 and the second capacitor insulating film 28, the first capacitor insulating film 18 is provided.

[0122] The second capacitor insulating film 28 includes a second low-concentration region 28 a and a second high-concentration region 28 b . The second high-concentration region 28 b is provided between the second low-concentration region 28 a and the second plate-type electrode 27 .

[0123] The atomic concentration of titanium (Ti) in the second high concentration region 28b is higher than the atomic concentration of titanium (Ti) in the second low concentration region 28a. The atomic concentration of titanium (Ti) in the second high concentration region 28b is, for example, 10 times or more the atomic concentration of titanium (Ti) in the second low concentration region 28a. The atomic concentration of titanium (Ti) in the second high concentration region 28b is, for example, 1×10 17 cm -3 ~1×10 20 cm -3 .

[0124] The second capacitor insulating film 28 is, for example, a metal oxide and contains at least one metal element selected from the group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), yttrium (Y), lanthanum (La), and tantalum (Ta), and oxygen (O).

[0125] The second capacitor insulating film 28 contains, for example, zirconium oxide, hafnium oxide, hafnium silicate, aluminum oxide, yttrium oxide, lanthanum oxide, or tantalum oxide. The second capacitor insulating film 28 is, for example, zirconium oxide, hafnium oxide, hafnium silicate, aluminum oxide, yttrium oxide, lanthanum oxide, or tantalum oxide. The second capacitor insulating film 28 is, for example, a laminated film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order.

[0126] The thickness of the second capacitor insulating film 28 is, for example, 1 nm to 20 nm. The thickness of the second capacitor insulating film 28 in the second direction is, for example, 1 nm to 20 nm.

[0127] The insulating layer 29 is provided between the second storage node electrode 26 and the second plate electrode 27 in the first direction. The insulating layer 29 is in contact with the second storage node electrode 26 and the second plate electrode 27. The insulating layer 29 electrically separates the second storage node electrode 26 and the second plate electrode 27. The thickness of the insulating layer 29 in the first direction is, for example, thicker than the thickness of the second capacitor insulating film 28 in the second direction.

[0128] The material of the insulating layer 29 is different from the material of the second capacitor insulating film 28. The chemical composition of the insulating layer 29 is different from the chemical composition of the second capacitor insulating film 28. The insulating layer 29 contains, for example, silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 29 is silicon oxide, silicon nitride, or silicon oxynitride.

[0129] The interlayer insulating layer 34 has a function of electrically separating members constituting the memory cell array 110 from each other. The interlayer insulating layer 34 is, for example, silicon oxide.

[0130] Next, one example of a manufacturing method of the memory cell array 110 of the first embodiment will be described.

[0131] Figures 7-23 is a schematic cross-sectional view that schematically shows a manufacturing method of a memory cell array of the first embodiment. Figures 7-23 is a cross section corresponding to Figure 4 .

[0132] First, a first silicon oxide film 42, a first titanium nitride film 44, and a second silicon oxide film 46 are formed on the silicon substrate 30. The first silicon oxide film 42, the first titanium nitride film 44, and the second silicon oxide film 46 are formed, for example, by a chemical vapor deposition (CVD) method.

[0133] Next, an opening portion 48 reaching the first titanium nitride film 44 is formed in the second silicon oxide film 46. Figure 7 The opening portion 48 is formed, for example, using a photolithography method and a reactive ion etching (RIE) method.

[0134] Next, a second titanium nitride film 50 ( Figure 8 The second titanium nitride film 50 is formed by, for example, a CVD method.

[0135] Next, a first zirconium oxide film 52 is formed on the second titanium nitride film 50 ( Figure 9 The first zirconium oxide film 52 is formed by, for example, CVD. During the formation of the first zirconium oxide film 52, titanium (Ti) in the second titanium nitride film 50 is absorbed into the first zirconium oxide film 52, forming a first high-concentration region 52x with a high titanium concentration.

[0136] Next, a third titanium nitride film 54 ( Figure 10 The opening 48 is filled with a third titanium nitride film 54. The third titanium nitride film 54 is formed by, for example, CVD.

[0137] Next, the third titanium nitride film 54, the zirconium oxide film 52, and the second titanium nitride film 50 on the second silicon oxide film 46 are removed ( Figure 11 The third titanium nitride film 54, the first zirconium oxide film 52, and the second titanium nitride film 50 are removed by, for example, RIE or chemical mechanical polishing (CMP).

[0138] Next, using a known process technology, a first source electrode 11, a first drain electrode 12, a first oxide semiconductor layer 13, a first gate electrode 14, a first gate insulating film 15, a second source electrode 21, a second drain electrode 22, a second oxide semiconductor layer 23, a second gate electrode 24, a second gate insulating film 25, a wiring layer 32, and a third silicon oxide film 56 are formed ( Figure 12 ).

[0139] Next, an opening 58 ( Figure 13 The opening 58 is formed using, for example, photolithography and RIE.

[0140] Next, a fourth titanium nitride film 60 ( Figure 14 ) The fourth titanium nitride film 60 is formed by, for example, a CVD method.

[0141] Next, the fourth titanium nitride film 60 on the third silicon oxide film 56 and at the bottom of the opening 58 is removed ( Figure 15 ) The fourth titanium nitride film 60 is removed by, for example, RIE.

[0142] Next, a second zirconium oxide film 62 is formed on the fourth titanium nitride film 60 ( Figure 16). The second zirconium oxide film 62 is formed, for example, by a CVD method. In the formation of the second zirconium oxide film 62, titanium (Ti) in the fourth titanium nitride film 60 is taken into the second zirconium oxide film 62, forming a second high concentration region 62x having a high titanium concentration.

[0143] Next, the second zirconium oxide film 62 on the third silicon oxide film 56 and the bottom of the opening portion 58 is removed (S6). Figure 17 ). The second zirconium oxide film 62 is removed, for example, by an RIE method.

[0144] Next, a fifth titanium nitride film 64 is formed on the second zirconium oxide film 62 (S7). Figure 18 The opening portion 58 is buried with the fifth titanium nitride film 64. The fifth titanium nitride film 64 is formed, for example, by a CVD method.

[0145] Next, the fifth titanium nitride film 64 on the third silicon oxide film 56 is removed (S8). Figure 19 ). The fifth titanium nitride film 64 is removed, for example, by a CMP method.

[0146] Next, a part of the fifth titanium nitride film 64 is removed (S9). Figure 20 ). The fifth titanium nitride film 64 is removed, for example, by an RIE method using a photoresist mask 66 formed using a photolithography method as a mask material.

[0147] Next, a fourth silicon oxide film 68 is formed on the fifth titanium nitride film 64 (S10). Figure 21 ). The fourth silicon oxide film 68 is formed, for example, by a CVD method.

[0148] Next, a part of the fourth silicon oxide film 68 is removed (S11). Figure 22 ). The fourth silicon oxide film 68 is removed, for example, by an RIE method.

[0149] Next, a sixth titanium nitride film 70 and a fifth silicon oxide film 72 are formed on the fourth silicon oxide film 68 and the third silicon oxide film 56 (S12). Figure 23 ). The sixth titanium nitride film 70 and the fifth silicon oxide film 72 are formed, for example, by a CVD method.

[0150] By the above manufacturing method, the memory cell array 110 shown in FIG. 1 is formed. Figure 4

[0151] Next, the operation and effects of the semiconductor storage device of the first embodiment will be described.

[0152] ​Oxide semiconductor transistors, which form a channel in an oxide semiconductor layer, have the excellent characteristic of extremely low channel leakage current during the off-state operation, i.e., off-leakage current. By using oxide semiconductor transistors as switching transistors in DRAM, charge leakage from the memory cell is reduced, and the charge retention characteristics of the memory cell are expected to be improved. This improved charge retention characteristic of the memory cell can, for example, extend the regeneration time of the DRAM, thereby reducing the DRAM's power consumption.

[0153] If the off-leakage current of the switching transistor is reduced, the leakage current of the capacitor insulating film may replace the off-leakage current of the switching transistor and become the main cause of charge leakage from the memory cell. Therefore, it is preferable to reduce the leakage current of the capacitor insulating film.

[0154] Figure 24 It is an enlarged schematic cross-sectional view of a memory cell array of a semiconductor memory device according to a comparative example. Figure 24 The first embodiment Figure 4 The corresponding figure.

[0155] The memory cell array 910 of the comparative example includes a first memory cell MC1 and a second memory cell MC2 .

[0156] The memory cell array 910 of the comparative example differs from the memory cell array 110 of the first embodiment in that the first storage node electrode 16 of the first memory cell MC1 surrounds the first plate electrode 17. In other words, the first plate electrode 17 is disposed inside the first storage node electrode 16, which is different from the memory cell array 110 of the first embodiment.

[0157] The first capacitor insulating film 18 of the memory cell array 910 of the comparative example includes a first low-concentration region 18 x and a first high-concentration region 18 y . The first high-concentration region 18 y is provided between the first low-concentration region 18 x and the first plate electrode 17 .

[0158] The memory cell array 910 of the comparative example differs from the memory cell array 110 of the first embodiment in that the second storage node electrode 26 of the second memory cell MC2 surrounds the second plate electrode 27. In other words, the second plate electrode 27 is disposed inside the second storage node electrode 26, which is different from the memory cell array 110 of the first embodiment.

[0159] The second capacitor insulating film 28 of the memory cell array 910 of the comparative example includes a second low-concentration region 28x and a second high-concentration region 28y. The second high-concentration region 28y is provided between the second low-concentration region 28x and the second storage node electrode 26. The second memory cell MC2 of the comparative example differs from the second memory cell MC2 of the first embodiment in that the region with a high atomic concentration of titanium (Ti) in the second capacitor insulating film 28 is provided on the second storage node electrode 26 side rather than the second plate electrode 27 side.

[0160] Figure 25 It is an explanatory diagram of the operation and effect of the semiconductor memory device according to the first embodiment. Figure 25 This is a graph showing the evaluation results of the leakage current of the capacitor insulating film. Figure 25 (a) is a diagram showing the structure of an evaluation sample. Figure 25 (b) means Figure 25 (a) is a graph showing the voltage-current characteristics of the evaluation sample.

[0161] like Figure 25 As shown in (a), the evaluation sample was fabricated by forming a zirconium oxide film on a lower titanium nitride film, and then forming an upper titanium nitride film on top of the zirconium oxide film. When the zirconium oxide film is formed on the lower titanium nitride film, titanium from the lower titanium nitride film is absorbed into the zirconium oxide film. As a result, a high titanium concentration region with a high titanium atomic concentration is formed on the lower titanium nitride film side of the zirconium oxide film.

[0162] like Figure 25 As shown in (a), the upper titanium nitride film and the lower titanium nitride film were used as electrodes, a gate voltage Vg was applied to the upper titanium nitride film side, and the leakage current of the zirconium oxide film was measured. Figure 25 (b) is the evaluation result.

[0163] like Figure 25 As shown in (b), the voltage-current characteristics of the zirconium oxide film have a dependency on the direction of application of the gate voltage Vg. The leakage current when the gate voltage Vg is positive is larger than the leakage current when the gate voltage Vg is negative.

[0164] The dependence of the leakage current on the direction of gate voltage Vg is believed to be due to the presence of the high titanium concentration region. When a positive voltage is applied to the electrode on the high titanium concentration region side, the leakage current is reduced compared to when a positive voltage is applied to the electrode on the low titanium concentration region side.

[0165] Consider the case where a positive voltage is applied to first plate electrode 17 and second plate electrode 27 in memory cell array 910 of the comparative example to activate the memory cell. In first memory cell MC1, a first high-concentration region 18y having a high atomic concentration of titanium is provided on the first plate electrode 17 side of first capacitor insulating film 18. Therefore, in first memory cell MC1, leakage current from first capacitor insulating film 18 can be suppressed when a positive voltage is applied to first plate electrode 17. Consequently, the charge retention characteristics of first memory cell MC1 are improved.

[0166] On the other hand, in the second memory cell MC2 of the memory cell array 910 of the comparative example, a second high-concentration region 28y having a high atomic concentration of titanium is provided on the second storage node electrode 26 side of the second capacitor insulating film 28. Therefore, in the second memory cell MC2, when a positive voltage is applied to the second plate electrode 27, the leakage current of the second capacitor insulating film 28 increases compared to the first memory cell MC1. Consequently, there is a possibility that the charge retention characteristics of the second memory cell MC2 may deteriorate.

[0167] In the second memory cell MC2 of the memory cell array 910 of the comparative example, the capacitor structure is such that the second capacitor insulating film 28 is formed on the second storage node electrode 26 to form the capacitor. Therefore, it is inevitable that a second high concentration region 28y having a high titanium atomic concentration is formed on the second storage node electrode 26 side of the second capacitor insulating film 28.

[0168] In the memory cell array 110 of the first embodiment, a case where a positive voltage is applied to the first plate electrode 17 and the second plate electrode 27 to activate the memory cell is considered. In the first memory cell MC1, a first high-concentration region 18b having a high atomic concentration of titanium is provided on the first plate electrode 17 side of the first capacitor insulating film 18. Therefore, in the first memory cell MC1, leakage current from the first capacitor insulating film 18 can be suppressed when a positive voltage is applied to the first plate electrode 17. Consequently, the charge retention characteristics of the first memory cell MC1 are improved.

[0169] In the second memory cell MC2 of the memory cell array 110 according to the first embodiment, a second high-concentration region 28b having a high titanium atomic concentration is provided on the second plate electrode 27 side of the second capacitor insulating film 28. Therefore, in the second memory cell MC2, leakage current from the second capacitor insulating film 28 can be suppressed when a positive voltage is applied to the second plate electrode 27. Consequently, similar to the first memory cell MC1, the charge retention characteristics of the second memory cell MC2 are improved.

[0170] In the memory cell array 110 of the first embodiment, both the first memory cell MC1 and the second memory cell MC2 have a region with a high titanium atomic concentration on the plate electrode side of the capacitor insulating film. Therefore, when a positive voltage is applied to the plate electrode to activate the memory cell, the charge retention characteristics of both the first memory cell MC1 and the second memory cell MC2 are improved.

[0171] Furthermore, when a metal oxide is used in the capacitor insulating film, if titanium (Ti) is added as an additive element, the equivalent oxide thickness (EOT) of the capacitor insulating film becomes thinner. Therefore, in the memory cell array 110 of the first embodiment, the increased capacitor capacitance increases the amount of charge retained by the memory cell, thereby improving the charge retention characteristics.

[0172] From the perspective of reducing the equivalent oxide film thickness of the first capacitor insulating film 18, the atomic concentration of titanium (Ti) in the first high-concentration region 18b is preferably 1×10 17 cm -3 More than 5×10 17 cm -3 Furthermore, from the perspective of reducing the equivalent oxide film thickness of the second capacitor insulating film 28, the atomic concentration of titanium (Ti) in the second high concentration region 28b is preferably 1×10 17 cm -3 More than 5×10 17 cm -3 above.

[0173] From the perspective of reducing the equivalent oxide film thickness of the first capacitor insulating film 18, the atomic concentration of titanium (Ti) in the first high-concentration region 18b is preferably 10 times or more, and more preferably 100 times, the atomic concentration of titanium (Ti) in the first low-concentration region 18a. 3 Furthermore, from the perspective of reducing the equivalent oxide film thickness of the second capacitor insulating film 28, the atomic concentration of titanium (Ti) in the second high concentration region 28b is preferably 10 times or more, and more preferably 100 times, the atomic concentration of titanium (Ti) in the second low concentration region 28a. 3 above.

[0174] From the viewpoint of suppressing the leakage current of the first capacitor insulating film 18, the atomic concentration of titanium (Ti) in the first high concentration region 18b of the first capacitor insulating film 18 is preferably 1×10 20 cm -3 Below, more preferably 1×10 19 cm -3From the viewpoint of suppressing the leakage current of the second capacitor insulating film 28, the atomic concentration of titanium (Ti) in the second high concentration region 28b of the second capacitor insulating film 28 is preferably 1×10 20 cm -3 Below, more preferably 1×10 19 cm -3 the following.

[0175] As described above, according to the first embodiment, a semiconductor memory device including a capacitor insulating film with low leakage current can be realized.

[0176] (Second embodiment)

[0177] The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that it does not include the first source electrode 11, the first drain electrode 12, the second source electrode 21, and the second drain electrode 22. Hereinafter, descriptions of the contents overlapping with the first embodiment will be partially omitted.

[0178] Figure 26 It is an enlarged schematic cross-sectional view of a memory cell array of a semiconductor memory device according to a second embodiment. Figure 26 The first embodiment Figure 4 The corresponding figure.

[0179] The memory cell array 210 of the second embodiment includes a first memory cell MC1 and a second memory cell MC2 .

[0180] The first memory cell MC1 includes a first oxide semiconductor layer 13, a first gate electrode 14, a first gate insulating film 15, a first storage node electrode 16, a first plate electrode 17, and a first capacitor insulating film 18. The first capacitor insulating film 18 includes a first low concentration region 18a and a first high concentration region 18b.

[0181] The first storage node electrode 16 is an example of a first electrode. The first plate electrode 17 is an example of a second electrode. The first low-concentration region 18a is an example of a first region. The first high-concentration region 18b is an example of a second region.

[0182] The second memory cell MC2 includes a second oxide semiconductor layer 23, a second gate electrode 24, a second gate insulating film 25, a second storage node electrode 26, a second plate electrode 27, a second capacitor insulating film 28, and an insulating layer 29. The second capacitor insulating film 28 includes a second low-concentration region 28a and a second high-concentration region 28b.

[0183] The second storage node electrode 26 is an example of a third electrode. The second plate electrode 27 is an example of a fourth electrode. The second low-concentration region 28a is an example of a third region. The second high-concentration region 28b is an example of a fourth region.

[0184] The memory cell array 110 includes a silicon substrate 30, a wiring layer 32, and an interlayer insulating layer 34. The silicon substrate 30 is an example of a substrate.

[0185] A portion of the wiring layer 32 is an example of a first conductive layer. A portion of the first storage node electrode 16 is an example of a second conductive layer.

[0186] A portion of the wiring layer 32 is an example of a third conductive layer. A portion of the second storage node electrode 26 is an example of a fourth conductive layer.

[0187] As described above, according to the second embodiment, similarly to the first embodiment, a semiconductor memory device including a capacitor insulating film with low leakage current can be realized.

[0188] In the first and second embodiments, the structure in which the gate electrode surrounds the oxide semiconductor layer is described as an example. However, the gate electrode may also be configured not to surround the oxide semiconductor layer.

[0189] Several embodiments of the present invention have been described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. For example, the constituent elements of one embodiment can be replaced or changed with the constituent elements of other embodiments. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: a first conductive layer; a second conductive layer; a first oxide semiconductor layer disposed between the first conductive layer and the second conductive layer; a first gate electrode surrounding the first oxide semiconductor layer; a first gate insulating film provided between the first oxide semiconductor layer and the first gate electrode; a first electrode, disposed relative to the second conductive layer and along a first direction from the first conductive layer toward the second conductive layer, electrically connected to the second conductive layer, and comprising titanium (Ti); a second electrode surrounding the first electrode and comprising titanium (Ti); a first capacitor insulating film provided between the first electrode and the second electrode, comprising a first region and a second region between the first region and the second electrode, wherein the atomic concentration of titanium (Ti) in the second region is higher than the atomic concentration of titanium (Ti) in the first region; a third conductive layer electrically connected to the first conductive layer; a fourth conductive layer, arranged along the first direction relative to the third conductive layer; a second oxide semiconductor layer disposed between the third conductive layer and the fourth conductive layer; a second gate electrode surrounding the second oxide semiconductor layer; a second gate insulating film provided between the second oxide semiconductor layer and the second gate electrode; a third electrode, disposed along the first direction relative to the fourth conductive layer, electrically connected to the fourth conductive layer, and comprising titanium (Ti); a fourth electrode surrounding the third electrode and comprising titanium (Ti); as well as The second capacitor insulating film is provided between the third electrode and the fourth electrode and includes a third region and a fourth region between the third region and the fourth electrode, wherein the atomic concentration of titanium (Ti) in the fourth region is higher than that in the third region.

2. The semiconductor memory device according to claim 1, wherein The atomic concentration of titanium (Ti) in the second region is 10 times or more the atomic concentration of titanium (Ti) in the first region, The atomic concentration of titanium (Ti) in the fourth region is 10 times or more the atomic concentration of titanium (Ti) in the third region.

3. The semiconductor memory device according to claim 1, wherein The atomic concentration of titanium (Ti) in the second region is 1×10 17 cm -3 above, The atomic concentration of titanium (Ti) in the fourth region is 1×10 17 cm -3 above.

4. The semiconductor memory device according to claim 1, further comprising an insulating layer provided between the third electrode and the fourth electrode in the first direction, in contact with the third electrode and the fourth electrode, and made of a material different from that of the second capacitor insulating film.

5. The semiconductor memory device according to claim 1, further comprising a substrate. The first capacitor insulating film is provided between the substrate and the second capacitor insulating film. The semiconductor memory device according to claim 1 , wherein: The first electrode, the second electrode, the third electrode, and the fourth electrode include nitrogen (N).

7. The semiconductor memory device according to claim 1, wherein The first capacitor insulating film and the second capacitor insulating film contain oxygen (O).

8. The semiconductor memory device according to claim 1, wherein The first capacitor insulating film and the second capacitor insulating film include at least one metal element selected from the group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), yttrium (Y), lanthanum (La), and tantalum (Ta).

9. The semiconductor memory device according to claim 1, further comprising a wiring layer extending in a second direction intersecting the first direction and electrically connected to the first conductive layer and the third conductive layer. The first gate electrode and the second gate electrode extend along a third direction intersecting the first direction and the second direction.

10. The semiconductor memory device according to claim 1, wherein The first oxide semiconductor layer and the second oxide semiconductor layer include indium (In) and zinc (Zn).

Images