A display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a display area, a peripheral circuit area, and an encapsulation area. The peripheral circuit area at least partially surrounds the display area, and the encapsulation area at least partially surrounds the peripheral circuit area. The display panel also includes a common light-emitting layer located at least in the display area, an encapsulation layer and a first planarization layer located in the display area and the peripheral circuit area, and an encapsulation structure located in the encapsulation area. Both the encapsulation layer and the first planarization layer are located on the side of the common light-emitting layer away from the substrate. Along the thickness direction of the display panel, the height of the first planarization layer is h1, and the height of the encapsulation structure is h2, wherein |h1-h2| / h2≤20%. This technical solution, by setting a planarization layer on the side of the common light-emitting layer away from the substrate, ensures that the height of the first planarization layer and the height of the encapsulation structure are approximately equal along the thickness direction of the display panel. This avoids the Newton's rings phenomenon caused by a height difference between the first planarization layer and the encapsulation structure, thus improving the display effect of the display panel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] In the existing display product, the height of the packaging structure is matched by the support column, and the support column and the packaging structure support the upper substrate together. Since the cathode is deposited on the whole surface, the cathode on the surface of the support column is easily scratched when the upper substrate is attached, which causes the difference in reflectivity between the scratched cathode and the surrounding cathode, thereby causing dark spot defects. In addition, due to the difference in the height of each support column, there is a height difference between the support column and the packaging structure, thereby causing Newton's ring, which affects the display effect of the product. SUMMARY

[0003] Embodiments of the present application provide a display panel and a display device. A first planar layer is arranged on the side of a common light-emitting layer away from a substrate, and the thickness of the first planar layer is approximately equal to the thickness of the packaging structure in the thickness direction of the display panel, thereby avoiding the generation of Newton's ring phenomenon due to the height difference between the first planar layer and the packaging structure, and improving the display effect of the display panel.

[0004] In a first aspect, embodiments of the present application provide a display panel. The display panel includes a display area, a peripheral circuit area, and a packaging area. The peripheral circuit area at least partially surrounds the display area. The packaging area at least partially surrounds the peripheral circuit area.

[0005] The display panel further includes a common light-emitting layer located at least in the display area, a packaging layer and a first planar layer located in the display area and the peripheral circuit area, and a packaging structure located in the packaging area. The packaging layer and the first planar layer are located on the side of the common light-emitting layer away from the substrate.

[0006] In the thickness direction of the display panel, the height of the first planar layer is h1, and the height of the packaging structure is h2, where |h1-h2| / h2≤20%.

[0007] In a second aspect, embodiments of the present application further provide a display device including the display panel of the first aspect.

[0008] The display panel provided by the application comprises at least a common light-emitting layer located in a display area, an encapsulation layer and a first planar layer located in the display area and a peripheral circuit area, and an encapsulation structure located in an encapsulation area. Thus, by arranging the first planar layer on the side of the common light-emitting layer away from the substrate, the first planar layer can be used as a protective layer of the common light-emitting layer, so as to avoid scratching the common light-emitting layer, for example, to avoid scratching the cathode in the common light-emitting layer, to avoid the difference in reflectivity between the scratched common light-emitting layer and the surrounding common light-emitting layer, and to avoid the phenomenon of dark spot defects. In addition, along the thickness direction of the display panel, the height of the first planar layer is h1, and the height of the encapsulation structure is h2. By setting |h1-h2| / h2≤20%, the height of the first planar layer is approximately equal to the height of the encapsulation structure, so as to avoid the Newton ring caused by the height difference between the first planar layer and the encapsulation structure, and improve the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some specific embodiments of the present application. For those skilled in the art, based on the basic concepts of device structure, driving method and manufacturing method disclosed and suggested by various embodiments of the present application, other structures and drawings can be expanded and extended, and it is needless to say that these should be within the scope of the claims of the present application.

[0010] Figure 1 is a cross-sectional structure schematic diagram of a display panel in the related art;

[0011] Figure 2 is a structure schematic diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 3 is Figure 2 is a cross-sectional structure schematic diagram along the A-A' direction in the embodiment;

[0013] Figure 4 is Figure 2 is another cross-sectional structure schematic diagram along the A-A' direction in the embodiment;

[0014] Figure 5 is Figure 2 is another cross-sectional structure schematic diagram along the A-A' direction in the embodiment;

[0015] Figure 6 is Figure 2 is another cross-sectional structure schematic diagram along the A-A' direction in the embodiment;

[0016] Figure 7 is Figure 2 is another cross-sectional structure schematic diagram along the A-A' direction in the embodiment;

[0017] Figure 8 is Figure 2 another sectional structure diagram of the display panel along the direction of A-A';

[0018] Figure 9 is a top view of a packaging structure provided by an embodiment of the present application;

[0019] Figure 10 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely by embodiments with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the basic concepts disclosed and suggested by the embodiments in the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0021] Figure 1 is a sectional structure schematic diagram of a display panel in the related art. Referring to Figure 1The display panel includes a first substrate 110', a second substrate 160', and an encapsulation structure 150' located between the first substrate 110' and the second substrate 160'. Furthermore, the display panel also includes a pixel definition layer 120' located on the side of the first substrate 110' near the second substrate 160', the pixel definition layer 120' including pixel openings that define the positions of sub-pixels 100'. On the side of the pixel definition layer 120' away from the first substrate 110', a plurality of support pillars 140' are also provided. Along the thickness direction of the display panel, the projection of the support pillars 140' does not overlap with the projection of the sub-pixels 100'. Thus, by fabricating support pillars 140' on the pixel definition layer 120', the height of the encapsulation structure 150' is matched, and they jointly support the second substrate 160'. In addition, the display panel also includes a common light-emitting layer 130'. The common light-emitting layer 130' can be a stacked structure of an organic light-emitting layer and a cathode, which is deposited on the entire surface of the pixel definition layer 120'. Thus, on the support pillars 140', a plurality of support pillars 140' are provided. The surface of the support pillar 140' near the second substrate 160' also has a common light-emitting layer 130'. Therefore, the common light-emitting layer 130' on the surface of the support pillar 140' near the second substrate 160' is easily scratched when it is attached to the second substrate 160'. For example, the cathode in the common light-emitting layer 130' may be scratched, resulting in a difference in reflectivity between the cathode at the scratch and the surrounding cathode, causing a dark spot defect. In addition, due to the difference in height of each support pillar 140', there is a height difference between the support pillar 140' and the packaging structure 150', which in turn produces the Newton's rings phenomenon and affects the product display effect.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a display panel comprising a display area, a peripheral circuit area, and an encapsulation area. The peripheral circuit area at least partially surrounds the display area, and the encapsulation area at least partially surrounds the peripheral circuit area. The display panel further includes a common light-emitting layer located at least in the display area, an encapsulation layer and a first planarization layer located in the display area and the peripheral circuit area, and an encapsulation structure located in the encapsulation area. The encapsulation layer and the first planarization layer are both located on the side of the common light-emitting layer away from the substrate. Along the thickness direction of the display panel, the height of the first planarization layer is h1, and the height of the encapsulation structure is h2, wherein |h1-h2| / h2≤20%. Compared with the prior art, the technical solution in the embodiments of the present invention eliminates the support pillar structure, thus avoiding damage to the common light-emitting layer above the support pillar, ensuring good balance in the orientation of the common light-emitting layer in different areas, and ensuring good overall display effect of the display panel. Furthermore, in this embodiment of the invention, by providing a first planarization layer on the side of the common light-emitting layer away from the substrate, the first planarization layer serves as a protective layer for the common light-emitting layer, preventing scratches on the common light-emitting layer, such as avoiding scratches on the cathode within the common light-emitting layer, avoiding differences in reflectivity between the scratched area and the surrounding common light-emitting layer, and preventing the generation of dark spots. In addition, along the thickness direction of the display panel, the height of the first planarization layer is h1, and the height of the encapsulation structure is h2. By setting |h1-h2| / h2≤20%, the height of the first planarization layer and the height of the encapsulation structure are approximately equal, avoiding the generation of Newton's rings due to the height difference between the first planarization layer and the encapsulation structure, thus improving the display effect of the display panel.

[0023] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0024] Specifically, Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 3 yes Figure 2 A simplified cross-sectional diagram along the A-A' direction, combined with... Figure 2 and Figure 3As shown, an embodiment of the present invention provides a display panel 10 including a display area AA, a peripheral circuit area AB, and an encapsulation area AC. The peripheral circuit area AB at least partially surrounds the display area AA, and the encapsulation area AC at least partially surrounds the peripheral circuit area AB. The display panel 10 also includes a common light-emitting layer 120 located at least in the display area AA, an encapsulation layer 130 and a first planarization layer 140 located in the display area AA and the peripheral circuit area AB, and an encapsulation structure 150 located in the encapsulation area AC. The encapsulation layer 130 and the first planarization layer 140 are both located on the side of the common light-emitting layer 120 away from the substrate 110. Along the thickness direction of the display panel, the height of the first planarization layer 140 is h1, and the height of the encapsulation structure 150 is h2, wherein |h1-h2| / h2≤20%.

[0025] Specifically, such as Figure 2 and Figure 3 As shown, the display panel 10 includes a display area AA, a peripheral circuit area AB, and a packaging area AC. The display area AA may include multiple pixel circuits 200, multiple gate lines, and multiple data lines (not shown in the figure) located on a substrate 110, as well as sub-pixels 100 located on one side of the substrate 110. The sub-pixels 100 can be arranged in an array. The multiple gate lines can extend along a first direction X, and the multiple data lines can extend along a second direction Y. The orthogonal projections of the multiple gate lines and multiple data lines on the substrate can intersect to form multiple circuit regions, each of which can contain one pixel circuit 200. The multiple data lines are electrically connected to the multiple pixel circuits 200 and can be configured to provide data signals to the multiple pixel circuits 200. The multiple gate lines are also electrically connected to the multiple pixel circuits 200 and can be configured to provide gate control signals to the multiple pixel circuits 200. The gate control signals may include scan signals, or may include both scan signals and light emission control signals.

[0026] For example, pixel circuit 200 can be configured to drive connected sub-pixels 100. Pixel circuit may include multiple transistors and at least one capacitor. For example, pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve product yield. The multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0027] Furthermore, sub-pixel 100 includes a common light-emitting layer 120, which can be a buffer layer, hole injection layer, hole transport layer, organic light-emitting layer, hole blocking layer, electron transport layer, and cathode stacked together. In some examples, the hole injection layers of all sub-pixels 100 can be common layers connected together, the hole transport layers of all sub-pixels 100 can be common layers connected together, the organic light-emitting layers of adjacent sub-pixels 100 can have a small overlap or can be isolated, and the hole blocking layers can be common layers connected together. The common light-emitting layer 120 of sub-pixels 100 is driven to emit light by pixel circuit 200 to ensure the normal operation of sub-pixels 100.

[0028] For example, the peripheral circuit area AB at least partially surrounds the display area AA, and various circuit structures and traces are provided therein. Specifically, power traces, such as PVEE signal lines, can be provided in the peripheral circuit area AB. The PVEE signal lines can be located on the second metal layer of the substrate 110 and disposed on the same layer as the source and drain of the transistor, and are disposed around the display area AA to provide a negative power signal to the display panel. Multiple data fan-out lines can be provided in the peripheral circuit area AB. These multiple data fan-out lines can be electrically connected to multiple data lines in the display area AA, thereby providing data signals to multiple pixel circuits through the data fan-out lines. Virtual traces can also be provided in the fourth metal layer of the substrate 110 in the peripheral circuit area AB, thereby ensuring that the wiring of the entire display area AA is balanced in the film layer where the connecting traces are located, avoiding reflection differences or film layer flatness differences caused by uneven wiring, etc. The embodiments of the present invention may also include other structures required for the normal operation of the peripheral circuit area AB, which will not be described in detail here.

[0029] It should be noted that, Figure 3 The diagram shown is only a illustrative cross-sectional view of the lower bezel area of ​​the display panel. In other embodiments, the peripheral circuit area AB may also be located in the upper bezel area, left bezel area, or right bezel area. It is understood that when the peripheral circuit area AB is located in the lower bezel area of ​​the display panel, power supply traces and data fan-out lines, etc., can be configured in the peripheral circuit area AB. When the peripheral circuit area AB is located in the left or right bezel area of ​​the display panel, a shift register can be configured in the peripheral circuit area AB to provide scanning signals to each row of sub-pixels in the display area AA. By configuring a shift register in the peripheral circuit area AB, the number of peripheral driver chips and corresponding connection lines can be reduced, saving design space for layout and wiring, and reducing the manufacturing cost of the display panel.

[0030] For example, the encapsulation area AC at least partially surrounds the peripheral circuit area AB, and the encapsulation area AC is provided with an encapsulation structure 150 to isolate the display panel from water and oxygen corrosion and improve the lifespan of the display panel.

[0031] Furthermore, in this embodiment of the invention, an encapsulation layer 130 and a first planarization layer 140 are disposed on the side of the common light-emitting layer 120 away from the substrate 110. The encapsulation layer 130 and the first planarization layer 140 are located in the display area AA and the peripheral circuit area AB. The first planarization layer 140 flattens the display area AA and the peripheral circuit area AB to support the upper substrate, without the need for support pillars to support the upper substrate. This avoids the difference in reflectivity between the scratched area and the surrounding area caused by scratching the cathode, resulting in dark spot defects and improving the display effect of the display panel. In addition, along the thickness direction of the display panel, the height of the first planarization layer 140 is h1 and the height of the encapsulation structure 150 is h2. By setting |h1-h2| / h2≤20%, the height h1 of the first planarization layer 140 and the height h2 of the encapsulation structure 150 are made approximately equal, thereby reducing the height difference between the first planarization layer 140 and the encapsulation structure 150, avoiding the Newton's rings phenomenon, and improving the display effect of the display panel.

[0032] It should be noted that, Figure 3 The illustration shows the encapsulation layer 130 located below the first planarization layer 140 only as an example. In other embodiments, the encapsulation layer 130 may also be located above the first planarization layer 140, and the present invention is not limited thereto.

[0033] In summary, the display panel provided by the embodiments of the present invention has an encapsulation layer and a first planarization layer disposed on the side of the common light-emitting layer away from the substrate. The encapsulation layer and the first planarization layer are located in the display area and the peripheral circuit area. The first planarization layer flattens the display area and the peripheral circuit area to support the upper substrate, thereby avoiding the dark spot defect phenomenon caused by scratching the cathode. In addition, by setting the height of the first planarization layer to h1 and the height of the encapsulation structure to h2, satisfying |h1-h2| / h2≤20%, the height of the first planarization layer and the height of the encapsulation structure are approximately equal, thereby reducing the height difference between the height of the first planarization layer and the height of the encapsulation structure, avoiding the Newton's rings phenomenon, and improving the display effect of the display panel.

[0034] Optionally, based on the above embodiments, see also... Figure 2 and Figure 3 h1 = h2. Specifically, by setting the height h1 of the first flattening layer 140 to be equal to the height h2 of the packaging structure 150, the height difference between the first flattening layer and the packaging structure is further reduced, avoiding the Newton's rings phenomenon caused by the height difference between the first flattening layer and the packaging structure, and further improving the display effect of the display panel.

[0035] Figure 4 yes Figure 2 A simplified diagram of another cross-sectional structure along the A-A' direction is shown in the image. Figure 4The display panel 10 also includes at least one first barrier structure 210 located in the peripheral circuit area AB. Specifically, as shown in... Figure 4 As shown, at least one first barrier structure 210 is provided in the portion of the first planarization layer 140 located in the peripheral circuit area AB. The first planarization layer 140 is blocked by the first barrier structure 210 to prevent the preparation material of the first planarization layer 140 from flowing into the encapsulation area AC and affecting the subsequent encapsulation, thus ensuring a good encapsulation effect of the display panel.

[0036] Optional, Figure 5 yes Figure 2 A simplified diagram of another cross-sectional structure along the A-A' direction is shown in the image. Figure 5 The peripheral circuit area AB is equipped with an electrostatic shielding circuit 230, and the display panel 10 also includes at least one first conductive structure 220 located in the peripheral circuit area AB, the first conductive structure 220 being electrically connected to the electrostatic shielding circuit 230. Specifically, as shown... Figure 5 As shown, the peripheral circuit area AB is provided with an electrostatic shielding circuit 230. In the part of the first planarization layer 140 located in the peripheral circuit area AB, a plurality of first conductive structures 220 are also provided. The plurality of electrostatic shielding circuits 230 are electrically connected to the plurality of first conductive structures 220, thereby transferring the charge in the first planarization layer 140 to the plurality of electrostatic shielding circuits 230 through the plurality of first conductive structures 220, preventing the charge from accumulating in the first planarization layer 140 and damaging the first planarization layer 140 and thus affecting the display area AA, avoiding any impact on the display area AA, and ensuring the display effect of the display area AA.

[0037] It should be noted that, Figure 5 The first conductive structure 220 and the electrostatic shielding circuit 230 are shown in the figure. The electrostatic shielding circuit 230 is then placed on the upper surface of the pixel definition layer. Those skilled in the art will understand that the electrostatic shielding circuit 230 is not placed on the upper surface of the pixel definition layer. The electrostatic shielding circuit 230 can be placed on the same layer as the pixel circuit 200.

[0038] See also Figure 5 The display panel 10 includes a plurality of first conductive structures 220 and a plurality of first barrier structures 210 located in the peripheral circuit area AB. The first conductive structures 220 and the first barrier structures 210 are alternately arranged in sequence along the direction from the display area AA to the peripheral circuit area AB.

[0039] Specifically, in the portion of the first flattening layer 140 located in the peripheral circuit area AB, not only are multiple first barrier structures 210 provided to block the first flattening layer 140, but also multiple first conductive structures 220 are provided to transfer the charge in the first flattening layer 140. Furthermore, along the direction from the display area AA to the peripheral circuit area AB, by alternately setting the first conductive structures 220 and the first barrier structures 210, the setting method of the first conductive structures 220 and the first barrier structures 210 is simple, ensuring that the first conductive structures 220 and the first barrier structures 210 can work normally.

[0040] Figure 6 yes Figure 2 A simplified diagram of another cross-sectional structure along the A-A' direction is shown in the image. Figure 6 The first planarization layer 140 includes an organic planarization layer, and the display panel also includes a second planarization layer 141 located between the first planarization layer 140 and the common light-emitting layer 120, the second planarization layer 141 including an inorganic planarization layer.

[0041] Specifically, such as Figure 6 As shown, the first planarization layer 140, the second planarization layer 141, and the encapsulation layer 130 are all located on the side of the common light-emitting layer 120 away from the substrate 110. The second planarization layer 141 is located between the first planarization layer 140 and the common light-emitting layer 120, and the encapsulation layer 130 is located on the side of the first planarization layer 140 away from the second planarization layer 141. Since the first planarization layer 140 includes an organic planarization layer, which contains moisture before drying, the moisture in the first planarization layer 140 can corrode the common light-emitting layer 120 during coating, causing the common light-emitting layer 120 to fail. There is also a risk of scratching the common light-emitting layer 120. Therefore, the first planarization layer... A second planarization layer 141 is disposed between the first planarization layer 140 and the common light-emitting layer 120. The second planarization layer 141 includes an inorganic planarization layer, which separates the first planarization layer 140 and the common light-emitting layer 120, preventing moisture from corroding the common light-emitting layer 120, thereby improving the lifespan of the display panel and the display effect. In addition, after electrostatic breakdown of the encapsulation structure 150, water and oxygen in the existing design directly enter the display area AA, causing the common light-emitting layer 120 located in the display area AA to fail. However, in this embodiment of the invention, the failure of the common light-emitting layer 120 can be delayed by the first planarization layer 140 and the second planarization layer 141, further improving the lifespan of the display panel.

[0042] See also Figure 6 The display panel also includes at least one second barrier structure 211 located in the peripheral circuit area AB, and the second flat layer 141 located in the peripheral circuit area AB includes at least one recess 1410, with a portion of the second barrier structure 211 located within the recess 1410.

[0043] Specifically, the portion of the second planarization layer 141 located in the peripheral circuit area AB is provided with multiple grooves 1410. The peripheral circuit area AB also includes at least one second barrier structure 211. The second barrier structure 211 includes a portion located in the grooves 1410 in the second planarization layer 141 and a portion located in the first planarization layer 140. That is, the grooves 1410 reinforce the second barrier structure 211 and enhance the blocking effect of the second barrier structure 211 on the first planarization layer 141, further preventing organic matter in the first planarization layer 141 from flowing into the encapsulation area AC and affecting subsequent encapsulation.

[0044] Optional, Figure 7 yes Figure 2 A simplified diagram of another cross-sectional structure along the A-A' direction is shown in the image. Figure 7 The second barrier structure 211 is integrally formed with the first planarization layer 140. Specifically, in the manufacturing process, the second barrier structure 211 and the first planarization layer 140 can be fabricated simultaneously in the same process. That is, the first planarization layer 140 fills the groove 1410, thereby preventing organic matter from the first planarization layer 140 from flowing into the encapsulation area AC and affecting subsequent encapsulation. In addition, since the second barrier structure 211 and the first planarization layer 140 are integrally formed, they can be fabricated using the same mask in the same process, eliminating the need to fabricate separate masks for the second barrier structure 211 and the first planarization layer 140, saving costs, reducing the number of processes, and improving production efficiency.

[0045] Optional, see below Figure 6 The second barrier structure 211 and the first planarization layer 140 are independently configured. Specifically, in the manufacturing process of the second barrier structure 211 and the first planarization layer 140, the second barrier structure 211 can be manufactured first, and then the first planarization layer 140 can be coated. The second barrier structure 211 can then block the organic matter in the first planarization layer 140, preventing the organic matter in the first planarization layer 140 from flowing into the encapsulation area AC and affecting subsequent encapsulation.

[0046] Optional, see below Figure 6 Along the thickness direction of the display panel, the depth of the groove 1401 is D1, and the thickness of the second planarization layer 141 is D2, where D2 / 3 ≤ D1 ≤ D2. Specifically, as shown... Figure 6As shown, the depth of the groove 1401 is D1, and the thickness of the second planarization layer 141 is D2. The thickness D2 of the second planarization layer 141 is the thickness of the second planarization layer 141 located in the encapsulation region AC. By setting the depth D1 of the groove 1401 to be greater than or equal to one-third of the thickness D2 of the second planarization layer 141 and less than or equal to the thickness D2 of the second planarization layer 141, it is prevented that the depth D1 of the groove 1401 is too deep, resulting in too much of the second blocking structure 211 being embedded in the groove 1401, which would affect the blocking effect of the second blocking structure 211. Alternatively, the depth D1 of the groove 1401 may be too shallow, failing to fix the second blocking structure 211.

[0047] Optional, see below Figure 6 The thickness of the second planarization layer 141 is D2, the thickness of the common light-emitting layer 120 is D3, and the thickness of the encapsulation structure 150 is D4, where D3 < D2 ≤ D4. Specifically, as shown... Figure 5 As shown, the thickness of the second planarization layer 141 is D2. By setting the thickness of the second planarization layer 141 to be greater than the thickness D3 of the common light-emitting layer 120, the thickness of the portion of the second planarization layer 141 located in the peripheral circuit area AB is greater than the thickness D3 of the common light-emitting layer 120. Consequently, the second planarization layer 141 can cover the common light-emitting layer 120 in both the display area AA and the peripheral circuit area AB without any breaks, so that the second planarization layer 141 can isolate the common light-emitting layer 120 from water and oxygen. In addition, by setting the thickness D2 of the second planarization layer 141 to be less than or equal to the thickness D4 of the encapsulation structure 150, that is, the maximum thickness D2 of the second planarization layer 141 is equal to the thickness D4 of the encapsulation structure 150, the thickness D2 of the second planarization layer 141 is not too thick, ensuring that the fabrication process is simple when the second planarization layer 141 is fabricated by CVD process.

[0048] Figure 8 yes Figure 2 A simplified diagram of another cross-sectional structure along the A-A' direction is shown in the image. Figure 8 The first planarization layer 140 includes an organic planarization layer, and the display panel also includes a third planarization layer 142 located on the side of the first planarization layer 140 away from the substrate 110, the third planarization layer 142 including an inorganic planarization layer.

[0049] Specifically, such as Figure 8As shown, between the common light-emitting layer 120 and the encapsulation layer 130, there are also a first planarization layer 140, a second planarization layer 141, and a third planarization layer 142. The first planarization layer 140 is located between the second planarization layer 141 and the third planarization layer 142. The second planarization layer 141 is located on the side of the first planarization layer 140 closer to the common light-emitting layer 120, and the third planarization layer 142 is located on the side of the first planarization layer 140 away from the common light-emitting layer 120. The first planarization layer 140 is an organic planarization layer, the second planarization layer 141 is an inorganic planarization layer, and the third planarization layer 142 is an inorganic planarization layer. That is, an inorganic-organic-inorganic stacked structure is formed by the first planarization layer 140, the second planarization layer 141, and the third planarization layer 142. After electrostatic breakdown of the encapsulation structure 150, the stacked structure of the first planarization layer 140, the second planarization layer 141, and the third planarization layer 142 can block water and oxygen, further delay the failure of the common light-emitting layer 120, and improve the life of the display panel.

[0050] It should be noted that the thickness of the third planarization layer 142 can be the same as or different from the thickness of the second planarization layer 141. This invention imposes restrictions on this, and those skilled in the art can set it as needed.

[0051] It should also be noted that, in the embodiments of the present invention, the planarization layer structure (i.e., the second planarization layer 141, the first planarization layer 140, and the third planarization layer 142) located between the common light-emitting layer 120 and the encapsulation layer 130, as well as the planarization layer structure (i.e., the second planarization layer 141, the first planarization layer 140, and the third planarization layer 142) located above the encapsulation layer 130, are different from the encapsulation structure in the encapsulation layer 130. That is, although the planarization layer structure is an inorganic-organic-inorganic stacked structure, it is independent of the inorganic-organic-inorganic thin film encapsulation structure in the encapsulation layer 130.

[0052] Based on the above embodiments, see below. Figure 8 The display panel also includes encapsulation metal 310 located in the encapsulation region AC and between the encapsulation structure 150 and the substrate 110. The display panel also includes at least one second conductive structure 320 located in the encapsulation region AC, and the second conductive structure 320 is electrically connected to the encapsulation metal 310.

[0053] Optional, see Figure 9The display panel also includes at least one second conductive structure 320 located in the encapsulation region AC. Multiple second conductive structures 320 penetrate the stacked structure of the first planarization layer 140, the second planarization layer 141, and the third planarization layer 142 and are electrically connected to the encapsulation metal 310 located between the encapsulation structure 150 and the substrate 110. Conductive adhesive is coated or deposited in the multiple second conductive structures 320 to form conductive holes. After electrostatic discharge (ESD) on the encapsulation structure 150, the charge in the encapsulation structure 150 is transferred to the encapsulation metal 310 through the multiple second conductive structures 320, preventing the charge from accumulating at the encapsulation structure 150 and damaging the encapsulation structure 150. This improves the antistatic capability of the display panel and increases the lifespan of the display panel.

[0054] Figure 9 This is a top view of the packaging structure provided in an embodiment of the present invention. See also... Figure 9 The display panel includes multiple second conductive point structures 320 located in the encapsulation area AC, and the multiple second conductive structures 320 are arranged around the encapsulation structure 150. Specifically, as shown... Figure 4 As shown, multiple second conductive structures 320 penetrate the third planarization layer 142 and are arranged around the encapsulation structure 150, thereby uniformly discharging static electricity around the encapsulation structure 150 through the encapsulation metal, further improving the antistatic capability of the display panel and increasing the lifespan of the display panel.

[0055] It should be noted that the embodiments of the present invention only exemplarily show that the top view of the second conductive structure 320 is circular. In other embodiments, the second conductive structure 320 may be other shapes. The embodiments of the present invention do not limit the size and shape of the second conductive structure 320, and those skilled in the art can set it as needed.

[0056] Based on the above embodiments, see Figure 6 and Figure 4 The encapsulation layer 130 includes an encapsulation cover plate 131, which is located between the film layer containing the common light-emitting layer 120 and the film layer containing the first planarization layer 140; or, the encapsulation layer 130 includes a thin film encapsulation layer 132, which is located on the side of the first planarization layer 140 away from the common light-emitting layer 120.

[0057] For details, see Figure 6 The encapsulation layer 130 includes an encapsulation cover plate 131, which can be a glass cover plate. The encapsulation cover plate 131 is located between the film layer containing the common light-emitting layer 120 and the film layer containing the first planarization layer 140 to prevent moisture and oxygen from corroding the common light-emitting layer 120, avoid failure of the common light-emitting layer 120, and improve the lifespan of the display panel. Or as... Figure 10As shown, the encapsulation layer 130 includes a thin-film encapsulation layer 132, which is located on the side of the first planarization layer 140 away from the common light-emitting layer 120. The thin-film encapsulation layer 132 may include a three-layer structure: an inorganic layer, an organic layer, and another inorganic layer. Water and oxygen are isolated by sequentially preparing 3 to 5 alternating layers of organic material. The inorganic layers in the thin-film encapsulation layer 132 are typically deposited using chemical vapor deposition (CVD) to form inorganic thin films, such as silicon nitride, which act as barriers to water and oxygen. The organic layers are typically coated using an inkjet printer to form organic thin films, such as polymers or resins. Their function is to cover defects in the inorganic layers, achieve planarization, and release stress between the inorganic layers, resulting in advantages such as thinness and flexibility.

[0058] It should be noted that the first planarization layer mentioned above can specifically be the first planarization layer 140, or it can be a planar structure, that is, the first planarization layer 140 and the second planarization layer 141, or a stacked structure of the first planarization layer 140, the second planarization layer 141 and the third planarization layer 142. That is, when the encapsulation layer 130 includes the encapsulation cover plate 131, the encapsulation cover plate 131 is located between the film layer where the common light-emitting layer 120 is located and the film layer where the planar structure is located; when the encapsulation layer 130 includes the thin film encapsulation layer 132, the thin film encapsulation layer 132 is located on the side of the planar structure away from the common light-emitting layer 120.

[0059] It should also be noted that, in the embodiments of the present invention, both the planarization layer structure located between the common light-emitting layer 120 and the encapsulation layer 130 (i.e., the second planarization layer 141, the first planarization layer 140, and the third planarization layer 142) and the planarization layer structure located above the encapsulation layer 130 (i.e., the second planarization layer 141, the first planarization layer 140, and the third planarization layer 142) are different from the encapsulation structure in the thin film encapsulation layer 132. That is, although the planarization layer structure is an inorganic-organic-inorganic stacked structure, it is independent of the inorganic-organic-inorganic thin film encapsulation structure in the thin film encapsulation layer 132.

[0060] Optionally, substrate 110 includes a flexible substrate. Specifically, substrate 110 includes a flexible substrate, which has bendable properties, making it easy to realize a bendable display device. When substrate 110 is a flexible substrate, a bonding area, a fan-out area, etc., are sequentially provided on the side of peripheral circuit area AB away from display area AA, but this invention does not limit this. The material of the flexible substrate can be ultra-thin glass, metal foil, or polymer plastic material. Among them, ultra-thin glass includes ultra-thin alkali-free glass, metal foil includes stainless steel foil, aluminum foil, copper foil, etc.; polymer plastic material includes polyimide, polyvinyl alcohol, polyethylene terephthalate, polymethyl methacrylate, etc.

[0061] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 10This is a schematic diagram of a display device provided in an embodiment of the present invention. ​ As shown, the display device includes the display panel 10 in the above embodiments. This display device includes the display panel 10 of any embodiment of the present invention; therefore, the display device provided by the embodiments of the present invention possesses the corresponding beneficial effects of the display panel 10 provided by the embodiments of the present invention, which will not be elaborated further here. For example, the display device can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device; the embodiments of the present invention do not limit this.

[0062] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises a display area, a peripheral circuit area at least partially surrounding the display area, and an encapsulation area at least partially surrounding the peripheral circuit area. The display panel further comprises a common light-emitting layer at least in the display area, an encapsulation layer and a first planarization layer at least in the display area and the peripheral circuit area, and an encapsulation structure in the encapsulation area; the encapsulation layer and the first planarization layer are both on a side of the common light-emitting layer away from the substrate. In a thickness direction of the display panel, a height of the first planarization layer is h1, and a height of the encapsulation structure is h2, where |h1-h2| / h2≤20%, and the display area and the peripheral circuit area are planarized and supported by the first planarization layer and the encapsulation structure.

2. The display panel of claim 1, wherein, h1=h2.

3. The display panel of claim 1, wherein, The display panel further comprises at least one first barrier structure in the peripheral circuit area.

4. The display panel of claim 1, wherein, The peripheral circuit area is provided with an electrostatic shielding circuit. The display panel further comprises at least one first conductive structure in the peripheral circuit area, and the first conductive structure is electrically connected with the electrostatic shielding circuit.

5. The display panel of claim 4, wherein, The display panel comprises a plurality of first conductive structures and a plurality of first barrier structures in the peripheral circuit area. In a direction of the display area pointing to the peripheral circuit area, the first conductive structures and the first barrier structures are alternately arranged in sequence.

6. The display panel of claim 1, wherein, The first planarization layer comprises an organic planarization layer. The display panel further comprises a second planarization layer between the first planarization layer and the common light-emitting layer, and the second planarization layer comprises an inorganic planarization layer.

7. The display panel of claim 6, wherein, The display panel further comprises at least one second barrier structure in the peripheral circuit area. The second planarization layer in the peripheral circuit area comprises at least one groove. Part of the second barrier structure is located in the groove.

8. The display panel of claim 7, wherein, The second barrier structure is integrally arranged with the first planarization layer.

9. The display panel of claim 7, wherein, The second barrier structure is independently arranged with the first planarization layer.

10. The display panel of claim 7, wherein, In a thickness direction of the display panel, a depth of the groove is D1, and a thickness of the second planarization layer is D2. Wherein, D2 / 3≤D1≤D 2.

11. The display panel of claim 6, wherein, The thickness of the second planarization layer is D2, the thickness of the common light-emitting layer is D3, and the thickness of the encapsulation structure is D4. Wherein, D3<D2≤D4.

12. The display panel of claim 1, wherein, The first planarization layer comprises an organic planarization layer. The display panel further comprises a third planarization layer on a side of the first planarization layer away from the substrate, and the third planarization layer comprises an inorganic planarization layer.

13. The display panel of claim 1, wherein, The display panel further comprises an encapsulation metal between the encapsulation structure and the substrate in the encapsulation area. The display panel further comprises at least one second conductive structure in the encapsulation area, and the second conductive structure is electrically connected with the encapsulation metal.

14. The display panel of claim 13, wherein, The display panel comprises a plurality of second conductive structures in the encapsulation area. The plurality of second conductive structures are arranged around the encapsulation structure.

15. The display panel of claim 1, wherein, The encapsulation layer comprises an encapsulation cover plate between a film layer where the common light-emitting layer is located and a film layer where the first planarization layer is located. Alternatively, the encapsulation layer comprises a thin film encapsulation layer, which is located on a side of the first planar layer distal to the common light emitting layer.

16. The display panel of claim 1, wherein, The substrate comprises a flexible substrate.

17. A display device comprising: A display panel comprising any of claims 1-16.

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