Data cache write method and system of SSD, flash memory controller and SSD controller

Abstract

The application provides a data cache writing method and system of an SSD, a flash memory controller and an SSD controller. The method comprises the following steps: obtaining data to be written; allocating at least one first cache unit and / or at least one second cache unit to the data to be written according to a predetermined proportion, wherein the first cache unit is from an on-chip SRAM, and the second cache unit is from an off-chip DDR; writing the data to be written into the allocated first cache unit and / or second cache unit; and transferring the data cached in the first cache unit and / or second cache unit of the written data to a NAND. The application provides a certain proportion of cache units from the on-chip SRAM and off-chip DDR respectively to cache the data to be written, and then transfers the cached data to the flash memory, so that the average bandwidth of the SSD when transferring data to the cache unit is improved, and the performance of the SSD is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data cache writing method, system, flash memory controller, and SSD controller for SSDs. Background Technology

[0002] With the application of PCIe Gen4 and PCIe Gen5, SSD performance requirements are increasing exponentially, and DDR (Double Data Rate Synchronous Dynamic Random Access Memory) serves as the buffer (data cache) unit for SSDs (Solid State Drives). Figure 1 The diagram illustrates a caching method using DDR as the cache unit during data writing in existing technologies. This method incurs additional overhead, such as FTL table lookups and modifications, and the data protection bit PI (Protection Information). Consequently, DDR media can experience performance bottlenecks and fail to meet new business performance requirements. For PCIe Gen 4 / PCIe Gen 5 or future higher bandwidth host interfaces, the SSD's host data cache space can only be handled by the controller's on-chip SRAM (Static Random Access Memory).

[0003] like Figure 2 The diagram illustrates a caching method in existing technologies that uses the controller's on-chip SRAM as a cache unit for data writing. On-chip SRAM typically offers ample bandwidth (SRAM bandwidth is generally several times that of off-chip DDR memory), but due to cost constraints, SRAM capacity is severely limited (typically in the MB range, while off-chip DDR can reach the GB range). Under SSD concurrency requirements, if the SRAM alone bears the immense pressure of bidirectional data transmission on both the uplink and downlink channels, the limited SRAM capacity cannot provide sufficient cache space to accommodate all read and write data, thus limiting SSD performance.

[0004] In existing technologies, tiered caching is typically used to balance the trade-off between memory bandwidth and capacity. However, tiered caching introduces additional data transfer between different cache tiers, which consumes bandwidth within the controller and increases SSD power consumption and complexity.

[0005] Therefore, the urgent technical problem to be solved is: how to increase the average bandwidth when SSDs transfer data to cache units, thereby improving SSD performance. Summary of the Invention

[0006] The purpose of this application is to provide an SSD data cache writing method, system, flash memory controller, and SSD controller, and to solve the problem of how to improve the average bandwidth when transferring data from an SSD to a cache unit.

[0007] According to a first aspect of this application, this application provides a data cache writing method for an SSD, the method comprising the following steps: acquiring data to be written; allocating at least one first cache unit and / or at least one second cache unit to the data to be written according to a predetermined ratio, wherein the first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR; writing the data to be written into the allocated first cache unit and / or second cache unit; and transferring the cached data in the first cache unit and / or second cache unit to NAND.

[0008] In one embodiment of the SSD data cache writing method described above, the step of transferring the cached data in the first cache unit and / or the second cache unit to the NAND flash memory includes:

[0009] The first cache unit and / or the second cache unit to which data is written are combined into a cache unit group; the data cached in the cache unit group is transferred to NAND.

[0010] In one embodiment of the SSD data cache writing method described above, after transferring the cached data in the first cache unit and / or the second cache unit to the NAND, the method further includes:

[0011] In response to the completion of data transfer in a cache unit, the cache unit that has completed the data transfer is released, and the released cache unit is used for reallocation to receive new data to be written by the host.

[0012] In one embodiment of the SSD data cache writing method described above, the cache unit group transfers data in the order of data transfer and releases the cache units sequentially in the order of data transfer, wherein the order of data transfer is either the order in which the cache units are assembled or the reverse order of their transfer to the NAND.

[0013] In one embodiment of the SSD data cache writing method described above, when transferring data cached in the cache unit group to NAND, the data of the first cache unit is transferred first, and then the data of the second cache unit is transferred.

[0014] In one embodiment of the SSD data cache writing method described above, the size of the cache unit group is equal to the size of the NAND programming unit.

[0015] In one embodiment of the SSD data cache writing method described above, the cache unit group includes one off-chip DDR and two on-chip SRAMs.

[0016] In one embodiment of the SSD data caching writing method described above, when the first cache unit and / or the second cache unit form a cache unit group, a total of multiple cache unit groups are formed, and the off-chip DDR constituting the cache unit groups in different cache unit groups are different, while the on-chip SRAM constituting the cache unit groups is the same.

[0017] In one embodiment of the SSD data caching write method described above, allocating at least one first cache unit and / or at least one second cache unit for the data to be written includes:

[0018] Identify the proportion of the first cache unit already allocated from the on-chip SRAM, and determine whether the proportion of the first cache unit exceeds the target threshold. If so, allocate the second cache unit from the off-chip DDR; otherwise, allocate the first cache unit from the on-chip SRAM.

[0019] In one embodiment of the SSD data cache writing method described above, the first cache unit is a virtual cache unit provided by on-chip SRAM; the second cache unit is a virtual cache unit provided by off-chip DDR.

[0020] In one embodiment of the SSD data caching writing method described above, when the first cache unit and / or the second cache unit for writing data are grouped into multiple cache unit groups, the proportion of the first cache unit and the second cache unit in different cache unit groups is the same or different, and the proportion of the second cache unit provided by off-chip DDR in different cache unit groups ranges from 40% to 60%.

[0021] According to a second aspect of this application, this application provides a flash memory controller for transferring data cached in a first cache unit and / or a second cache unit to NAND, wherein the data cached in the first cache unit and / or the second cache unit is data cached by allocating the data to be written to at least one first cache unit and / or at least one second cache unit according to a predetermined ratio, wherein the first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR.

[0022] According to a third aspect of this application, this application provides an SSD controller, comprising:

[0023] PCIe interface, on-chip SRAM and flash memory controller;

[0024] The PCIe interface is communicatively connected to the host. The PCIe interface is used to receive data to be written from the host and allocate the data to be written to at least one first cache unit and / or at least one second cache unit according to a predetermined ratio. The first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR.

[0025] One end of the on-chip SRAM is communicatively connected to the PCIe interface, and the other end is communicatively connected to the flash memory controller. The on-chip SRAM is used to write data allocated to the first cache unit.

[0026] The flash memory controller is used to transfer data cached in the first cache unit and / or the second cache unit to NAND.

[0027] According to a fourth aspect of this application, this application provides an SSD data caching and writing system, the system comprising:

[0028] An SSD controller and an off-chip DDR; the SSD controller includes a PCIe interface, on-chip SRAM, and a flash memory controller; one end of the off-chip DDR and the on-chip SRAM are communicatively connected to the PCIe interface, and the other end is communicatively connected to the flash memory controller; the flash memory controller is communicatively connected to NAND; the SSD controller is communicatively connected to the host via the PCIe interface, which is used to receive data to be written by the host; the data to be written is allocated to at least one first cache unit and / or at least one second cache unit according to a predetermined ratio, wherein the first cache unit comes from the on-chip SRAM, and the second cache unit comes from the off-chip DDR; the on-chip SRAM is used to write the data allocated to the first cache unit; the flash memory controller is used to transfer the data cached in the first cache unit and / or the second cache unit to NAND; the off-chip DDR is used to write the data allocated to the second cache unit.

[0029] The beneficial effects achieved by this application are as follows:

[0030] (1) This application provides cache units for two different types of storage media, namely on-chip SRAM and off-chip DDR, at the same level. The cache units provided by the two storage media need to be provided in a certain ratio to improve the average bandwidth when the SSD transfers data to the cache unit, thereby improving the actual performance of the SSD.

[0031] (2) This application configures the on-chip SRAM and off-chip DDR to be used as cache in terms of capacity ratio and performance contribution ratio, so as to obtain higher performance on a certain capacity basis by making more use of SRAM.

[0032] (3) In this application, multiple cache units allocated for data to be written to the host are assembled into a cache unit group. The data of the cache unit in the cache unit group is cached to NAND in sequence. After the data transfer is completed, the cache unit is released and the released cache unit is reassigned to the host for caching data, thereby improving the utilization rate of the cache unit.

[0033] (4) This application determines the proportion of SRAM cache allocation by time period or multiple cache unit groups, promotes the reverse processing of QoS front-end data preparation order and NAND programming order, so as to create a difference in the utilization rate of DDR and SRAM, thereby improving the performance ratio of SRAM. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0035] Figure 1 This is a schematic diagram of a caching method in the prior art that uses DDR as the cache unit when writing data.

[0036] Figure 2 This diagram illustrates a caching method in existing technologies that uses the controller's on-chip SRAM as a cache unit for data writing.

[0037] Figure 3 This is a flowchart illustrating an SSD data cache writing method according to an embodiment of this application.

[0038] Figure 4 This is a schematic diagram illustrating the communication connection between the SSD controller, DDR, and NAND in an embodiment of this application.

[0039] Figure 5 This is a flowchart of a first SSD data cache writing method according to an embodiment of this application.

[0040] Figure 6 This is a flowchart of a second SSD data cache writing method according to an embodiment of this application.

[0041] Figure 7 This is a flowchart of a third SSD data cache writing method according to an embodiment of this application.

[0042] Figure 8 The cache unit allocation method flow of this application embodiment Figure 1 .

[0043] Figure 9 This is a flowchart of a fourth SSD data cache writing method according to an embodiment of this application.

[0044] Figure 10 This is a schematic diagram of the block and page strip structure of an embodiment of this application.

[0045] Figure 11This is a flowchart of the fifth SSD data cache writing method according to an embodiment of this application.

[0046] Figure 12 This is a schematic diagram of the first virtual cache unit structure according to an embodiment of this application.

[0047] Figure 13 This is a schematic diagram of the second type of virtual cache unit composition structure according to an embodiment of this application.

[0048] Figure 14 This is a schematic diagram of the third type of virtual cache unit structure in an embodiment of this application.

[0049] Figure 15 This is a schematic diagram of the fourth virtual cache unit structure in an embodiment of this application.

[0050] Figure 16 The cache unit allocation method flow of this application embodiment Figure 2 .

[0051] Figure 17 This is a flowchart illustrating the method for processing and writing data according to an embodiment of this application.

[0052] Figure 18 This is a schematic diagram of the structure of an SSD data cache writing system according to an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0054] With the increasing popularity of high-capacity SSDs and a significant shortage of SRAM, improving SRAM utilization and achieving greater performance with less SRAM has become a pressing challenge. This application leverages the characteristics of NAND programming and improves the performance of high-capacity SSDs through differentiated data preparation sequences, thereby achieving more efficient SRAM utilization.

[0055] Example 1

[0056] like Figure 3 As shown, this application provides a method for writing data cache to an SSD, which includes the following steps:

[0057] Step S1: Obtain the data to be written.

[0058] Specifically, the host receives data to be written to the SSD from the SSD controller's PCIe interface. The data the host needs to write to the SSD is the data that needs to be cached.

[0059] Step S2: Allocate at least one first cache unit and / or at least one second cache unit to the data to be written according to a predetermined ratio, wherein the first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR.

[0060] Because the bandwidth of on-chip SRAM exceeds performance requirements, while the bandwidth of off-chip DDR falls short, cache units provided by these two different types of storage media must be allocated in a certain ratio, with the proportion of off-chip DDR not exceeding a certain threshold. This threshold can be calculated based on the maximum bandwidth M of the host interface for receiving and writing data, the maximum bandwidth M1 of on-chip SRAM, and the maximum bandwidth M2 of off-chip DDR, or it can be determined according to the SSD design requirements.

[0061] As a specific embodiment of this application, the target threshold YD for the proportion of off-chip DDR is calculated as follows:

[0062] According to the formula The process involves solving for the target threshold YD to obtain a second target threshold for the proportion of off-chip DDR. The cache units of on-chip SRAM and off-chip DDR are then allocated according to the principle that the proportion of off-chip DDR cannot exceed the obtained target threshold YD.

[0063] Preferably, the proportion of the first cache units already allocated from the on-chip SRAM is identified, and it is determined whether the proportion of the first cache units exceeds a first target threshold. If so, a second cache unit is allocated from the off-chip DDR; otherwise, a first cache unit is allocated from the on-chip SRAM. The first target threshold ranges from 40% to 60%. Preferably, the first target threshold is 50%.

[0064] In another embodiment of this application, the proportion of the second cache units already allocated from off-chip DDR can be identified, and it can be determined whether the proportion of the second cache units exceeds a second target threshold. If so, a first cache unit is allocated from on-chip SRAM; otherwise, a second cache unit is allocated from off-chip DDR. The second target threshold ranges from 40% to 60%. Preferably, the second target threshold is 50%; or the second target threshold is 60%.

[0065] As a specific embodiment of this application, after the cache unit ratio of on-chip SRAM and off-chip DDR is completed, the theoretical maximum performance of the SSD is calculated. The method for calculating the theoretical maximum performance of the SSD is as follows:

[0066] ;

[0067] Wherein, DDR% represents the percentage of off-chip DDR, SRAM% represents the percentage of on-chip SRAM, and the sum of the percentage of off-chip DDR and the percentage of on-chip SRAM is 1; DDR performance represents the performance (maximum bandwidth) of off-chip DDR; SRAM performance represents the performance (maximum bandwidth) of on-chip SRAM.

[0068] The minimum required number of cache units allocated to the host must meet the following conditions:

[0069] Since the performance of a single SSD disk is less than the minimum number of concurrent flash channels multiplied by the performance of a single flash channel, the supply of cache units should be at least greater than the data cache capacity required for the minimum number of concurrent channels to meet the data concurrent transmission performance requirements, while also considering the turnaround requirements.

[0070] As an example, an SSD includes 16 flash channels, providing concurrent data transfer capabilities for 16 LUNs (Logical Units). Each LUN consists of 4 planes. The smallest unit of data written to each plane (called a program unit) is a TLC physical page (comprising three 16KB physical pages). To maximize the concurrency of this SSD's 16 channels, the minimum data cache requirement is: At this point, the channels for the concurrent access must always be in a data transmission state to achieve the theoretical performance. The supply of cache units should be at least greater than the data cache capacity required for the minimum number of concurrent channels.

[0071] Furthermore, different NAND flash memory chips may receive write data at different granularities. For example, some NAND flash memory chips, when processing programming commands, receive all three pages of data from a TLC physical page and provide a programming result (success or failure). In response, the cache unit containing these three pages of data can be completely released. Other NAND flash memory chips provide two or more programming results for the three pages of TLC physical page data, with each result indicating whether the programming of one or two pages was successful or failed. In response, the corresponding one or two pages of data are released. Therefore, the granularity of allocating and releasing cache units may differ when the SSD controller manages the cache units. For example, when allocating cache units, the minimum number can be allocated, and the cache units can be assembled into TLC physical page sizes; however, when releasing cache units, it needs to be released in one or more steps. As an example, for SSD controllers to operate NAND, the basic unit for releasing cache units is a single physical page (not a TLC physical page), meaning the allocated cache unit is released in three steps. Therefore, to ensure uninterrupted data transmission and maximize SSD throughput, at least an additional 1 / 3 of the cache units are needed to fill the gaps between allocated and released cache units. Thus, the theoretically required total number of cache units for an SSD is:

[0072] ;

[0073] Providing 4MB of SRAM directly from the controller is challenging (leading to high or even unacceptable costs). Even if the controller provides 4MB of SRAM, some of the SRAM space may be used for other purposes and cannot be used as cache units. Therefore, higher overall SSD performance (e.g., write bandwidth) needs to be achieved by combining a limited number of on-chip SRAM cache units with off-chip DDR cache units.

[0074] like Figure 4 As shown, the SSD controller includes a PCIe interface, SRAM located within the controller chip (referred to as on-chip SRAM), and a flash memory controller. The SSD also includes DDR (referred to as off-chip SSD) coupled to the SSD controller and located outside the SSD controller. After the on-chip SRAM and off-chip DDR input terminals are connected to the PCIe interface for communication, their output terminals are connected to the flash memory controller for communication, and the flash memory controller is connected to the NAND flash memory.

[0075] Step S3: Write the data to be written to the allocated first cache unit and / or second cache unit.

[0076] Specifically, the cache unit for the receiving host to write data can be either the first cache unit provided by the on-chip SRAM or the second cache unit provided by the off-chip DDR.

[0077] Step S4: Transfer the data cached in the first cache unit and / or the second cache unit to NAND.

[0078] Step S4 includes:

[0079] Step S410: Assemble the first cache unit and / or the second cache unit into multiple cache unit groups for writing data.

[0080] As a specific embodiment of this application, multiple cache unit groups may include a first number of first cache units and a second number of second cache units, the first number and the second number may be the same or different. Furthermore, the ratio of first cache units to second cache units in the multiple cache unit groups may be the same or different. When the ratio is the same, for example, each of the multiple cache unit groups includes two first cache units and two second cache units; when the ratio is different, for example, each of the multiple cache unit groups includes two first cache units and one second cache unit.

[0081] Step S420: Transfer the data cached in the cache unit group to NAND.

[0082] Specifically, the flash controller within the SSD controller transfers cached data to NAND. According to embodiments of this application, the flash controller can transfer data cached in on-chip SRAM cache units to NAND, or data cached in off-chip DDR cache units to NAND.

[0083] Preferably, data in each cache unit of the cache unit group is sequentially transferred to the NAND flash memory, and in response to the completion of data transfer in a certain cache unit, the cache unit whose data transfer has been completed is released. After being released, the cache unit is reassigned to the host for data to be written. Preferably, the cache unit group transfers data to the NAND flash memory sequentially according to the order in which the cache units were assembled or in reverse order, and releases the cache units sequentially according to the order in which the data is transferred.

[0084] Preferably, the cache unit group first transfers the data from the first cache unit, and then transfers the data from the second cache unit. That is, the data from the first cache unit provided by the on-chip SRAM is transferred first, and then the data from the second cache unit provided by the off-chip DDR is transferred. This is to free up the first cache unit provided by the on-chip SRAM first, and then reallocate the first cache unit to receive new data to be written by the host. This can improve the utilization rate of the on-chip SRAM and make full use of the high performance (mainly referring to bandwidth and latency performance) provided by the SRAM.

[0085] Preferably, the size of the cache cell group is equal to the size of the NAND programming cell. Since the data transmitted from the backend to the NAND needs to be assembled according to the size of the NAND programming cell, and the NAND programming cell is the smallest unit of data written to the NAND, assembling the cache cell group to be equal to the size of the NAND programming cell allows for successful and fast writing of the data in the cache cell group into the NAND.

[0086] Traditional buffer (data cache) management methods tend to meet the minimum buffer requirement, sacrificing buffer allocation, which reduces the theoretical maximum performance of the SSD. The actual ratio of the two types of buffers is as follows:

[0087] SRAM percentage = SRAM amount / Total buffer amount;

[0088] DDR percentage = DDR quantity / (SRAM quantity + DDR quantity) = 100% - SRAM percentage;

[0089] Among them, SRAM percentage represents the proportion of SRAM data cache; DDR percentage represents the proportion of DDR data cache; SRAM quantity represents the total number of cache units provided by on-chip SRAM; and DDR quantity represents the total number of cache units provided by off-chip DDR.

[0090] To improve the theoretical maximum performance of SSDs, this application adopts the following methods:

[0091] This application allocates multiple cache units to carry data written by the front end (e.g., write commands from the host). Since the front end writes data at unpredictable times, and the data transferred from the back end to the NAND flash memory needs to be assembled according to the NAND programming cell size, the allocated cache units form a cache unit group, with the data in the cache unit group corresponding to the NAND programming cell size. For example, the size of the cache unit group is 48KB, corresponding to a TLC physical page. Alternatively, it can be used for 3072KB of concurrent data across 16 channels. Each time a cache unit is released, one 16KB physical page of data or 1024KB of data corresponding to 16 channels is released. For example... Figure 5 In this configuration, cache units S1 and S2 are provided by on-chip SRAM, while cache units D1 and D2 are provided by off-chip DDR. Each cache unit group includes 3 cache units, and cache units are released one at a time after data is transferred to NAND from the backend. Understandably, cache unit groups can have other sizes and include different numbers of cache units, and when releasing cache units, the number of cache units can be equal to the number of cache units at a time.

[0092] According to embodiments of this application, when allocating cache units to form cache unit groups, the quantity relationship (ratio) between cache units from on-chip SRAM and cache units from off-chip DDR is also considered. For example, in Figure 5 In this embodiment, the cache unit group includes one off-chip DDR and two on-chip SRAMs. Of the three cache units constituting the cache unit group, two are cache units from the on-chip SRAM (i.e., S1 and S2), and the other is a cache unit from the off-chip DDR (i.e., D1). In this way, when writing data to the cache unit group, data written to two cache units can achieve the high performance (mainly in terms of bandwidth and latency) provided by the on-chip SRAM, while data written to the other cache unit experiences the relatively low performance (mainly in terms of bandwidth and latency) provided by the off-chip DDR. Therefore, the overall bandwidth for writing data to this cache unit group is higher than the bandwidth obtained by using only off-chip DDR as cache. Furthermore, the number (proportion) of cache units provided by the on-chip SRAM in the cache unit group determines the performance bandwidth for writing data to that cache unit group. The larger the number (proportion) of cache units provided by the on-chip SRAM in the cache unit group, the more high bandwidth and low latency performance the on-chip SRAM provides for the data writing process, and correspondingly, the better the overall performance for writing data to a cache unit group with a larger proportion of on-chip SRAM.

[0093] For example, only cache units S1, S2, D1 and D2 can be used to cache the written data, without occupying additional storage space in the memory.

[0094] like Figure 5 The diagram shown is a flowchart of an SSD data caching writing method according to a first embodiment of this application. The data caching method includes the following steps:

[0095] Step 1: At the front end, cache unit D2 (from DDR) has been allocated to carry write data. At the front end, the host transmits data to cache unit D2 through the PCIe interface. At the same time, at the back end, there is an assembled cache unit group (including cache units S1, S2 and D1), in which cache unit S1 is transmitting data to NAND. After the data transmission is completed, cache unit S1 is released.

[0096] Step 2: At the front end, the cache unit S1 released in Step 1 is allocated to carry the data written through the PCIe interface; in the prepared data waiting area, the cache unit D2 has been written with data but has not yet completed data assembly (not enough of the 3 cache units required to construct the cache unit group); while the back end transmits the data of the cache unit S2 in the cache unit group to the NAND. After the data transmission is completed, the cache unit S2 is released.

[0097] Since cache units D2 and S1 are allocated and filled in steps 1 and 2, and according to the embodiments of this application, in order to improve the overall bandwidth of writing data to the cache unit group, two cache units S1 and S2 from the on-chip SRAM and one cache unit D1 from the DDR are used when constructing the cache unit group.

[0098] Step 3: At the front end, cache unit S2, released in step 2, is allocated to carry data written through the PCIe interface; in the prepared data waiting area, cache units D2 and S1 have been written with data, but data assembly has not yet been completed (the three cache units required to construct the cache unit group have not been filled); while the back end transmits the data of cache unit D1 in the cache unit group to the NAND. After the data transmission is completed, cache unit D1 is released.

[0099] Step 4: At the front end, cache unit D1, released in Step 3, is allocated to carry data written via the PCIe interface. In the prepared data waiting area, cache units D2, S1, and S2 have been written with data, completing the data assembly of the cache unit group. The newly assembled cache unit group includes cache units D2, S1, and S2. At the back end, the data of cache unit S2 in the cache unit group is transferred to the NAND flash memory. After Step 4 is completed, cache unit S2 is released.

[0100] Further, in step 4, for the assembled cache unit group (including cache units S2, S1, and D1), data is transferred to the NAND in reverse order of the assembly sequence of the cache units. Figure 3 In this embodiment, cache units are assembled into cache unit groups in the order of D2, S1, and S2. When transferring data to NAND, the cache units are transferred and released in the order of S2, S1, and D2. In this way, cache units S1 and S2 are allocated and utilized more frequently (compared to cache units from off-chip DDR) by releasing cache units (S1 and S2) from on-chip SRAM in advance.

[0101] According to embodiments of this application, when the first cache unit and / or the second cache unit form a cache unit group, multiple cache unit groups are formed in total. The off-chip DDR constituting the cache unit groups are different in different cache unit groups, while the on-chip SRAM constituting the cache unit groups is the same. Figure 5 As shown in the example, in step 1, the back-end output is composed of an external DDR (D1) and two on-chip SRAMs (S1, S2) to form a cache unit group. In step 4, the back-end output is composed of an external DDR (D2) and two on-chip SRAMs (S1, S2) to form a cache unit group. The on-chip SRAMs in the two cache unit groups are the same, but the external DDRs are different, thus improving the utilization rate of the on-chip SRAM.

[0102] Figure 5 The illustrated embodiment demonstrates a processing flow where the front end receives data, a waiting area constructs a complete buffer unit group, and the data from the buffer unit group is written to the back end. Furthermore, the buffer units released after each data transfer to the NAND flash memory are immediately used for front end data reception and writing in the next step, eliminating waste of buffer units. There are no idle buffer units in any step, thus reducing the required buffer units (e.g., using only 4 buffer units). Furthermore, in Figure 5 In this implementation, the ratio of cache units from on-chip SRAM to cache units from off-chip DDR is 1:1 (two of each), and each cache unit group includes two cache units from on-chip SRAM and one cache unit from off-chip DDR, thereby achieving higher overall performance (bandwidth and latency) for writing data to the cache unit group.

[0103] Furthermore, Figure 5In the illustrated embodiment, when transferring data from the assembled cache unit group to the NAND, data from two cache units (S1 and S2) provided by on-chip SRAM is always transferred first to release the SRAM-provided cache units. Finally, data from the cache units (D1 and D2) provided by off-chip DDR is transferred to release the DDR-provided cache units later. Optionally, when transferring data from the assembled cache unit group to the NAND, data can be transferred in other orders (sorted by the storage medium type providing the cache units). However, for each assembled cache unit group, the order of data transfer should be consistent to ensure that the cache units constituting each cache unit group maintain the same proportion (2 cache units from on-chip SRAM and 1 cache unit from off-chip DDR).

[0104] Understandably, when constructing cache cell groups, ensuring that the allocated cache cells maintain the same proportion is aimed at fully utilizing the high performance provided by SRAM. However, if high performance is not a priority, the proportion of cache cells in the constructed cache cell groups can be left unrestricted.

[0105] according to Figure 5 The cache unit group configuration shown, according to an embodiment of this application, adjusts the order of cache unit usage, increasing the utilization rate of cache units from SRAM to twice that of cache units from DDR when constructing the cache unit group. This results in the performance contribution of cache units from SRAM exceeding their actual capacity proportion. Specifically, the capacity proportion of cache units from on-chip SRAM is 2 / 4 = 50%.

[0106] However, its actual contribution to SSD performance reaches 2 / 3 = 66.7%;

[0107] The cache unit capacity from off-chip DDR accounts for 2 / 4 = 50%;

[0108] However, the actual impact on SSD performance is 1 / 3 = 33.3%.

[0109] The performance impact calculations presented here are merely illustrative. Further calculations on the performance impact of SSDs can be obtained by combining the performance data of on-chip SRAM and off-chip DDR.

[0110] Therefore, it can be seen that, according to Figure 5 The proposed implementation significantly reduces the SRAM requirement while meeting the total throughput of cache units and the specified performance requirements of the SSD. In other words, it can improve the overall performance of the SSD while meeting the SRAM capacity requirements.

[0111] To further illustrate the cache unit allocation, data assembly, and cache unit release stages, this application provides, for example... Figure 6 The second data cache writing method is shown. The cache unit allocation, data assembly, and cache unit release stages can be implemented by corresponding modules (software, hardware, firmware, or a combination thereof), so that the cache unit allocation, data assembly, and cache unit release stages can occur or be processed concurrently or in parallel.

[0112] It needs to be explained that, in Figure 6 In the diagram, the downward arrow on the left represents the direction of time t's passage. This allows us to understand that step 1-1 occurs before step 1-2, step 1-2 occurs before step 1-3, and so on. During the cache unit allocation phase, available cache units (those not used to receive data written by the host or to build cache unit groups) are acquired. Figure 6 In this embodiment, since only four cache units (S1, S2, D1, D2) are provided, cache units that were typically released after the data transfer to NAND was completed in the steps preceding the current step can be reallocated.

[0113] During the front-end data transfer phase, data to be written to the SSD is received from the host via, for example, PCIe, and the data is filled into the allocated cache units. Figure 6 In this embodiment, since only one cache unit can be allocated at a time, data is transferred to only one cache unit in one step.

[0114] During the data assembly phase, allocated cache units are assembled into cache unit groups. Since cache units are allocated one at a time, and assembly only occurs after each cache unit has been filled with data written to it by the front end, the data assembly phase is not complete until all three cache units constituting a cache unit group have been allocated and filled with data. Before the cache unit group is fully assembled, one or more cache units already included in the group will not be allocated again.

[0115] The cache unit group in the data assembly stage is a different cache unit group from the cache unit group from which the backend retrieves data and transfers it to NAND. For example, see Figure 6 In step 2-1, cache unit group B is in the data assembly stage and has been allocated cache unit D2, while cache unit group A is in the backend data transfer stage to NAND, and its original cache unit S1 has been released. During the backend data transfer stage, the data from the cache units in the assembled cache unit groups is transferred to NAND. Figure 6In one embodiment, data from one cache unit is transferred to the NAND flash memory at a time, and the cache unit is released in response to the completion of the data transfer. Alternatively, data from one or more cache units in a cache unit group can be transferred to the NAND flash memory at a time, and the corresponding cache units are released according to the processing result of the programming commands given by the NAND flash memory.

[0116] Although Figure 6 The diagram illustrates cache units S1 and S2 provided by on-chip SRAM, and cache units D1 and D2 provided by off-chip DDR. Understandably, S1 / S2 can represent contiguous or non-contiguous storage space in the on-chip SRAM. The size of cache units S1 / S2 is, for example, 4KB, 1024KB, etc. Similarly, D1 / D2 can represent contiguous or non-contiguous storage space in the off-chip DDR. The size of cache units D1 / D2 is, for example, 4KB, 1024KB, etc. In one or more embodiments, cache units S1 / S2 and cache units D1 / D2 can have the same size.

[0117] like Figure 6 The diagram shown is a flowchart of an SSD data cache writing method according to a second embodiment of this application. The data cache method includes the following steps:

[0118] Step 1-1: At the front end, cache unit D2 receives the data to be written by the host through the PCIe interface; at the back end, cache unit group A transfers the data in cache unit S1 to NAND.

[0119] Step 1-2: Release cache unit S1.

[0120] Steps 1-3: Allocate the released cache unit S1 to receive data to be written by the host.

[0121] Step 2-1: At the front end, cache unit S1 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache unit D2 has been written with data but has not yet completed data assembly and is located in cache unit group B; at the back end, cache unit group A transfers the data in cache unit S2 to NAND.

[0122] Step 2-2: Release cache unit S2.

[0123] Steps 2-3: Allocate the released cache unit S2 to receive data to be written by the host.

[0124] Step 3-1: At the front end, cache unit S2 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache units D2 and S1 have been written with data but have not yet completed data assembly, and are located in cache unit group B; at the back end, cache unit group A transfers the data in cache unit D1 to NAND.

[0125] Step 3-2: Release cache unit D1.

[0126] Step 3-3: Allocate the released cache unit D1 to receive the data to be written by the host.

[0127] Step 4-1: At the front end, cache unit D1 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache units D2, S1 and S2 have been written with data and completed data assembly, and are assembled into cache unit group B. At the back end, cache unit group B transfers the data in cache unit D2 to NAND.

[0128] Step 4-2: Release cache unit D2.

[0129] Step 4-3: Allocate the released cache unit D2 to receive the data to be written by the host.

[0130] Step 5-1: At the front end, cache unit D2 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache unit D2 has been written with data but has not yet completed data assembly and is located in cache unit group C; at the back end, cache unit group B transfers the data in cache unit S1 to NAND.

[0131] Then, repeat the above method in a loop.

[0132] This application also provides more cache units. Figure 7 A flowchart of the SSD data cache writing method according to the third embodiment is shown. Figure 7 The data cache writing method provides cache units (S1, S2, S3, and S4) from on-chip SRAM and cache units (D1, D2, D3, and D4) from off-chip DDR. Although Figure 7 In this context, the number of cache units provided by the on-chip SRAM is the same as the number of cache units provided by the off-chip DDR. Understandably, the number of cache units provided by the on-chip SRAM and the number of cache units provided by the off-chip DDR can have other ratios and quantities.

[0133] exist Figure 7 In this embodiment, the backend data transmission phase maintains at most one cache unit group to transmit data to the NAND at any given time, and the data assembly phase also maintains at most one cache unit group at any given time. Therefore, Figure 7 In this embodiment, the number of cache units exceeds the usage demand, and some cache units are limited during use. The number of cache units used by the controller can be configured. The number of cache unit groups maintained by the backend data transmission phase and the data assembly phase can also be configured.

[0134] exist Figure 7In the embodiments, the same Figure 6 Compared to the previous embodiment, the difference also includes that the ratio of cache units from on-chip SRAM to cache units from off-chip DDR is different within the cache unit groups (A and B). Figure 6 In one embodiment, the memory cell group includes two cache cells from on-chip SRAM and one cache cell from off-chip DDR, while Figure 7 In one embodiment, the storage unit group (A and B) includes one cache unit from on-chip SRAM and two cache units from off-chip DDR. Figure 7 This configuration in the embodiment is the same as Figure 6 Compared to the previous implementation, the performance of the memory cell group in receiving and transmitting data decreases, but the demand for SRAM capacity also decreases. In some cases, Figure 7 Such implementations are needed, for example, when the controller cannot provide a large amount of SRAM space.

[0135] Because there are more cache units, Figure 7 In this embodiment, there are more available cache units to be allocated during the cache unit allocation phase. As one embodiment, during the cache unit allocation phase, cache units allocated in three consecutive steps (steps before step 1-1 (not shown), steps 1-3, and steps 2-3) are used to construct a cache unit group. These three cache units include one cache unit from on-chip SRAM and two cache units from off-chip DDR. The cache unit allocation phase selects the cache unit from on-chip SRAM and the cache unit from off-chip DDR in such a proportional relationship. The order in which these three cache units are allocated is not limited; for example, two cache units from off-chip DDR can be allocated first, followed by one cache unit from on-chip SRAM. Optionally, when the source of all cache units constituting a cache unit is not limited (e.g., in scenarios where there is no performance requirement for cache units or a performance consistency requirement), the cache unit allocation phase only needs to allocate available cache units without considering the source of the allocated cache units.

[0136] like Figure 7 The diagram shown is a flowchart of an SSD data caching writing method according to a third embodiment of this application. The data caching method includes the following steps:

[0137] In step S1-1, at the front end, cache unit D2 receives the data to be written by the host through the PCIe interface; at the back end, cache unit group A transfers the data in cache unit S1 to NAND.

[0138] Step S1-2: Release cache unit S1.

[0139] Steps S1-3: Allocate buffer unit S3 to receive data to be written by the host.

[0140] In step S2-1, at the front end, cache unit S3 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache unit D2 has been written with data but has not yet completed data assembly and is located in cache unit group B; at the back end, cache unit group A transfers the data in cache unit D4 to NAND.

[0141] Step S2-2: Release cache unit D4.

[0142] Step S2-3: Allocate buffer unit D3 to receive data to be written by the host.

[0143] In step S3-1, at the front end, cache unit D3 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache units D2 and S3 have been written with data but have not yet completed data assembly, and are located in cache unit group B; at the back end, cache unit group A transfers the data in cache unit D1 to NAND.

[0144] Step S3-2: Release cache unit D1.

[0145] Step S3-3: Allocate the released buffer unit D1 to receive data to be written by the host.

[0146] In step S4-1, at the front end, cache unit D1 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache units D2, S3 and D3 have been written with data and completed data assembly, and are assembled into cache unit group B. At the back end, cache unit group B transfers the data in cache unit D2 to NAND.

[0147] Step S4-2: Release cache unit D2.

[0148] Step S4-3: Allocate buffer unit S4 to receive data to be written by the host.

[0149] In step S5-1, at the front end, cache unit S4 receives the data to be written by the host through the PCIe interface; during the data assembly stage, cache unit D1 has been written with data but has not yet completed data assembly, and is located in cache unit group C; at the back end, cache unit group B transfers the data in cache unit S3 to NAND.

[0150] Then, repeat the above method in a loop.

[0151] like Figure 8 The diagram illustrates various cache unit allocation methods during the cache unit allocation phase of this application. As one embodiment, cache units from on-chip SRAM and cache units from off-chip DDR are allocated to each cache unit group in a specified ratio. Figure 3In this embodiment, cache units from on-chip SRAM and cache units from off-chip DDR are allocated in a 2:1 ratio. Figure 4 In this embodiment, cache units from on-chip SRAM and cache units from off-chip DDR are allocated in a 1:2 ratio. Understandably, a larger proportion of cache units from on-chip SRAM represents higher data transfer performance for the cache unit group. Therefore, the allocation ratio can be set according to the required performance needs.

[0152] As another example, available cache units are allocated solely based on their availability. This simplifies the complexity of the cache allocation phase.

[0153] As another embodiment, the source of the currently allocated cache unit is determined based on the source of the previously allocated cache unit. For example, if the previously allocated cache unit came from on-chip SRAM, then the current cache unit is allocated from off-chip DDR; conversely, if the previously allocated cache unit came from off-chip DDR, then the current cache unit is allocated from on-chip SRAM. This achieves a balanced use of on-chip SRAM and off-chip DDR, and also ensures that each cache unit group has cache units from SRAM, thus ensuring the basic performance of data transfer within the cache unit group.

[0154] As another embodiment, within a specified time period (e.g., 0.1s) or a specified number of cache unit groups (e.g., 10), the source ratio of the allocated cache units is maintained to provide substantially consistent performance across the specified ranges, such as substantially consistent data transfer bandwidth within each 0.1s period. To this end, the cache unit allocation phase identifies, for example, the proportion of cache units already allocated from on-chip SRAM within the current time period or cache unit group range. If this proportion exceeds a threshold corresponding to the target performance, cache units allocated from off-chip DDR are used; otherwise, cache units allocated from on-chip SRAM are used. This approach prioritizes allocating cache units from on-chip SRAM and also helps improve SSD performance.

[0155] like Figure 9 The diagram illustrates a fourth embodiment of the SSD data cache writing method of this application. It provides more cache units, maintaining two cache unit groups each during the data assembly phase and the backend data transmission phase. During the data transmission phase, the two cache unit groups concurrently write data to the NAND flash memory to fully utilize the concurrent capabilities of the SSD's multiple flash memory channels.

[0156] like Figure 9In the illustrated embodiment, for example, in step T1, although data transfers from cache unit S1 to NAND and from cache unit D3 to NAND are performed, these two data transfers to NAND are not completed at the start of step T2. Because more cache units are provided, the cache unit allocation operation in the cache unit allocation phase does not need to wait for the completion of the backend data transfer phase and / or the cache unit allocation phase. In some cases, such as when NAND processing programming commands fails, data transfer to NAND requires more time, and the release of the corresponding cache units is also delayed. The cache unit S3 allocated in step T2 is used to construct cache unit group C. The delayed completion of data transfers from cache unit groups A and B to NAND does not affect the construction of cache unit group C. The cache units of cache unit groups A and B in the backend data transfer phase to NAND do not need to be released simultaneously. After NAND provides the programming processing result, the corresponding cache units can be released individually. For example, in step T4, cache unit S1 of cache unit group A is released, while in step T7, cache units S2 and D3 of cache unit groups A and B are both released. Referring to step T10, the last cache unit D1 of cache unit group A is released, thus cache unit group A ceases to exist. However, at this time, cache unit groups C and D have not yet been fully constructed, and data transmission cannot be initiated from cache unit groups C and D during the backend data transmission to NAND phase. In step T14, cache unit group D is fully constructed, while cache unit group C is still not fully constructed. Therefore, cache unit group D enters the backend data transmission to NAND phase, starting data transmission to NAND from, for example, cache unit S3 of cache unit group D. Thus, the two cache unit groups in the data assembly phase can proceed without a specific order, but rather enter the backend data transmission to NAND phase in response to the completion of cache unit group construction. Further, referring to step T13, two cache units (S2 and S5) are allocated. Figure 9 The number of cache units allocated each time in an embodiment can also be varied, such as 1, 2 or other numbers.

[0157] Although Figure 9It is not shown that during the front-end data transfer phase, data can be transferred concurrently to multiple cache units. As can be understood from the embodiments of this application, each "step" is illustrative and does not imply that the next step can only begin after the previous step is completed. Operations in a phase can begin once the data or operational conditions required for that phase are met. This allows each module in each phase to execute its operations concurrently. For example, the cache unit allocation phase begins when, for instance, there are available cache units that meet certain conditions. The front-end data transfer phase begins when cache units are allocated and the host has data to transfer to the SSD. The data assembly phase begins when there are cache units filled with data, and optionally, the corresponding flash channel is also free. The back-end data transfer phase begins when there is a group of cache units that have been assembled. The cache unit release phase begins when the NAND indicates that the corresponding programming operation has been completed.

[0158] exist Figure 9 In the embodiments, cache unit group A and cache unit group B are shown to have different configurations. Cache unit group A has two cache units from on-chip SRAM, while cache unit group B has one cache unit from on-chip SRAM. Even if it is not the optimal implementation, Figure 9 The implementation method shown is also feasible.

[0159] like Figure 9 As shown, the SSD data cache writing method of the fourth embodiment of this application includes the following steps:

[0160] In step T1, at the front end, cache unit D2 receives the data to be written by the host through the PCIe interface; at the back end, cache unit group A transfers the data in cache unit S1 to NAND.

[0161] Step T2: Allocate buffer unit S3 to receive data to be written by the host.

[0162] In step T3, at the front end, cache unit S3 receives the data to be written by the host through the PCIe interface; in the data assembly area, cache unit D2 has already written data but has not yet completed assembly and is located in storage unit group C; at the back end, cache unit group A transfers the data in cache unit S2 to NAND, and cache unit group B transfers the data in cache unit D3 to NAND.

[0163] Step T4: Release cache unit S1.

[0164] Step T5: Allocate buffer unit D5 to receive data to be written by the host.

[0165] In step T6, at the front end, cache unit D5 receives data to be written by the host through the PCIe interface; in the data assembly area, cache unit D2 has been written with data but has not yet completed assembly and is located in storage unit group C, and cache unit S3 has been written with data but has not yet completed assembly and is located in storage unit group D; at the back end, cache unit group A transfers the data in cache unit D1 to NAND, and cache unit group B transfers the data in cache unit D4 to NAND.

[0166] Step T7: Release cache unit S2 and cache unit D3.

[0167] Step T8: Allocate buffer unit S1 to receive data to be written by the host.

[0168] In step T9, at the front end, cache unit S1 receives data to be written by the host through the PCIe interface; in the data assembly area, cache units D2 and D5 have been written with data but have not yet completed assembly and are located in storage unit group C, and cache unit S3 has been written with data but has not yet completed assembly and is located in storage unit group D; at the back end, cache unit group A transfers the data in cache unit D1 to NAND, and cache unit group B transfers the data in cache unit D4 to NAND.

[0169] Step T10: Release cache units D1 and D4.

[0170] Step T11: Allocate buffer unit D6 to receive data to be written by the host.

[0171] In step T12, at the front end, cache unit D6 receives the data to be written by the host through the PCIe interface; in the data assembly area, cache units D2 and D5 have been written with data but have not yet completed assembly and are located in storage unit group C, and cache units S3 and S1 have been written with data but have not yet completed assembly and are located in storage unit group D; at the back end, cache unit group B transfers the data of cache unit S4 to NAND.

[0172] Step T13: Allocate buffer units S2 and S5 to receive data to be written by the host.

[0173] In step T14, at the front end, cache unit S2 receives data to be written by the host through the PCIe interface; in the data assembly area, cache units D2 and D5 have been written with data but have not yet completed assembly and are located in storage unit group C, while cache units S3, S1 and D6 have been written with data and completed assembly, forming storage unit group D; at the back end, cache unit group B transfers the data in cache unit S4 to NAND, and cache unit group D transfers the data in cache unit S3 to NAND.

[0174] In another specific embodiment of this application, cache unit groups correspond to page stripes. Page stripes are a concept in the prior art. For example, an SSD controller organizes NAND storage space into blocks and page stripes. The controller writes data to the NAND in units of page stripes, where a page stripe becomes the smallest unit of programming operation maintained by the controller. On, for example, the 16 flash channels of an SSD, one or more page stripes can be operated concurrently. A block comprises a physical block from each of multiple logical units (LUNs). The multiple logical units that provide physical blocks for a block are called a logical unit group. Each logical unit in a logical unit group can provide a physical block for a block.

[0175] like Figure 10 The diagram shows a large block. A large block is constructed on a group of logic units, for example, 16 logic units (LUN0, LUN1, ..., LUN15). Figure 10 In this block, blocks 0 of LUN0-LUN15 constitute large block 0. Physical blocks 0 in each plane from LUN0 to LUN14 are used to store user data, while physical block 0 of LUN15 is used to store checksum data calculated based on the user data in large block 0. Blocks 1 of LUN0-LUN15 constitute large block 1. Figure 10 The document also demonstrates page striping. Page striping is constructed on large blocks, where physical pages with the same physical address within each physical block constitute a "page stripe". Figure 10 In this diagram, physical pages P0-0, P0-1, ..., and P0-X constitute page stripe 0. Physical pages P0-0, P0-1, ..., P0-14 are used to store user data, while physical page P0-X stores checksum data calculated from all user data within the stripe. Similarly, physical pages P2-0, P2-1, ..., and P2-X constitute page stripe 2. Optionally, the physical page used to store checksum data can be located anywhere within the page stripe. Understandably, other ways of organizing blocks and page stripes exist.

[0176] See again Figure 9 An SSD provides 16 flash memory channels. For example, page stripe A occupies flash memory channels 0-7, while page stripe B occupies flash memory channels 8-15. Cache unit group A provides data to be written to page stripe A, and cache unit group B provides data to be written to page stripe B. Therefore, the capacity of the cache unit group is the same as the capacity of the page stripe. The configuration of the page stripe (size, capacity, NAND physical page type, etc.) determines the required cache unit group.

[0177] Although Figure 9In the embodiments shown, a cache unit group comprises three cache units. Optionally, the size of the cache unit is not necessarily limited to the size of the physical page that constructs the page stripe. Thus, the cache unit group may include other numbers of cache units. For example, each cache unit may be 512 bytes in size, and the page stripe (cache unit group) may be 3072 KB in size. Thus, the cache unit group may comprise thousands of cache units. Smaller capacity cache units are advantageous for allocating storage space from the storage medium for the cache units.

[0178] According to another specific embodiment of this application, the first cache unit is a virtual cache unit provided by on-chip SRAM; the second cache unit is a virtual cache unit provided by off-chip DDR. Figure 11 In the illustrated embodiment, the cache units used are virtual cache units (B1-B8). By providing virtual cache units, the difference in storage media (on-chip SRAM or off-chip DDR) no longer needs to be considered during the cache unit allocation stage; instead, a specified number of virtual cache units are allocated solely for the purpose of accommodating front-end data. Figure 11 In one embodiment, one virtual cache unit is allocated each time.

[0179] Virtual cache units comprise storage space from, for example, on-chip SRAM and / or off-chip DDR. The ratio of on-chip SRAM to off-chip DDR storage space in a virtual cache unit is determined based on the required data transfer performance (bandwidth / latency). Thus, each virtual cache unit can have the same ratio, allowing the SSD to achieve substantially consistent performance when transferring data across each virtual cache unit. For example, to achieve the same... Figure 6 Similar to other implementations, in each virtual cache unit, the ratio of storage space from on-chip SRAM to off-chip DDR is 2:1. Optionally, each virtual cache unit can have a different ratio; for example, different performance virtual cache units can be used for users of shared storage devices or different namespaces, or different performance virtual cache units can be used at different lifecycles of the SSD to match variations in NAND performance. The construction of virtual cache units can be completed during the SSD initialization phase, rather than being implemented each time a virtual cache unit is allocated, thereby reducing... Figure 11 The processing latency of the illustrated embodiment is shown. The construction of virtual cache units can also be implemented during host I / O command processing to improve storage space utilization.

[0180] like Figure 11 As shown, this application provides a fifth embodiment of an SSD data cache writing method, which includes the following steps:

[0181] In step P1-1, at the front end, virtual cache unit B4 receives the data to be written by the host through the PCIe interface; at the back end, cache unit group A transfers the data of virtual cache unit B1 to NAND.

[0182] Step P1-2: Release virtual cache unit B1.

[0183] Steps P1-3: Allocate virtual cache unit B5 to cache data to be written by the host.

[0184] In step P2-1, at the front end, virtual cache unit B5 receives the data to be written by the host through the PCIe interface; during the data assembly stage, virtual cache unit B4 has written data but has not yet completed assembly and is located in cache unit group B; at the back end, cache unit group A transfers the data of virtual cache unit B2 to NAND.

[0185] Step P2-2: Release virtual cache unit B2.

[0186] Step P2-3: Allocate virtual cache unit B6 to cache the data to be written by the host.

[0187] In step P3-1, at the front end, virtual cache unit B6 receives the data to be written by the host through the PCIe interface; during the data assembly stage, virtual cache units B4 and B5 have written data but have not yet completed assembly, and are located in cache unit group B; at the back end, cache unit group A transfers the data of virtual cache unit B3 to NAND.

[0188] Step P3-2: Release virtual cache unit B3.

[0189] Step P3-3: Allocate virtual cache unit B7 to cache data to be written by the host.

[0190] In step P4-1, at the front end, virtual cache unit B7 receives the data to be written by the host through the PCIe interface; during the data assembly stage, virtual cache units B4, B5 and B6 have written data and completed assembly, forming cache unit group B; at the back end, cache unit group B transfers the data of virtual cache unit B4 to NAND.

[0191] Step P4-2: Release virtual cache unit B4.

[0192] Step P4-3: Allocate virtual cache unit B8 to cache the data that the host needs to write.

[0193] In step P5-1, at the front end, virtual cache unit B8 receives the data to be written by the host through the PCIe interface; during the data assembly stage, virtual cache unit B7 has written data but has not yet completed assembly and is located in cache unit group C; at the back end, cache unit group B transfers the data of virtual cache unit B5 to NAND.

[0194] Then, follow the above method to perform the subsequent procedures.

[0195] like Figure 12-15 The diagram illustrates various virtual cache units. Virtual cache units B, B1, B2, and B3 are virtual cache units, with physical cache units provided by DDR and SRAM respectively, simplifying the allocation of cache units. Figure 12 In this, the virtual cache unit B includes storage space S1 from on-chip SRAM and storage space D1 from off-chip DDR. Figure 13 In this configuration, virtual cache unit B1 includes storage spaces S1 and S2 from on-chip SRAM and storage space D1 from off-chip DDR. Therefore, virtual cache unit B and virtual cache unit B1 can have different performance characteristics. Virtual cache unit B1 includes more storage space from on-chip SRAM, thus its data transfer performance is higher. Figure 14 In the virtual cache unit B2, there are storage spaces S1 from the on-chip SRAM and storage spaces D1 and D2 from the off-chip DDR. Figure 15 In this configuration, virtual cache unit B3 includes storage spaces D1, D2, and D3 from off-chip DDR. Virtual cache unit B3 does not include storage space from on-chip SRAM.

[0196] like Figure 16 The diagram illustrates the cache unit allocation process applicable to virtual cache units. The virtual cache unit allocation process includes:

[0197] Allocate available virtual cache units;

[0198] Determine whether the proportion of cache capacity allocated from SRAM within a specified time period or a specified number of page stripes exceeds a preset threshold. If so, allocate virtual cache units that include more DDR space; otherwise, allocate virtual cache units that include more SRAM space.

[0199] Understandably, virtual cache units that include a larger proportion of on-chip SRAM space represent higher performance in data transfer within the virtual cache unit group. Therefore, the proportion of storage space provided by different storage media within the required virtual cache unit can be selected based on the desired performance requirements.

[0200] As one example, available virtual cache units are allocated solely based on their availability. This simplifies the complexity of the cache allocation phase. The allocated virtual cache units can have a pre-configured ratio of storage space sizes provided by different storage media.

[0201] As another embodiment, within a specified time period (e.g., 0.1s) or a specified number of cache unit groups (e.g., 10), in order to provide substantially consistent data transfer bandwidth, the proportion of storage space from, for example, on-chip SRAM in the allocated virtual cache units is identified. If it exceeds a first target threshold, virtual cache units including more off-chip DDR storage space are allocated; otherwise, virtual cache units including more on-chip SRAM storage space are allocated.

[0202] like Figure 17 The diagram shows a flowchart of a method for processing written data according to an embodiment of this application. The method includes the following steps:

[0203] Step Y1: Allocate cache units.

[0204] The allocation of cache units (including virtual cache units) has been described above, along with several other methods for allocating cache units.

[0205] Step Y2: Receive the data to be written to the SSD and fill it into the allocated cache unit;

[0206] The data written to the SSD comes from, for example, write commands sent to the SSD by the host.

[0207] Step Y3: Assemble the cache units filled with data into a cache unit group.

[0208] Step Y4: Determine if the cache units are assembled into a cache unit group. If yes, proceed to step Y5; otherwise, return to step Y4. The cache unit group is, for example, the same size as the minimum unit size for SSD programming operations.

[0209] Step Y5: Write the data of the cache unit group into the NAND flash.

[0210] Specifically, for the assembled cache unit group, the data in the cache unit group is used to initiate a programming operation on the NAND, and the data of the cache unit group is written into the NAND.

[0211] Step Y6: In response to successfully writing data to NAND, release the corresponding cache unit.

[0212] In the method for processing data writing in this application, the overall bandwidth for writing data to a cache unit group assembled from on-chip SRAM and off-chip DDR is higher than the bandwidth obtained by using only off-chip DDR as cache, and the latency is lower, thereby improving the overall performance of data writing.

[0213] Example 2

[0214] like Figure 18 As shown, this application provides a flash memory controller 13, which is used to transfer data cached in a first cache unit and / or a second cache unit to NAND. The data cached in the first cache unit and / or the second cache unit is data cached by allocating the data to be written to at least one first cache unit and / or at least one second cache unit according to a predetermined ratio. The first cache unit comes from on-chip SRAM 12, and the second cache unit comes from off-chip DDR 20.

[0215] Example 3

[0216] This application provides an SSD controller, such as... Figure 18 As shown, the SSD controller 10 includes:

[0217] 11 PCIe interface, 12 on-chip SRAM and 13 flash memory controller;

[0218] PCIe interface 11 is connected to the host for communication. PCIe interface 11 is used to receive data to be written from the host and allocate the data to be written to at least one first cache unit and / or at least one second cache unit according to a predetermined ratio. The first cache unit comes from the on-chip SRAM 12 and the second cache unit comes from the off-chip DDR 20.

[0219] One end of the on-chip SRAM 12 is connected to the PCIe interface 11, and the other end is connected to the flash memory controller 13. The on-chip SRAM 12 is used to write data allocated to the first cache unit.

[0220] The flash memory controller 13 is used to transfer data cached in the first cache unit and / or the second cache unit to NAND.

[0221] Example 4

[0222] like Figure 18 As shown, this application provides an SSD data caching and writing system, the system 100 including:

[0223] SSD controller 10 and off-chip DDR 20; SSD controller 10 includes PCIe interface 11, on-chip SRAM 12 and flash memory controller 13; one end of off-chip DDR 20 and on-chip SRAM 12 are communicatively connected to PCIe interface 11, and the other end of each is communicatively connected to flash memory controller 13; flash memory controller 13 is communicatively connected to NAND 300; SSD controller 10 is communicatively connected to host 200 through PCIe interface 11, PCIe interface 11 is used to receive data to be written by host 200; the data to be written is allocated to at least one first cache unit and / or at least one second cache unit according to a predetermined ratio, wherein the first cache unit is a cache unit from on-chip SRAM 12; the second cache unit is a cache unit from off-chip DDR 20;

[0224] The on-chip SRAM 12 is used to write data allocated to the first cache unit, and the off-chip DDR 20 is used to write data allocated to the second cache unit.

[0225] Flash memory controller 13 is used to transfer data cached in the first cache unit and / or the second cache unit to NAND;

[0226] The cache unit release module 30 is used to release the cache unit after the data transfer of the cache unit is completed.

[0227] According to another specific embodiment of this application, the first cache unit is a virtual storage space provided by on-chip SRAM; the second cache unit is a virtual storage space provided by off-chip DDR.

[0228] As a specific embodiment of this application, an SSD data caching and writing system can be a solid-state storage device or a solid-state hard drive.

[0229] As a specific embodiment of this application, the present invention can implement all or part of the processes in the above-described methods, or it can be accomplished by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0230] The beneficial effects achieved by this application are as follows:

[0231] (1) This application provides cache units at the same level for two different types of storage media, namely on-chip SRAM and off-chip DRAM. The cache units provided by the two storage media need to be provided in a certain ratio to improve the average bandwidth when the SSD transfers data to the cache unit, thereby improving the actual performance of SSD writing data.

[0232] (2) This application configures the capacity ratio and performance contribution ratio of SRAM and DDR as cache respectively, so as to obtain higher performance on a certain capacity basis by making more use of SRAM.

[0233] (3) In this application, multiple cache units allocated for data to be written to the host are assembled into a cache unit group, and the data of the cache units in the cache unit group are cached to NAND in turn. After the data transfer is completed, the cache unit is released and the released cache unit is reassigned to the host for caching data, thereby improving the utilization rate of the cache unit.

[0234] (4) This application determines the proportion of SRAM cache allocation by time period or multiple cache unit groups, promotes the reverse processing of QoS front-end data preparation order and NAND programming order, so as to create a difference in the utilization rate of DDR and SRAM, thereby improving the performance ratio of SRAM.

[0235] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for writing data cache to an SSD, characterized in that, The method includes the following steps: Get the data to be written; At least one first cache unit and at least one second cache unit are allocated to the data to be written according to a predetermined ratio, wherein the first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR; Write the data to be written to the allocated first and second cache units; Transfer the data cached in the first and second cache units to NAND; Transferring data cached in the first and second cache units to NAND includes: The first and second cache units that write data are combined into a cache unit group; Transfer the data cached in the cache unit group to NAND; The cache unit group includes one off-chip DDR and two on-chip SRAMs; When the first cache unit and the second cache unit form a cache unit group, multiple cache unit groups are formed in total. The off-chip DDR that constitutes the cache unit group is different in different cache unit groups, while the on-chip SRAM that constitutes the cache unit group is the same.

2. The SSD data cache writing method according to claim 1, characterized in that, After transferring the data cached in the first and second cache units to the NAND, the process also includes: In response to the completion of data transfer in a certain cache unit, the cache unit that has completed the data transfer is released. The released cache unit is then reallocated to receive new data to be written by the host. The certain cache unit is either a first cache unit or a second cache unit.

3. The SSD data cache writing method according to claim 1, characterized in that, The cache unit group transfers data in the order of data transfer and releases cache units sequentially in the order of data transfer, wherein the order of data transfer is either the order in which the first cache unit or the second cache unit was assembled or the reverse order in which they are transferred to the NAND.

4. The SSD data cache writing method according to claim 1, characterized in that, When transferring data cached in a cache unit group to NAND, the data in the first cache unit is transferred first, followed by the data in the second cache unit.

5. The SSD data cache writing method according to claim 1, characterized in that, The size of the cache unit group is equal to the size of the NAND programming unit.

6. The SSD data cache writing method according to claim 1, characterized in that, Allocating at least one first cache unit and at least one second cache unit for the data to be written includes: Identify the proportion of the first cache unit already allocated from the on-chip SRAM, and determine whether the proportion of the first cache unit exceeds the target threshold. If so, allocate the second cache unit from the off-chip DDR; otherwise, allocate the first cache unit from the on-chip SRAM.

7. The SSD data cache writing method according to claim 6, characterized in that, The first cache unit is a virtual cache unit provided by on-chip SRAM; the second cache unit is a virtual cache unit provided by off-chip DDR.

8. The SSD data cache writing method according to any one of claims 2-7, characterized in that, When the first cache unit and the second cache unit for writing data are combined into a cache unit group, the proportion of the second cache unit provided by off-chip DDR in different cache unit groups ranges from 40% to 60%.

9. A flash memory controller, characterized in that, The flash memory controller is used to transfer data cached in the first cache unit and the second cache unit to NAND, wherein the data cached in the first cache unit and the second cache unit is data cached by allocating the data to be written to at least one first cache unit and at least one second cache unit according to a predetermined ratio, wherein the first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR; Transferring data cached in the first and second cache units to NAND includes: The first and second cache units that write data are combined into a cache unit group; Transfer the data cached in the cache unit group to NAND; The cache unit group includes one off-chip DDR and two on-chip SRAMs; When the first cache unit and the second cache unit form a cache unit group, multiple cache unit groups are formed in total. The off-chip DDR that constitutes the cache unit group is different in different cache unit groups, while the on-chip SRAM that constitutes the cache unit group is the same.

10. An SSD controller, characterized in that, include: PCIe interface, on-chip SRAM and flash memory controller; The PCIe interface is communicatively connected to the host. The PCIe interface is used to receive data to be written from the host and allocate the data to be written to at least one first cache unit and at least one second cache unit according to a predetermined ratio. The first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR. One end of the on-chip SRAM is communicatively connected to the PCIe interface, and the other end is communicatively connected to the flash memory controller. The on-chip SRAM is used to write data allocated to the first cache unit. The flash memory controller is used to transfer the data cached in the first cache unit and the second cache unit to NAND; Transferring data cached in the first and second cache units to NAND includes: The first and second cache units that write data are combined into a cache unit group; Transfer the data cached in the cache unit group to NAND; The cache unit group includes one off-chip DDR and two on-chip SRAMs; When the first cache unit and the second cache unit form a cache unit group, multiple cache unit groups are formed in total. The off-chip DDR that constitutes the cache unit group is different in different cache unit groups, while the on-chip SRAM that constitutes the cache unit group is the same.

11. An SSD data caching and writing system, used to perform the method according to any one of claims 1-7, characterized in that, The system includes: SSD controller and off-chip DDR; the SSD controller includes a PCIe interface, on-chip SRAM and flash memory controller; The SSD controller communicates with the host through the PCIe interface. One end of both the off-chip DDR and the on-chip SRAM are communicated with the PCIe interface, and the other end of both are communicated with the flash memory controller. The flash memory controller is communicated with the NAND. The PCIe interface is used to receive data to be written from the host and allocate the data to be written to at least one first cache unit and at least one second cache unit according to a predetermined ratio, wherein the first cache unit comes from on-chip SRAM and the second cache unit comes from off-chip DDR. The on-chip SRAM is used to write data allocated to the first cache unit; The flash memory controller is used to transfer the data cached in the first cache unit and the second cache unit to NAND; The off-chip DDR is used to write data allocated to the second cache unit.

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