An in-memory computing circuit, an in-memory linear interpolation computing circuit, and a chip

Abstract

This invention relates to the field of in-memory computing technology, and in particular to an in-memory computing circuit, an in-memory linear interpolation computing circuit, and a chip. The in-memory computing circuit consists of a 4×4 memory array composed of 16 memory cells, and a shift calculation unit. Each row of memory cells is connected to a word line, and the four rows of memory cells are connected sequentially from top to bottom to word lines WL0 to WL3. Each column of memory cells is connected to a local bit line, and the four columns of memory cells are connected sequentially to local bit lines BL_IN1 to BL_IN4. The shift calculation unit includes four input terminals and five output terminals, with the four input terminals of the shift calculation unit corresponding one-to-one with the local bit lines BL_IN1 to BL_IN4. The circuit structure designed in this invention is simple, and a set of linear interpolation results can be calculated within one cycle; it reduces the power consumption during data transmission, while increasing the operation speed and occupying a smaller area.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and in particular to an in-memory computing circuit, as well as an in-memory linear interpolation computing circuit and chip that uses the in-memory computing circuit as the basic circuit. Background Technology

[0002] Due to the separation of computing and storage modules in traditional architectures, coupled with the inconsistent development speed of computing and storage modules, the von Neumann bottleneck problem has become increasingly prominent. The concept of in-memory computing emerged to address this issue. In-memory computing breaks through the traditional von Neumann bottleneck, achieving the integration of storage and logic units, hence also known as compute-storage integration. Unlike the traditional von Neumann architecture, it fundamentally avoids the data movement between computing modules and storage units caused by large-scale data processing. It enables the storage and processing of initial, intermediate, and final data within the same area, directly achieving compute-storage integration at the hardware level, thereby effectively reducing access power consumption and latency caused by the von Neumann bottleneck.

[0003] Currently, in-memory computing can be used to implement various algorithms, such as basic XOR and XOR. Linear interpolation is an interpolation method for one-dimensional data, estimating the value based on the left and right neighboring data points of the point to be interpolated in a one-dimensional sequence. It is widely used in image processing, where it can reasonably compensate for missing data or enlarge or reduce the size of images. While SRAM-based in-memory computing designs can implement various algorithms, such as basic XOR and XOR, performing linear interpolation in memory remains challenging. It incurs significant area overhead and cannot guarantee processing speed, sometimes even sacrificing the read / write advantages of SRAM. Summary of the Invention

[0004] Therefore, it is necessary to address the problem that existing SRAM-based in-memory computing designs cannot effectively implement in-memory linear interpolation calculations, and to provide an in-memory computing circuit, as well as an in-memory linear interpolation calculation circuit and chip that uses the in-memory computing circuit as the basic circuit.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] An in-memory computing circuit includes a 4×4 memory array consisting of 16 memory cells and a shift computing unit. Each row of memory cells is connected to a word line, and the four rows of memory cells are connected sequentially from top to bottom to word lines WL0 to WL3. Each column of memory cells is connected to a local bit line, and the four columns of memory cells are connected sequentially to local bit lines BL_IN1 to BL_IN4.

[0007] The shift calculation unit includes four input terminals and five output terminals. The four input terminals of the shift calculation unit are connected one-to-one with the local bit lines BL_IN1 to BL_IN4.

[0008] When the in-memory computing circuit performs linear interpolation calculations, it uses two sets of four-bit binary signals X, which are inverses of each other, as input from an external source. i and Control the word lines of any two rows of memory cells, according to signal X. i and The control then causes the data stored in the two rows of storage units to undergo multi-cycle shift addition operations in the shift calculation unit, so as to realize linear interpolation calculation of the data stored in the two rows of storage units.

[0009] Furthermore, the shift calculation unit includes adders AD0 to AD3 and a buffer register BU. The input terminals A_IN0 to A_IN3 of adders AD0 to AD3 serve as the input terminals of the shift calculation unit.

[0010] A switch K4 connects the output S4 of adder AD3 to the input of buffer register BU. The output of buffer register BU is connected to the input B_IN3 of adder AD3 via transmission gate T3. The output S3 of adder AD3 is connected to the input B_IN2 of adder AD2 via transmission gate T2. The output S2 of adder AD2 is connected to the input B_IN1 of adder AD1 via transmission gate T1. The output S1 of adder AD1 is connected to the input B_IN0 of adder AD0 via transmission gate T0. Adders AD0 to AD3 are connected end-to-end, and their series connection is controlled sequentially by switches K1 to K3.

[0011] Furthermore, the memory cell employs a 6T memory cell. The 6T memory cell includes two cross-coupled inverters I0 and I1, and two NMOS transistors N0 and N1. The gates of N0 and N1 are connected to the word line signal WL. The source of N0 is connected to the bit line BL_IN, and the drain of N0 is connected to the input terminal Q of inverter I0. The source of N1 is connected to the bit line BLB, and the drain of N1 is connected to the input terminal QB of inverter I1. The output terminal of inverter I0 is connected to the input terminal QB of inverter I1, and the output terminal of inverter I1 is connected to the input terminal Q of inverter I0.

[0012] Furthermore, when the shift calculation unit performs an addition operation, switches K1 to K4 are closed, and transmission gates T1 to T4 are closed. When the shift calculation unit performs a shift operation, switches K1 to K4 are opened, and transmission gates T1, T2, T3, and T4 are opened sequentially, while other transmission gates are closed when a transmission gate is opened.

[0013] Furthermore, when the in-memory computing circuit performs a selection operation, if the word line WL0 of the first row of memory cells is used to input the control signal X... i The word line WL1 of the second row of memory cells is used to input control signals. When control signal X i When the signal is low, word line WL1 is enabled and word line WL0 is disabled. When the control signal X... i When the level is high, word line WL0 is enabled and word line WL1 is disabled.

[0014] Furthermore, when the in-memory calculation circuit performs linear interpolation, if one of the memory cells A0 to A3 is controlled by the control signal X... i The control signal controls the internally stored data, which is denoted as A3A2A1A0; another row of storage units, B0 to B3, is controlled by the control signal. Control, internally stored data is denoted as B3B2B1B0; externally input control signal X i The binary data X3X2X1X0 = 1010, according to the control signal X i Select a memory cell and perform a four-cycle operation. The four-cycle operation method is as follows:

[0015] Cycle 1: Initialize adders AD0-AD3 internally (set to zero). Input X0. At this time, word line WL1 is on and word line WL0 is off. B0-B3 input data to the four adders AD0-AD3 through BL_IN1-BL_IN4. Switches K1-K4 are closed, and transmission gates T1-T4 are closed, completing the addition calculation of B3B2B1B0 and 0000. The result is denoted as S. 40 S 30 S 20 S 10 S 00 Output S 00 And it serves as the least significant bit of the final result, i.e., LSB.

[0016] Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 10 Transmit to AD0. Then close transmission gate T1 and open transmission gate T2, S 20 Transmit to AD1. Then close transmission gate T2 and open transmission gate T3, S 30 Transmit to AD2. Then close transmission gate T3 and open transmission gate T4, S 40 Transfer to AD3 to complete the shift.

[0017] Cycle 2: Input X1. At this time, word line WL1 is closed and word line WL0 is open. The operation process is the same as in Cycle 1, completing A3A2A1A0 and S. 40 S 30 S 20 S 10The addition calculation is denoted as S. 41 S 31 S 21 S 11 S 01 Output S 01 And it is used as the second least significant bit of the final result, i.e., LSB+1.

[0018] Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 11 Transmit to AD0. Then close transmission gate T1 and open transmission gate T2, S 21 Transmit to AD1. Then close transmission gate T2 and open transmission gate T3, S 31 Transmit to AD2. Then close transmission gate T3 and open transmission gate T4, S 41 Transfer to AD3 to complete the shift.

[0019] Cycle 3: Input X2. At this time, word line WL1 is turned on and word line WL0 is turned off. The operation process is the same as in cycle 2, completing B3B2B1B0 and S. 41 S 31 S 21 S 11 The addition calculation is denoted as S. 42 S 32 S 22 S 12 S 02 Output S 02 And it is used as the second least significant bit of the final result, i.e., LSB+2.

[0020] Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 12 Transmit to AD0. Then close transmission gate T1 and open transmission gate T2, S 22 Transmit to AD1. Then close transmission gate T2 and open transmission gate T3, S 32 Transmit to AD2. Then close transmission gate T3 and open transmission gate T4, S 42 Transfer to AD3 to complete the shift.

[0021] Cycle 4: Input X3. At this time, word line WL1 is closed and word line WL0 is open. The operation process is the same as in cycle 3, completing A3A2A1A0 and S. 42 S 32 S 22 S 12 The addition calculation is denoted as S. 43 S 33 S 23 S 13 S 03 And as the high five digits of the final result.

[0022] Furthermore, based on the control of X3X2X1X0, the linear interpolation calculation result of the two rows of storage cells A0~A3 and B0~B3 is S. 43 S 33 S 23 S 13 S 03 S 02 S 01 S 00 .

[0023] The present invention also relates to an in-memory linear interpolation calculation circuit, including an in-memory calculation unit array, word lines WL, bit line pairs, switches S, a word line control module, a precharge circuit, a row decoding circuit, and a timing control module.

[0024] The in-memory computing unit array consists of N 2 The in-memory computing units are arranged in an N×N array.

[0025] There are 4N word lines (WL), which are used to control the on and off of the transmission tubes in each line of memory computing unit.

[0026] Bit line pairs consist of 4N pairs of bit lines BL and BLB. Each in-memory computing unit in each column is connected to the same bit line BLB.

[0027] There are 4N switches S, which are used to connect the local bit lines BL_IN of each column of in-memory computing units in the in-memory computing unit array to the same bit line BL.

[0028] The word line control module is used to control the opening or closing of the word lines (WL) connected to each in-memory computing unit in the in-memory computing array.

[0029] The precharge circuit is used to precharge the bit lines BL and BLB connected to each column of in-memory compute units in the in-memory compute unit array.

[0030] The row decoding circuit is used to decode the input signal and control the word line driving module according to the decoding result.

[0031] The timing control module is used to provide the pulse signals required for reading, writing, and linear interpolation calculations to the in-memory computing unit array.

[0032] In particular, the in-memory computing unit adopts the circuit structure of the in-memory computing circuit as described above, and can realize the complete function of the in-memory computing circuit.

[0033] Furthermore, when the in-memory linear interpolation calculation circuit performs storage, read, and write operations, it closes switch S to connect BL and BL_IN.

[0034] When the in-memory linear interpolation calculation circuit performs linear interpolation calculation, switch S is turned off, so that BL and BL_IN are not connected.

[0035] The present invention also relates to an in-memory linear interpolation calculation chip, which is packaged from the aforementioned in-memory write-back multiplication calculation circuit.

[0036] Furthermore, the interface of the in-memory linear interpolation calculation chip includes at least a power interface VDD, a ground interface VSS, a charging interface PRE, an input signal interface X_IN, a row strobe interface A, and an output signal interface S.

[0037] The power interface VDD is used to connect to the power supply.

[0038] The grounding interface VSS is used for grounding.

[0039] The charging interface PRE is used to input control signals to adjust the charging status of each line.

[0040] The input signal interface X_IN is used to input corresponding control signals to the word lines connected to each row of in-memory computing units in the in-memory computing unit array.

[0041] The row strobe interface A is used to input row strobe signals to the circuit. The row strobe signals are used to adjust the access status of each memory computing unit on each word line.

[0042] The output signal interface S is used to read the data stored in each storage unit or to read the linear interpolation results of each shift calculation unit.

[0043] The technical solution provided by this invention has the following beneficial effects:

[0044] The circuit structure designed in this invention is simple and can calculate a set of linear interpolation results within one cycle. Compared with the traditional von Neumann architecture, which performs calculations in memory and then in the processor, this circuit reduces the power consumption during data transfer and improves the speed and efficiency of computation. Furthermore, this circuit can also perform normal SRAM read / write functions by adding a set of bit lines and using switches to control the selection of different modes, thereby increasing the computational speed and occupying a smaller area. Attached Figure Description

[0045] Figure 1 This is a circuit diagram of an in-memory computing circuit according to Embodiment 1 of the present invention;

[0046] Figure 2 Based on Figure 1 A circuit diagram of the mobile computing unit;

[0047] Figure 3 A schematic diagram illustrating the concept of unilinear interpolation;

[0048] Figure 4 This is a conceptual diagram of bilinear interpolation;

[0049] Figure 5 Based on Figure 1 A schematic diagram of bit line connectivity during period 1 when the in-memory computing circuit performs linear interpolation calculations;

[0050] Figure 6 Based on Figure 5 A schematic diagram of bit line connectivity during period 2 when the in-memory computing circuit performs linear interpolation calculations;

[0051] Figure 7 Based on Figure 6 A schematic diagram of the bit line connectivity during period 3 when the in-memory computing circuit performs linear interpolation calculation;

[0052] Figure 8 Based on Figure 7 A schematic diagram of bit line connectivity during period 4 when the in-memory computing circuit performs linear interpolation calculation;

[0053] Figure 9 Based on Figures 5-8 Timing waveform diagram of the in-memory computing circuit performing linear interpolation calculation;

[0054] Figure 10 Based on Figure 1 A circuit diagram of a 6T storage unit;

[0055] Figure 11 This is a circuit diagram of an in-memory linear interpolation calculation circuit according to Embodiment 2 of the present invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Example 1

[0058] Please see Figure 1 , Figure 1 A circuit diagram of an in-memory computing circuit is shown. This embodiment introduces an in-memory computing circuit, which includes a 4×4 memory array consisting of 16 memory cells and a shift computing unit.

[0059] Each row of memory cells is connected to one word line, and the four rows of memory cells are connected sequentially from top to bottom to word lines WL0 to WL3. Each column of memory cells is connected to one local bit line, and the four columns of memory cells are connected sequentially to local bit lines BL_IN1 to BL_IN4.

[0060] Please see Figure 2 , Figure 2 A circuit diagram of the shift calculation unit is shown. The shift calculation unit includes four input terminals and five output terminals. The four input terminals of the shift calculation unit are connected one-to-one with the local bit lines BL_IN1 to BL_IN4. The specific circuit structure of the shift unit is as follows: The shift calculation unit includes adders AD0 to AD3 and a buffer register BU. The input terminals A_IN0 to A_IN3 of adders AD0 to AD3 serve as the input terminals of the shift calculation unit.

[0061] A switch K4 connects the output S4 of adder AD3 to the input of buffer register BU. The output of buffer register BU is connected to the input B_IN3 of adder AD3 via transmission gate T3. The output S3 of adder AD3 is connected to the input B_IN2 of adder AD2 via transmission gate T2. The output S2 of adder AD2 is connected to the input B_IN1 of adder AD1 via transmission gate T1. The output S1 of adder AD1 is connected to the input B_IN0 of adder AD0 via transmission gate T0. Adders AD0 to AD3 are connected end-to-end, and their series connection is controlled sequentially by switches K1 to K3.

[0062] When the in-memory computing circuit performs linear interpolation calculations, it uses two sets of four-bit binary signals X, which are inverses of each other, as input from an external source. i and Control the word lines of any two rows of memory cells, according to signal X. i and The control then causes the data stored in the two rows of storage units to undergo multi-cycle shift addition operations in the shift calculation unit, so as to realize linear interpolation calculation of the data stored in the two rows of storage units.

[0063] To facilitate the explanation of the linear interpolation calculation implemented in this circuit, we will first introduce the concept of linear interpolation. Linear interpolation refers to an interpolation method where the interpolation function is a first-order polynomial, and the interpolation error at the interpolation nodes is zero. In image processing, linear interpolation algorithms can reduce jagged edges and blurring. Single linear interpolation performs linear interpolation in only one direction, such as the X-axis. Figure 3 As shown, given the coordinates (x0, y0) and (x1, y1), to obtain the intermediate coordinate, assuming the intermediate coordinate is (x, y), it can be calculated using the following formula:

[0064]

[0065] The formula is simplified to the following formula:

[0066]

[0067] Based on unilinear interpolation, bilinear interpolation can be performed, which essentially involves performing unilinear interpolation once in each of the two directions. For example... Figure 4 As shown, the specific process is as follows:

[0068] Given coordinates A 11 (x0,y0), A 21 (x1,y0), A 12 (x0,y1), A 22 Given (x1, y1), we first perform two linear interpolations in the x-direction to obtain the coordinates of B1 and B2 as follows:

[0069]

[0070] Then perform a single linear interpolation in the y-direction to obtain the coordinates of C:

[0071]

[0072] This achieves bilinear interpolation, which can be used in image processing in practical applications. This embodiment implements single-linear interpolation in in-memory operations, and then implements bilinear interpolation based on this. As is well known, in-memory operations only have two different values, 0 and 1, which is to implement the algorithm AX+B(1-X), where A, B, and X are all 4-bit binary numbers, and X and 1-X are inverses of each other. To implement the AX+B(1-X) algorithm, two multiplications and one addition are first performed to complete the single-linear interpolation operation. Two more single-linear interpolations are then performed on top of the single-linear interpolation to complete the bilinear interpolation.

[0073] However, this embodiment uses a different approach. This embodiment utilizes the special relationship that X and 1-X are each other's complements. Given that A, B, and X are all 4-bit binary numbers, X... i The four binary digits are defined as X3, X2, X1, and X0. The process involves determining X... i In the case of X, choose A or B for the calculation. i If the value is 1, choose A; otherwise, choose B. Assuming the data is selected correctly, the algorithm AX+B(1-X) can be completed by performing a shift operation after each selection.

[0074] Therefore, the circuit in this embodiment needs to perform two parts when performing linear interpolation calculations: selection and shifting.

[0075] 1. Selection: Select the two rows of storage units for the linear interpolation calculation. Taking the first and second rows of storage units as examples, the first row of storage units is denoted as A0 to A3, and the data stored inside is denoted as A3A2A1A0. The second row of storage units is denoted as B0 to B3, and the data stored inside is denoted as B3B2B1B0. Assume that A0 to A3 are controlled by signal X... i Control, B0 to B3 are controlled by control signals Control, when control signal X i When the signal is low, word line WL1 is enabled and word line WL0 is disabled. When the control signal X... i When the signal is high, word line WL0 is enabled and word line WL1 is disabled. This completes the selection process.

[0076] 2. Shift: Based on X i The four-bit binary number requires four cycles of computation. At the end of each cycle, the result needs to be right-shifted for use in the next cycle. At the beginning of each cycle, all transmission gates are closed, and K1, K2, K3, and K4 are closed for a 4-bit + 4-bit addition operation. After the calculation phase, a shift operation is performed. First, K1, K2, K3, and K4 are closed, and SW1 of transmission gate T1 is opened, allowing the data of S1 to be passed to the lower-order input for the next cycle. Then, SW1 is closed, and SW3 of transmission gate T2 is opened, passing the data of S2 to the lower-order input. Next, SW3 is closed, and SW5 of transmission gate T3 is opened, passing the data of S3 to the lower-order input. Finally, SW5 is closed, and SW7 of transmission gate T4 is opened, passing the data of S4 to the highest-order input. This completes the entire shift process, and the output of S0 is used as the least significant bit of the final result. At the start of the next cycle, all transmission gates are closed, and K1, K2, K3, and K4 are all closed, continuing to perform the same operation as the previous cycle.

[0077] With control signal X i The four-bit binary data is X3X2X1X0=1010. A detailed explanation of the four-cycle operation is provided.

[0078] Cycle 1: Initialize the adders AD0 to AD3 internally, i.e., set them to zero. For example... Figure 5 As shown, when inputting X0, word line WL1 is open and word line WL0 is closed. Data from B0 to B3 is input to four adders AD0 to AD3 through BL_IN1 to BL_IN4. Switches K1 to K4 are closed, and transmission gates T1 to T4 are closed, completing the addition calculation of B3B2B1B0 and 0000. The result is denoted as S. 40 S 30 S 20 S 10 S 00 Output S00 And it serves as the least significant bit of the final result, i.e., LSB.

[0079] Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 10 Transmit to AD0. Then close transmission gate T1 and open transmission gate T2, S 20 Transmit to AD1. Then close transmission gate T2 and open transmission gate T3, S 30 Transmit to AD2. Then close transmission gate T3 and open transmission gate T4, S 40 Transfer to AD3 to complete the shift.

[0080] Period 2: such as Figure 6 As shown, inputting X1 will turn word line WL1 off and word line WL0 on. The operation process is the same as in cycle 1, completing A3A2A1A0 and S. 40 S 30 S 20 S 10 The addition calculation is denoted as S. 41 S 31 S 21 S 11 S 01 Output S 01 And it is used as the second least significant bit of the final result, i.e., LSB+1.

[0081] Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 11 Transmit to AD0. Then close transmission gate T1 and open transmission gate T2, S 21 Transmit to AD1. Then close transmission gate T2 and open transmission gate T3, S 31 Transmit to AD2. Then close transmission gate T3 and open transmission gate T4, S 41 Transfer to AD3 to complete the shift.

[0082] Period 3: such as Figure 7 As shown, inputting X2 will activate word line WL1 and deactivate word line WL0. The operation process is the same as in cycle 2, completing B3B2B1B0 and S. 41 S 31 S 21 S 11 The addition calculation is denoted as S. 42 S 32 S 22 S 12 S 02 Output S 02 And it is used as the second least significant bit of the final result, i.e., LSB+2.

[0083] Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 12Transmit to AD0. Then close transmission gate T1 and open transmission gate T2, S 22 Transmit to AD1. Then close transmission gate T2 and open transmission gate T3, S 32 Transmit to AD2. Then close transmission gate T3 and open transmission gate T4, S 42 Transfer to AD3 to complete the shift.

[0084] Period 4: such as Figure 8 As shown, inputting X3 will close word line WL1 and open word line WL0. The operation process is the same as in cycle 3, completing A3A2A1A0 and S. 42 S 32 S 22 S 12 The addition calculation is denoted as S. 43 S 33 S 23 S 13 S 03 And as the high five digits of the final result.

[0085] Therefore, the linear interpolation result of the two rows of storage cells A0~A3 and B0~B3 is S. 43 S 33 S 23 S 13 S 03 S 02 S 01 S 00 .

[0086] To further illustrate the four-cycle operation, we will use A3A2A1A0=1111, B3B2B1B0=1101, and X3X2X1X0=1010 as examples.

[0087] At the start of cycle 1, X0 = 0. The bit lines of the second row are now open, and B3B2B1B0 is passed to the input of the shift calculation unit via BL_IN. All transmission gates are closed, and K1, K2, K3, and K4 are all closed. The shift circuit is in its initialized state, i.e., internally set to 0. The shift calculation unit completes the calculation of 1101 + 0000, obtaining the result S. 40 S 30 S 20 S 10 S 00 =01101, least significant bit S 00 =1 is used as the least significant bit of the final result. Then, the transmission gates are opened sequentially, and 0110 is passed to the shift calculation unit by right shifting.

[0088] Then, in cycle 2, X1 = 1. The adder in the shift calculation unit receives 0110 at one input terminal B_IN, while the other input terminal A_IN receives... The control is selected as 1111, so the adder performs the calculation 0110 + 1111, and obtains the result S. 41 S 31 S 21 S 11 S 01 =10101, least significant bit result S 01 =1 is the second to last digit of the final result. Then, the shifting process is completed so that the input for the next round is 1010.

[0089] After cycle 3 begins, the adder's B_IN input is 1010, and the other input terminal A_IN of the adder in the X2=0 shift calculation unit is 1101, thus obtaining the calculation result S. 42 S 32 S 22 S 12 S 02 =10111, the least significant bit result S 02 =1 represents the third to last bit of the final result. Then, the shifting process is completed so that the input for the next round is 1011.

[0090] Then, continuing with cycle 4, input 1111 through the input terminal A_IN of the X3=1 adder, and input 1011 through the other input terminal of the adder in the shift calculation unit, resulting in S. 43 S 33 S 23 S 13 S 03 =11010, which is also the high five bits of the final result. Thus, the final result is S. 43 S 33 S 23 S 13 S 03 S 02 S 01 S 00 =11010111. The most important aspect to focus on during this process is timing. In each cycle, the selection and shift operations are separated. The specific timing diagram is shown below. Figure 9 As shown.

[0091] Since the in-memory computing unit has 4 rows of storage units, according to X i and The two lines of signal connection are used for control to implement the AX+C(1-X) algorithm, and so on, which can achieve 16 different combinations.

[0092] The requirements specify that the memory cells mentioned in this embodiment can be conventional memory cells with different numbers of transistors, such as 6T, 8T, 10T, 12T, etc., but are not limited to the mentioned memory cells, as long as they can achieve the same function as the aforementioned memory cells in the circuit. Furthermore, the internal circuit connections are not limited to any particular form.

[0093] For example, in this embodiment, taking a 6T storage unit as an example, a corresponding in-memory computing unit is designed. Figure 10 The circuit diagram of a 6T memory cell is shown. The 6T memory cell includes two cross-coupled inverters I0 and I1, and two NMOS transistors N0 and N1. The gates of N0 and N1 are connected to the word line signal WL. The source of N0 is connected to the bit line BL_IN, and the drain of N0 is connected to the input terminal Q of inverter I0. The source of N1 is connected to the bit line BLB, and the drain of N1 is connected to the input terminal QB of inverter I1. The output terminal of inverter I0 is connected to the input terminal QB of inverter I1, and the output terminal of inverter I1 is connected to the input terminal Q of inverter I0.

[0094] In summary, the circuit structure provided by this invention is simple, using 6T SRAM cells as the basic unit, and can calculate a set of linear interpolation results within one cycle. Compared with the traditional von Neumann architecture where calculations are performed in memory and then in the processor, this circuit reduces the energy consumption during data transfer and improves the speed and efficiency of computation. Furthermore, the four rows of memory cells share a single shift calculation unit, reducing the area occupied.

[0095] Example 2

[0096] This embodiment relates to an in-memory linear interpolation calculation circuit, including an in-memory calculation unit array, word lines WL, bit line pairs, switches S, a word line control module, a precharge circuit, a row decoding circuit, and a timing control module.

[0097] The in-memory computing unit array consists of N 2 The in-memory computing units are arranged in an N×N array.

[0098] There are 4N word lines (WL), which are used to control the on and off of the transmission tubes in each line of memory computing unit.

[0099] Bit line pairs consist of 4N pairs of bit lines BL and BLB. Each in-memory computing unit in each column is connected to the same bit line BLB.

[0100] There are 4N switches S, which are used to connect the local bit lines BL_IN of each column of in-memory computing units in the in-memory computing unit array to the same bit line BL.

[0101] The word line control module is used to control the opening or closing of the word lines (WL) connected to each in-memory computing unit in the in-memory computing array.

[0102] The precharge circuit is used to precharge the bit lines BL and BLB connected to each column of in-memory compute units in the in-memory compute unit array.

[0103] The row decoding circuit is used to decode the input signal and control the word line driving module according to the decoding result.

[0104] The timing control module is used to provide the pulse signals required for reading, writing, and linear interpolation calculations to the in-memory computing unit array.

[0105] In particular, the in-memory computing unit adopts the circuit structure of the in-memory computing circuit as described above, and can realize the complete function of the in-memory computing circuit.

[0106] When the in-memory linear interpolation calculation circuit performs storage, read, and write operations, it closes switch S, connecting BL and BL_IN. When the in-memory linear interpolation calculation circuit performs linear interpolation calculation operations, it opens switch S, disconnecting BL and BL_IN.

[0107] The difference between this embodiment and Embodiment 1 is that this embodiment uses an array to form a large-scale in-memory computing circuit array, which, in conjunction with other circuits, constitutes a complete in-memory linear interpolation computing circuit. Therefore, this embodiment can realize the linear interpolation operations and other operations in Embodiment 1.

[0108] Furthermore, this embodiment adds a BL_IN bit line to the original two sets of bit lines (BL and BLB) for the calculation process. A switch controls BL and BL_IN; when the array is performing storage, read, or write operations, the switch is closed, and BL and BL_IN function as a single bit line, enabling normal SRAM operation. To further ensure other functions of the storage unit, a switch can be added between BL_IN and the shift calculation unit. This allows BL_IN to be connected to BL while simultaneously disconnecting from the shift circuit when the circuit is not performing linear interpolation, thus enabling the circuit to perform other functions.

[0109] The following is combined with Figure 11 The solution of this embodiment will be described in detail: In Figure 11In the original 6T memory cells, a 64×64 distribution was used. However, in this embodiment, a basic unit circuit is constructed using 4×4 6T memory cells and a shift computation unit. Therefore, the final in-memory computation unit array is actually a 16×16 distribution. This is because in the original 6T memory cell array, every four adjacent columns form a column of the new circuit, and every four adjacent rows of memory cells form a row of the new circuit. Therefore, in the final in-memory computation unit array, the basic circuit in any row and column includes 4×4 6T memory cells and a shift computation unit.

[0110] It should be noted that for a row of in-memory computing units, their 6T memory cells are all connected to the same word line WL. For a column of in-memory computing units, their local bit line BL_IN is connected to the same global bit line BL via switch S. When switch S is closed, BL_IN and BL are equivalent to one bit line, allowing normal SRAM read and write operations, consistent with the original SRAM memory cells. That is, each memory cell is located through the word line and bit line, and the data in the corresponding memory node is retrieved. When switch S is open, BL_IN and BL are two bit lines, at which point the in-memory computing unit can perform linear interpolation calculations.

[0111] according to Figure 11 As shown, taking a basic unit circuit, namely the in-memory computing unit, as an example: 16 basic 6T memory cells are arranged in a 4×4 layout, with a shift circuit inserted in the middle. The 4 6T memory cells in the first row are connected to WL0, the 4 6T memory cells in the second row are connected to WL1, the 4 6T memory cells in the third row are connected to WL2, the 4 6T memory cells in the fourth row are connected to WL3, the 4 6T memory cells in the first column are connected to BL_IN1, the 4 6T memory cells in the second column are connected to BL_IN2, the 4 6T memory cells in the third column are connected to BL_IN3, and the 4 6T memory cells in the fourth column are connected to BL_IN4. The local bit lines BL_IN1 to BL_IN4 are connected to the shift computing unit. BL_IN1 is connected to BL1 through S1, BL_IN2 is connected to BL2 through S2, BL_IN3 is connected to BL3 through S3, and BL_IN4 is connected to BL4 through S4.

[0112] It should be noted that the 6T-SRAM storage cells and the 64×64 in-memory computing unit array distribution are examples listed in this embodiment to illustrate the solution, and are not intended to limit the scope of this case. In other embodiments, based on the same technical concept, other types of storage cells can be used to form other arrays of a larger scale to obtain the required "computing unit array".

[0113] This embodiment not only has the same effect as Embodiment 1, but also allows for full array operations in the array constructed based on Embodiment 1.

[0114] Example 3

[0115] This embodiment provides an in-memory linear interpolation calculation chip, which is packaged from the in-memory linear interpolation calculation circuit in Embodiment 2. The interface of the in-memory linear interpolation calculation chip includes at least a power interface VDD, a ground interface VSS, a charging interface PRE, an input signal interface X_IN, a row strobe interface A, and an output signal interface S.

[0116] The system includes the following interfaces: Power Interface VDD for connecting to the power supply; Ground Interface VSS for grounding; Charging Interface PRE for inputting control signals to adjust the charging status of each word line; Input Signal Interface X_IN for inputting corresponding control signals to the word lines connected to each row of the in-memory compute unit array; Row strobe Interface A for inputting row strobe signals to the circuit, which adjust the connection status of each in-memory compute unit on each word line; and Output Signal Interface S for reading data stored in each memory cell or reading the linear interpolation results of each shift compute unit.

[0117] This implementation, by packaging it into a chip, makes it easier to promote and apply in-memory linear interpolation calculation circuits.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An in-memory computing circuit, characterized in that, It includes a 4×4 memory array consisting of 16 memory cells and a shift calculation unit; each row of memory cells is connected to a word line, and the four rows of memory cells are connected to word lines WL0 to WL3 from top to bottom; each column of memory cells is connected to a local bit line, and the four columns of memory cells are connected to local bit lines BL_IN1 to BL_IN4 in sequence. The shift calculation unit includes four input terminals and five output terminals. The four input terminals of the shift calculation unit are connected one-to-one with the local bit lines BL_IN1 to BL_IN4. When the in-memory computing circuit performs linear interpolation calculations, it uses two sets of four-bit binary signals X, which are inverses of each other, as input externally. i and Control the word lines of any two rows of memory cells, according to signal X. i and The control then causes the data stored in the two rows of storage units to undergo multi-cycle shift addition operations in the shift calculation unit, so as to realize linear interpolation calculation of the data stored in the two rows of storage units.

2. The in-memory computing circuit according to claim 1, characterized in that, The shift calculation unit includes adders AD0 to AD3 and a buffer register BU; the input terminals A_IN0 to A_IN3 of adders AD0 to AD3 serve as the input terminals of the shift calculation unit. A switch K4 connects the output S4 of adder AD3 to the input of buffer register BU. The output of buffer register BU is connected to the input B_IN3 of adder AD3 through transmission gate T3. The output S3 of adder AD3 is connected to the input B_IN2 of adder AD2 through transmission gate T2. The output S2 of adder AD2 is connected to the input B_IN1 of adder AD1 through transmission gate T1. The output S1 of adder AD1 is connected to the input B_IN0 of adder AD0 through transmission gate T0. Adders AD0 to AD3 are connected end-to-end, and their series connection is controlled sequentially by switches K1 to K3.

3. The in-memory computing circuit according to claim 2, characterized in that, The memory cell is a 6T memory cell; the 6T memory cell includes two cross-coupled inverters I0 and I1, and two NMOS transistors N0 and N1; wherein, the gates of N0 and N1 are connected to the word line signal WL; the source of N0 is connected to the bit line BL_IN, the drain of N0 is connected to the input terminal Q of inverter I0, the source of N1 is connected to the bit line BLB, the drain of N1 is connected to the input terminal QB of inverter I1, the output terminal of inverter I0 is connected to the input terminal QB of inverter I1, and the output terminal of inverter I1 is connected to the input terminal Q of inverter I0.

4. The in-memory computing circuit according to claim 3, characterized in that, When the shift calculation unit performs an addition operation, switches K1 to K4 are closed and transmission gates T1 to T4 are closed; when the shift calculation unit performs a shift operation, switches K1 to K4 are opened, and transmission gates T1, T2, T3, and T4 are opened sequentially, while other transmission gates are closed when the transmission gate is opened.

5. The in-memory computing circuit according to claim 4, characterized in that, When the in-memory computing circuit performs a selection operation, if the word line WL0 of the first row of memory cells is used to input the control signal X... i The word line WL1 of the second row of memory cells is used to input control signals. When control signal X i When the signal is low, word line WL1 is enabled and word line WL0 is disabled; when the control signal X... i When the level is high, word line WL0 is enabled and word line WL1 is disabled.

6. The in-memory computing circuit according to claim 5, characterized in that, When the in-memory calculation circuit performs linear interpolation, if one of the memory cells A0 to A3 is controlled by the control signal X... i The control signal controls the internally stored data, which is denoted as A3A2A1A0; another row of storage units, B0 to B3, is controlled by the control signal. Control, internally stored data is denoted as B3B2B1B0; externally input control signal X i The binary data X3X2X1X0 = 1010, according to the control signal X i Select a memory cell and perform a four-cycle operation. The four-cycle operation method is as follows: Cycle 1; Initialize adders AD0-AD3 internally to zero; Input X0, at this time word line WL1 is open and word line WL0 is closed. B0-B3 input data to the four adders AD0-AD3 through BL_IN1-BL_IN4. Switches K1-K4 are closed, and transmission gates T1-T4 are closed, completing the addition calculation of B3B2B1B0 and 0000. The result is denoted as S. 40 S 30 S 20 S 10 S 00 Output S 00 And it is used as the least significant bit of the final result, i.e., LSB; Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 10 Transmit to AD0; then close transmission gate T1 and open transmission gate T2, S 20 Transmit to AD1; then close transmission gate T2 and open transmission gate T3, S 30 Transmit to AD2; then close transmission gate T3 and open transmission gate T4, S 40 The data is transferred to AD3 to complete the shift. Cycle 2; Input X1. At this time, word line WL1 is closed and word line WL0 is open. The operation process is the same as in cycle 1, completing A3A2A1A0 and S. 40 S 30 S 20 S 10 The addition calculation is denoted as S. 41 S 31 S 21 S 11 S 01 Output S 01 And it is used as the second least significant bit of the final result, i.e., LSB+1; Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 11 Transmit to AD0; then close transmission gate T1 and open transmission gate T2, S 21 Transmit to AD1; then close transmission gate T2 and open transmission gate T3, S 31 Transmit to AD2; then close transmission gate T3 and open transmission gate T4, S 41 The data is transferred to AD3 to complete the shift. Cycle 3; Input X2. At this time, word line WL1 is turned on and word line WL0 is turned off. The operation process is the same as in cycle 2, completing B3B2B1B0 and S. 41 S 31 S 21 S 11 The addition calculation is denoted as S. 42 S 32 S 22 S 12 S 02 Output S 02 And it is used as the second least significant bit of the final result, i.e., LSB+2; Then, switches K1 to K4 are disconnected, and transmission gate T1 is opened. 12 Transmit to AD0; then close transmission gate T1 and open transmission gate T2, S 22 Transmit to AD1; then close transmission gate T2 and open transmission gate T3, S 32 Transmit to AD2; then close transmission gate T3 and open transmission gate T4, S 42 The data is transferred to AD3 to complete the shift. Cycle 4; Input X3. At this time, word line WL1 is closed and word line WL0 is open. The operation process is the same as in cycle 3, completing A3A2A1A0 and S. 42 S 32 S 22 S 12 The addition calculation is denoted as S. 43 S 33 S 23 S 13 S 03 And as the high five digits of the final result; Furthermore, based on the control of X3X2X1X0, the linear interpolation calculation result of the two rows of storage cells A0~A3 and B0~B3 is S. 43 S 33 S 23 S 13 S 03 S 02 S 01 S 00 .

7. A memory-based linear interpolation calculation circuit, characterized in that, It includes: An array of in-memory computing units, consisting of N 2 The in-memory computing units are arranged in an N×N array. Word lines WL, numbering 4N, are used to control the on / off state of the transmission transistors in each line of memory computing unit; Bit line pairs, which include 4N pairs of bit lines BL and BLB; each in-memory computing unit in each column is connected to the same bit line BLB; Switches S, numbering 4N, are used to connect the local bit lines BL_IN of each column of in-memory computing units in the in-memory computing unit array to the same bit line BL. The word line control module is used to control the opening or closing of the word lines WL connected to each in-memory computing unit in the in-memory computing array. A pre-charge circuit is used to pre-charge the bit lines BL and BLB connected to each column of in-memory computing units in the in-memory computing unit array. A line decoding circuit is used to decode the input signal and control the word line driving module according to the decoding result; The timing control module is used to provide the pulse signals required for reading, writing, and linear interpolation calculations to the in-memory computing unit array; The in-memory computing unit adopts the circuit structure of the in-memory computing circuit as described in any one of claims 1-6, and can realize the complete function of the in-memory computing circuit.

8. The in-memory linear interpolation calculation circuit according to claim 7, characterized in that, When the in-memory linear interpolation calculation circuit performs storage, read, and write operations, it closes switch S to connect BL and BL_IN. When the in-memory linear interpolation calculation circuit performs linear interpolation calculation, it disconnects switch S, making BL and BL_IN disconnected.

9. A memory-based linear interpolation calculation chip, characterized in that, It is encapsulated by the in-memory linear interpolation calculation circuit described in any one of claims 7-8.

10. The in-memory linear interpolation calculation chip according to claim 9, characterized in that, The interface of the in-memory linear interpolation calculation chip includes at least: The power interface VDD is used to connect to the power supply. The grounding interface VSS is used for grounding. The charging interface PRE is used to input control signals to adjust the charging status of each line. The input signal interface X_IN is used to input corresponding control signals to the word lines connected to each row of in-memory computing units in the in-memory computing unit array. Row strobe interface A is used to input row strobe signals to the circuit, and the row strobe signals are used to adjust the access status of each in-memory computing unit on each word line; The output signal interface S is used to read the data stored in each storage unit or to read the linear interpolation results of each shift calculation unit.

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