Reference cell module of non-volatile memory and reference cell repair method

Abstract

The application discloses a reference cell module of a non-volatile memory and a reference cell repair method. The reference cell repair method comprises: performing first reference cell repair in a wafer test stage; and performing second reference cell repair in a package test stage. The reference cell module of the non-volatile memory comprises a first subarray and a second subarray, and the reference cell repair comprises forming an address mapping between a first reference cell of the first subarray with defects and a second reference cell of the second subarray without defects and with the same threshold voltage. In the wafer test stage and the package test stage, the first reference cell with defects is repaired, so that the chip yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a reference cell module of a non-volatile memory and a reference cell repair method. BACKGROUND

[0002] A non-volatile memory is a non-volatile solid-state storage technology that can save data after power-off, and has the advantages of low power consumption and fast read-write speed, and is widely used in mobile terminal devices and data center fields. The performance requirements of non-volatile memories are different in different fields.

[0003] When the storage unit of a non-volatile memory chip performs a read operation, the current of the storage unit is usually compared with the current of a reference cell to obtain the data stored in the storage unit. For example, when the read current of the storage unit is greater than the current of the reference cell, it indicates that the stored data is 1, and when the read current of the storage unit is less than the current of the reference cell, it indicates that the stored data is 0.

[0004] In general, in the production process of a non-volatile memory chip, in order to ensure the reliability of the chip, defective chips need to be removed during testing, such as chips with defective reference cells due to production processes or stress testing. Figure 1 As shown in a wafer, all non-volatile memory dies on the wafer will undergo a series of wafer tests. The dies 1 that pass the test will be packaged into non-volatile memory chips and enter the packaging test link. Only the qualified chips can finally be applied to mobile terminals or data center fields, and those dies 2 or packaged chips that do not pass the test (for example, damaged reference cells) will be removed. The wafer yield is the ratio of the number of non-volatile memory dies that pass all tests on the wafer to the total number of non-volatile memory dies on the wafer. A wafer with a low yield not only increases the manufacturing cost, but also causes waste of die resources and pollution to the environment. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a reference cell module of a non-volatile memory and a reference cell repair method, wherein the damaged reference cells are repaired during wafer testing and packaging testing, thereby improving the yield of the chip.

[0006] According to an aspect of the present application, a reference cell repair method for a non-volatile memory is provided, comprising: performing a first reference cell repair in a wafer test stage; and performing a second reference cell repair in a package test stage, wherein the reference cell module of the non-volatile memory comprises a first sub-array and a second sub-array, and the reference cell repair comprises forming an address mapping between a first reference cell of the first sub-array having a defect and a second reference cell of the second sub-array having no defect and a same threshold voltage.

[0007] Optionally, the first sub-array comprises a plurality of the first reference cells, and the second sub-array comprises a plurality of the second reference cells, and the number of the first reference cells is the same as that of the second reference cells.

[0008] Optionally, the first reference cell repair comprises: adjusting the threshold voltage of the first reference cell to a design value; performing an aging test on the wafer; judging whether the first reference cell has a defect according to whether the threshold voltage of the first reference cell changes; adjusting the threshold voltage of the second reference cell to the design value when the first reference cell has a defect; and forming an address mapping between the second reference cell and the first reference cell having a defect and recording mapping information.

[0009] Optionally, the aging test comprises placing the wafer in a 250℃ environment for 24 hours.

[0010] Optionally, the second reference cell repair comprises: judging whether the first reference cell has a defect according to whether the threshold voltage of the first reference cell changes; adjusting the threshold voltage of the second reference cell to the design value when the first reference cell has a defect; and forming an address mapping between the second reference cell and the first reference cell having a defect and recording mapping information.

[0011] Optionally, the first reference cell repair comprises: adjusting the threshold voltage of the first reference cell to a design value; adjusting the threshold voltage of the second reference cell to the design value; performing an aging test on the wafer; judging whether the first reference cell has a defect according to whether the threshold voltage of the first reference cell changes; judging whether the second reference cell has a defect according to whether the threshold voltage of the second reference cell changes when the first reference cell has a defect; and forming an address mapping between the second reference cell and the first reference cell having a defect and recording mapping information when the second reference cell has no defect.

[0012] Optionally, the aging test comprises placing the wafer in a 250℃ environment for 24 hours.

[0013] Optionally, the second reference cell repair comprises: judging whether the first reference cell repair exists according to the mapping information; judging whether the first reference cell has a defect according to whether the threshold voltage of the first reference cell changes when the first reference cell repair does not exist; judging whether the second reference cell has a defect according to whether the threshold voltage of the second reference cell changes when the first reference cell has a defect; and forming an address mapping between the second reference cell and the first reference cell having a defect and recording mapping information when the second reference cell does not have a defect.

[0014] Optionally, each of the first reference cells has the second reference cell with the same threshold voltage.

[0015] According to still another aspect of the present application, a reference cell module of a non-volatile memory is provided, comprising: a first sub-array comprising a plurality of first reference cells; a second sub-array comprising a plurality of second reference cells; wherein a reference current generation module selects the first reference cell to generate a reference current according to a read condition, and selects the corresponding second reference cell to generate the reference current when the first reference cell has a defect.

[0016] Optionally, the reference cell further comprises: a repair information storage module for storing address mapping information of the first reference cell and the second reference cell; and a repair information reading module connected to the repair information storage module, for providing the address mapping information to the reference current generation module.

[0017] According to the reference cell repair method of the embodiments of the present application, whether the reference cell is damaged is judged by detecting the threshold voltage set for the first reference cell in the wafer testing stage and the packaging testing stage, and an address mapping is formed between the first reference cell having a defect and the second reference cell having the same threshold voltage and not having a defect according to the detection result, so as to reduce the damage of the reference cell caused by the production or testing process, and to improve the chip yield. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A wafer schematic diagram is shown;

[0020] Figure 2 A schematic block diagram of a non-volatile memory system in the prior art is shown;

[0021] Figure 3A schematic block diagram showing a nonvolatile memory system according to an embodiment of the present application is shown.

[0022] Figure 4 A flowchart showing a reference cell repair method according to an embodiment of the present application is shown.

[0023] Figure 5 A detailed flowchart showing a reference cell repair method according to a first embodiment of the present application is shown.

[0024] Figure 6 A detailed flowchart showing a reference cell repair method according to a second embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] The present application will be described in more detail by referring to the attached drawings. In each of the drawings, like elements are designated by like reference numerals. Each part in the drawings is not drawn to scale for the sake of clarity. Also, certain parts that are well-known can not be shown.

[0026] The present application will be described in more detail by referring to the attached drawings. In each of the drawings, like elements are designated by like reference numerals. Each part in the drawings is not drawn to scale for the sake of clarity. Also, certain parts that are well-known can not be shown.

[0027] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to". In this description, the terms "first", "second" and the like, do not denote any ordinal, quantity or importance, but are used to distinguish a certain element from another, unless otherwise indicated. Also, the use herein of "a" or "an" to describe a certain feature, material or component is not intended to be construed as excluding there being a plurality of such features, materials or components, unless otherwise indicated.

[0028] The specific embodiments of the present application will now be described in further detail by reference to the drawings and examples.

[0029] Figure 2 A schematic block diagram showing a nonvolatile memory system 100 in the prior art is shown.

[0030] The nonvolatile memory system 100 includes a memory chip 110 of a nonvolatile memory and a memory controller 120. The memory controller 120 transfers instructions and data between a host and the memory chip 110.

[0031] The memory chip 110 includes a memory cell array 111 and a reference cell array 112. The memory cell array 111 includes, for example, a plurality of memory cells of a NAND flash memory structure or a NOR flash memory structure. The reference cell array 112 includes, for example, a plurality of reference cells of a NOR flash memory structure. In the NOR flash memory structure, a transistor can be independently addressed compared to the NAND flash memory structure. Therefore, in the reference cell array 112, a single reference cell can be selected, a threshold voltage of the single reference cell can be set, and a reference current generated by the single reference cell can be obtained.

[0032] The memory chip 110 further includes a reference current generation module 113 and a read circuit 114. The read circuit 114 includes a plurality of sensing modules 114-1 to 114-m. The reference current generation module 113 outputs a selection signal to the reference cell array 112 according to data reading of different read conditions (e.g., a pre-programming check, a program check, an erase check, a weak program check), selects a reference cell of a corresponding threshold voltage to apply a voltage to generate a corresponding reference current Iref. The sensing modules compare a detection current Isen of a memory cell in the memory cell array 111 with the reference current Iref. The read circuit 114 determines a charge state in the memory cell according to a comparison result of the detection current Isen and the reference current Iref, thereby reading data stored in the memory cell under a corresponding condition.

[0033] The memory chip 110 further includes a control module 117, a column decoder 115, and a row decoder 116. The control module 117 provides an address interface between an address of a host or a memory controller and a hardware address in the memory cell array 111. The control module 117 is connected to the column decoder 115 and the row decoder 116, the column decoder 115 addresses a memory cell via a bit line, and the row decoder 116 addresses the memory cell via a word line. The control module 117 further provides a word line voltage and a bit line voltage in a data operation, and is connected to the read circuit 114 to obtain data read from the memory cell.

[0034] Figure 3 A schematic block diagram of a non-volatile memory system 200 according to an embodiment of the present application is shown.

[0035] The non-volatile memory system 200 includes a memory chip 210 of a non-volatile memory and a memory controller 220. The memory controller 220 transmits instructions and data between a host and the memory chip 210.

[0036] The memory chip 210 includes a memory cell array 211, a reference cell module 212, a reference current generation module 213, and a read circuit 214. The memory cell array 211 includes, for example, a plurality of memory cells of a NAND flash memory structure or a NOR flash memory structure.

[0037] The reference cell module 20 includes a first subarray 21 and a second subarray 22. The first subarray 21 includes a plurality of first reference cells of a NOR flash structure, for example, and the second subarray 22 includes a plurality of second reference cells of a NOR flash structure, for example. Compared with a NAND flash structure, the transistors in the NOR flash structure can be independently addressed. Therefore, a single first reference cell or a corresponding second reference cell can be selected, a single threshold voltage can be set, and a single first reference cell or second reference cell can be used to obtain a reference current. Further, since there can be a plurality of first reference cells with different threshold voltages according to a read condition, the same number of second reference cells as the first reference cells is needed to ensure that all defective first reference cells can be repaired.

[0038] The read circuit 214 includes a plurality of sensing modules 214-1 to 214-m. The reference current generation module 213 outputs a selection signal to the reference cell module 20 according to data reading (e.g., a pre-programmed check, a program check, an erase check, and a weak program check) of different read conditions, selects a first reference cell with a corresponding threshold to apply a voltage to generate a corresponding reference current Iref. And in the case that the first reference cell is defective, a corresponding second reference cell is selected to generate the reference current Iref. The sensing module compares the detection current Isen of the storage cell in the storage cell array 211 with the reference current Iref. The read circuit 214 determines the charge state in the storage cell according to the comparison result of the detection current Isen and the reference current Iref, thereby reading the data stored in the storage cell under the corresponding condition.

[0039] The storage chip 210 further includes a control module 217, a column decoder 215, and a row decoder 216, which have substantially the same structure and function as the control module 117, the column decoder 115, and the row decoder 116 in the prior art storage chip 110, and detailed descriptions thereof are omitted here.

[0040] Further, the reference cell module 20 further includes a repair information storage module 23 and a repair information read module 24. The repair information storage module 23 is used to store address mapping information. When any first reference cell in the first subarray 21 is detected to be defective at the wafer test stage or the packaged chip test stage, it is address-mapped with a corresponding second reference cell in the second subarray 22 that is not defective, and the address mapping information is stored in the repair information storage module 23, wherein the first reference cell and the corresponding second reference cell have the same threshold voltage;

[0041] The repair information read module 24 reads out the address mapping information in the repair information storage module 23 when the chip is powered on, and outputs the parsed information to the reference current generation module 213;

[0042] The reference current generating module receives the address mapping information parsed by the repair information reading module 24, and selects a first reference cell in the first sub-array 21 or a second reference cell in the second sub-array 22 to generate a reference current. Specifically, according to the selection signal output by the reference current generating module 213, there is a first reference cell corresponding to the threshold voltage, if the selected first reference cell does not exist address mapping information, the first reference cell is provided to the reference current generating module 213; if the first reference cell exists address mapping information, the corresponding second reference cell is selected to provide to the reference current generating module 213.

[0043] Figure 4 A flow chart of the reference cell repair method according to the present application is shown, comprising

[0044] S1: wafer manufacturing;

[0045] S2: first repair of reference cells in the wafer test stage;

[0046] In this step, the die is tested to determine whether the first reference cell in the first sub-array 21 has a defect, if the first reference cell has a defect, an address mapping is formed between the defective first reference cell and the second reference cell with the same threshold voltage and without defects, and the address mapping information is recorded.

[0047] S2: chip packaging;

[0048] In this step, the die without the first reference cell defect and the die after the first repair of the reference cell are packaged into a memory chip.

[0049] S3: second repair of reference cells in the packaging test stage.

[0050] In this step, the packaged memory chip is tested to determine whether the packaging process has caused damage to the first reference cell, if the first reference cell has a defect, an address mapping is formed between the defective first reference cell and the second reference cell with the same threshold voltage and without defects, and the address mapping information is recorded.

[0051] Figure 5 and Figure 6 A detailed flow chart of different embodiments of the reference cell repair method according to the present application is shown, which will be described below in combination with Figure 6 and Figure 5 The first reference cell repair method is described in detail.

[0052] Figure 5 A detailed flow chart of the reference cell repair method according to the first embodiment of the present application is shown. In this embodiment, steps S101 to S105 correspond to Figure 5The step S2 shown is to repair the reference cells for the first time in the wafer test stage. The steps S107 to S109 correspond to Figure 5 The step S4 shown is to repair the reference cells for the second time in the package test stage. The specific steps include:

[0053] S101: Adjust the first reference cells to the design values;

[0054] In this step, the design of the die is performed, specifically, the design values of the first reference cells in the first sub-array 21 are adjusted, in this embodiment, the design values are, for example, the threshold voltages of the first reference cells. Since different threshold voltage first reference cells need to be selected to apply voltages to generate corresponding reference currents under different reading conditions (for example, pre-program check, program check, erase check, weak program check), in the first sub-array 21, several groups of first reference cells with different threshold voltages may need to be designed at the same time.

[0055] S102: Aging test:

[0056] In this step, the designed wafer and die are placed in a high temperature environment for a certain period of time, for example, the die is placed in a high temperature environment of 250°C for 24 hours to accelerate the aging of the die.

[0057] S103: Measure whether the design values of the first reference cells change;

[0058] In this step, the aged die is tested to measure whether the threshold voltages of the first reference cells change. If none of the first reference cells changes, step S106 and subsequent steps are performed. If there is at least one first reference cell whose threshold voltage changes, steps S104 and S105 are performed before step S106.

[0059] S104: Adjust the second reference cells to the design values;

[0060] In this step, the threshold voltages of the second reference cells in the second sub-array 22 are adjusted to the design values of the defective first reference cells. Further, when there are multiple defective first reference cells, a second reference cell with the same threshold voltage as each defective first reference cell is set.

[0061] S105: Address mapping;

[0062] In this step, address mapping is formed between the defective first reference cells with the same threshold voltage and the second reference cells without defects, and the mapping information is stored in the repair information storage unit 23. The number of second reference cells should be consistent with the number of defective first reference cells to ensure that each defective first reference cell is repaired.

[0063] S106: chip packaging;

[0064] In this step, the dies whose first reference cell threshold voltage does not change and the dies whose first reference cell repair is completed are packaged to obtain a packaged chip.

[0065] S107: measuring whether the first reference cell design value changes;

[0066] In this step, the packaged chip is tested to measure whether the threshold voltage of each first reference cell changes. If the threshold voltage of each first reference cell does not change, the test is ended and the packaged chip is qualified. If the threshold voltage of at least one first reference cell changes, steps S108 and S109 are performed.

[0067] S108: adjusting the second reference cell to the design value;

[0068] In this step, a second reference cell is selected in the second subarray 22 and its threshold voltage is adjusted to the design value of the defective first reference cell. Further, when there are multiple defective first reference cells, a second reference cell having the same threshold voltage as each defective first reference cell is set.

[0069] S109: address mapping

[0070] In this step, address mapping is formed between the defective first reference cell and the second reference cell having the same threshold voltage and the mapping information is stored in the repair information storage unit 23. The number of second reference cells should be consistent with the number of defective first reference cells to ensure that each defective first reference cell is repaired.

[0071] Figure 5 The embodiment shown is to set and replace the second reference cell when it is found that the first reference cell does not meet the requirements. Therefore, the second reference cell does not need to be fixed to a specific first reference cell at the design time, which improves the utilization rate of the second reference cell. At the same time, since the second reference cell is set when replacement is needed, the test time is reduced.

[0072] Figure 6 A detailed flowchart of the first reference cell repair method according to the second embodiment of the present application is shown. In this embodiment, steps S201 to S206 correspond to Figure 5 the step S2 shown, i.e., the first repair of the reference cell in the wafer test stage; and steps S208 to S211 correspond to Figure 5 the step S4 shown, i.e., the second repair of the reference cell in the packaging test stage. The specific steps include:

[0073] S201: adjusting the first reference cell to a design value;

[0074] In this step, the die is designed, specifically, the design value of the first reference cell in the first subarray 21 is designed, in this embodiment, the design value is taken as the threshold voltage. Since different threshold voltage first reference cells need to be selected to apply voltage to generate corresponding reference current under different reading conditions (for example, pre-program check, program check, erase check, weak program check), in the first subarray 21, several groups of first reference cells with different threshold voltages may need to be designed at the same time.

[0075] S202: adjusting the second reference cell to a design value;

[0076] In this step, the die is designed, specifically, the design value of the second reference cell in the second subarray 22 is designed, in this embodiment, the design value is taken as the threshold voltage. So that each threshold voltage has a corresponding first reference cell in the first subarray 21 and a second reference cell in the second subarray 22.

[0077] S203: aging test:

[0078] In this step, the designed wafer and die are placed in a high temperature environment for a certain period of time, for example, the die is placed in a 250℃ high temperature environment for 24 hours to accelerate the aging of the die.

[0079] S204: measuring whether the design value of the first reference cell changes;

[0080] In this step, the aged die is tested to measure whether the threshold voltage of each first reference cell changes, if none of the first reference cells changes, step S207 and subsequent steps are executed, if there is at least one first reference cell whose threshold voltage changes, steps S205 and S206 are executed before step S207.

[0081] S205: measuring whether the design value of the second reference cell changes;

[0082] In this step, the aged die is tested to measure whether the threshold voltage of the second reference cell corresponding to the defective first reference cell changes, if none of the second reference cells corresponding to the defective first reference cells changes, step S206 and subsequent steps are executed, if there is at least one second reference cell whose threshold voltage changes, the test is ended and the package is unqualified.

[0083] S206: address mapping;

[0084] In this step, address mapping is formed between the first reference cell with the same threshold voltage as the defective one and the second reference cell without defect, and the mapping information is stored in the repair information storage unit 23.

[0085] S207: Chip packaging

[0086] In this step, the dies with no change in the first reference cell design value and the dies with completed first reference cell replacement are packaged to obtain packaged chips.

[0087] S208: Whether replacement occurs

[0088] In this step, it is determined according to the address mapping information in the repair information storage unit 23 whether replacement of the first reference cell occurs in the die test stage. If replacement occurs, step S210 and subsequent steps are performed. If no replacement occurs, step S209 is performed before step S210.

[0089] S209: Whether the first reference cell design value changes

[0090] In this step, the packaged chips are tested to determine whether the threshold voltage of the first reference cell in the packaged chips without replacement in the die test stage changes. If the threshold voltage of each first reference cell does not change, the test is ended and the packaged chip is a qualified chip. If the design value of at least one first reference cell changes, step S210 and subsequent steps are performed.

[0091] S210: Whether the second reference cell design value changes

[0092] In this step, the second reference cell that has undergone replacement is tested to determine whether the design value changes. If the design value of at least one second reference cell changes, the test is ended and the packaged chip is unqualified. If the design value of each defective first reference cell corresponding second reference cell does not change, step S211 is performed.

[0093] S211: Address mapping

[0094] Address mapping is formed between the first reference cell with the same threshold voltage as the defective one and the second reference cell without defect, and the mapping information is stored in the repair information storage unit 23.

[0095] In the first reference unit repair method as shown in the figure, at the die stage, the first reference unit and the second reference unit both need to be set and tested at the die stage and the package stage, to determine whether the design values of the first reference unit and the second reference unit change, if the design value of the first reference unit does not change, the chip passes the test; if only the design value of the first reference unit changes, the defective first reference unit is replaced with the corresponding second reference unit; if the design values of the first reference unit and the corresponding second reference unit both change, the chip fails the test, thereby ensuring that each chip that passes the test is in compliance.

[0096] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details, nor limit the application to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above descriptions. The present description is chosen and described in order to best explain the principles of the application and practical application, so that those skilled in the art can well use the application and make modifications on the basis of the application. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for repairing reference cells in a non-volatile memory, comprising: The first reference cell repair is performed during the wafer testing phase; as well as A second reference cell repair is performed during the packaging and testing phase. The reference cell module of the non-volatile memory includes a first sub-array and a second sub-array. The reference unit repair includes: When a defect is determined in the first reference cell of the first subarray, the threshold voltage of the second reference cell of the second subarray is adjusted to the design value; and An address mapping is formed between the defective first reference unit and the adjusted second reference unit.

2. The reference unit repair method according to claim 1, wherein, The first subarray includes a plurality of first reference cells, and the second subarray includes a plurality of second reference cells, wherein the number of first reference cells and second reference cells is the same.

3. The reference unit repair method according to claim 1, wherein, The first reference unit repair also includes: Adjust the threshold voltage of the first reference unit to the design value; Aging tests are performed on the wafers; and The presence of a defect in the first reference unit is determined based on whether the threshold voltage of the first reference unit changes.

4. The reference unit repair method according to claim 3, wherein, The aging test includes placing the wafer at 250°C for 24 hours.

5. The reference unit repair method according to claim 4, wherein, The second reference unit repair also includes: The presence of a defect in the first reference unit is determined based on whether the threshold voltage of the first reference unit changes.

6. The reference unit repair method according to claim 1, wherein, The first reference unit repair also includes: Adjust the threshold voltage of the first reference unit to the design value; Adjust the threshold voltage of the second reference unit to the design value; Aging tests are performed on the wafers; and The presence of a defect in the first reference unit is determined based on whether the threshold voltage of the first reference unit changes.

7. The reference unit repair method according to claim 6, wherein, The aging test includes placing the wafer at 250°C for 24 hours.

8. The reference unit repair method according to claim 6, wherein, The second reference unit repair also includes: Determine whether the first reference unit repair exists based on the mapping information; When the first reference unit is not repaired, the presence of a defect in the first reference unit is determined based on whether the threshold voltage of the first reference unit changes. When the first reference unit has a defect, the presence of a defect in the second reference unit is determined based on whether the threshold voltage of the second reference unit changes; and When the second reference unit is free of defects, an address mapping is formed between the second reference unit and the first reference unit with defects, and the mapping information is recorded.

9. The reference unit repair method according to any one of claims 6 to 8, wherein, Each of the first reference cells has a second reference cell with the same threshold voltage.

10. A reference cell module for a non-volatile memory, comprising: A first subarray, the first subarray comprising a plurality of first reference elements; The second subarray includes a plurality of second reference elements; Specifically, the reference current generation module selects the first reference unit to generate the reference current based on the reading conditions, and selects the corresponding second reference unit to generate the reference current when the first reference unit has a defect. The reference unit module obtains the address mapping between the defective first reference unit and its corresponding second reference unit according to the reference unit repair method as described in any one of claims 1 to 9.

11. The reference unit module according to claim 10, wherein, The reference unit further includes: Repair information storage module, used to store address mapping information of the first reference unit and the second reference unit; The repair information reading module is connected to the repair information storage module and provides the address mapping information to the reference current generating module.

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