Method for improving field effect transistor load

Abstract

The present invention provides a method for improving the load of a field effect transistor. A substrate is provided, and shallow trench isolation is formed on the substrate to define an active region. An N-well and a P-well are formed in the active region on the substrate by ion implantation. A gate stack is formed on the substrate, and then an etching protection layer is formed on the gate stack; the etching protection layer and the gate stack thereunder are etched to form gate structures respectively located on the N-well and the P-well; a first hard mask layer covering the gate structures is formed on the substrate, and then the first hard mask layer is etched back to form a first sidewall structure; a protection layer covering the first sidewall structure and the gate structures is formed, and then the NMOS region is covered by a lithography process, the protection layer in the PMOS region is removed, grooves are formed in the N-well regions on both sides of the gate structures, and then the remaining protection layer in the NMOS region is removed. The present invention avoids the consumption of the gate oxide layer caused in the subsequent etching process by growing an etching protection layer in advance, thereby improving the effect of the load between the NFET and the PFET.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the load of a field effect transistor. Background Art

[0002] Currently, before the photoresist etch-back (PREB) of all high-K metal gates at the 28-nanometer and 22-nanometer technology nodes, a load difference of approximately 170 A is found between N / PFETs (N-type field effect transistors and P-type field effect transistors). This load originates from the fact that during the epitaxial layer trench etching, the PFET region has no pattern mask, and a part of the gate top oxide will be consumed during the etching process, resulting in a load. And the load further increases after the etching of the second spacer structure, bringing greater challenges to the subsequent etching and planarization.

[0003] To solve the above problems, a new method for improving the load of a field effect transistor needs to be proposed. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving the load of a field effect transistor, which is used to solve the problems in the prior art that during the epitaxial layer trench etching, the PFET region has no pattern mask, and a part of the gate top oxide will be consumed during the etching process, resulting in a load; and the load further increases after the etching of the second spacer structure, bringing greater challenges to the subsequent etching and planarization.

[0005] To achieve the above purpose and other related purposes, the present invention provides a method for improving the load of a field effect transistor, including:

[0006] Step 1: Provide a substrate, a shallow trench isolation is formed on the substrate to define an active region, an N-well and a P-well are formed in the active region on the substrate by ion implantation, a gate stack is formed on the substrate, and then an etching protection layer is formed on the gate stack;

[0007] Step 2: Etch the etching protection layer and the gate stack below it to form gate structures respectively located on the N-well and the P-well; form a first hard mask layer covering the gate structures on the substrate, and then etch-back the first hard mask layer to form a first spacer structure;

[0008] Step 3: Form a protection layer covering the first spacer structure and the gate structures, then use a lithography process to cover the NMOS region, remove the protection layer in the PMOS region, form grooves in the N-well regions on both sides of the gate structures, and then remove the remaining protection layer in the NMOS region;

[0009] Step 4: Form an epitaxial layer to fill the groove, and then form second and third hard mask layers on the substrate to cover the epitaxial layer, the gate structure, and the first sidewall structure. Then, perform a re-etch on the second and third hard mask layers to form a second sidewall structure;

[0010] Step 5: Form a first metal layer on the substrate to cover the epitaxial layer, the gate structure, and the second sidewall structure, and a second metal layer on the first metal layer. Then, use an annealing process to form a metal silicide on the active region in the PMOS region;

[0011] Step 6: Remove the first and second metal layers and the etch protection layer.

[0012] Preferably, the substrate in Step 1 includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0013] Preferably, the material of the etch protection layer in Step 1 is titanium nitride.

[0014] Preferably, the gate stack in Step 2 is composed of a titanium nitride layer, a hafnium oxide layer, a first NF DARC layer, an amorphous silicon layer, a gate silicon nitride layer, and a gate oxide layer stacked in sequence from bottom to top.

[0015] Preferably, the method for etching the etch protection layer and the gate stack thereunder to form gate structures on the N-well and the P-well respectively in Step 2 is as follows: form an APF layer, a second NF DARC layer, and a capping oxide layer stacked from bottom to top on the etch protection layer. Then, use a lithography process to define the etch region. Then, etch the APF layer, the second NF DARC layer, the capping oxide layer, and the gate stack thereunder to form the gate structures.

[0016] Preferably, the material of the first hard mask layer in Step 2 is silicon nitride.

[0017] Preferably, the material of the protection layer in Step 3 is silicon dioxide or silicon nitride.

[0018] Preferably, the epitaxial layer in Step 4 is a germanium-silicon epitaxial layer.

[0019] Preferably, the materials of the second and third hard mask layers in Step 4 are both silicon nitride.

[0020] Preferably, the material of the first metal layer in Step 5 is NiPt.

[0021] Preferably, the material of the second metal layer in Step 5 is titanium nitride.

[0022] As described above, the method for improving the load of a field effect transistor according to the present invention has the following beneficial effects:

[0023] The present invention avoids the consumption of the gate oxide layer during the subsequent etching process by growing a relatively high-selectivity etching protection layer in advance, thereby improving the load effect between NFET and PFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It shows a schematic process flow diagram of the present invention;

[0025] Figure 2 It shows a schematic diagram of the substrate of the present invention and the semiconductor structure thereon;

[0026] Figure 3 It shows a schematic diagram of the gate structures formed on the N-well and P-well respectively according to the present invention;

[0027] Figure 4 It shows a schematic diagram of the formation of the first sidewall structure according to the present invention;

[0028] Figure 5 It shows a schematic diagram of the formation of the epitaxial layer trench according to the present invention;

[0029] Figure 6 It shows a schematic diagram of the removal of the photoresist layer and the protection layer according to the present invention;

[0030] Figure 7 It shows a schematic diagram of the formation of the second and third hard mask layers according to the present invention;

[0031] Figure 8 It shows a schematic diagram of the formation of the second sidewall structure according to the present invention;

[0032] Figure 9 It shows a schematic diagram of the formation of the metal silicide according to the present invention;

[0033] Figure 10 It shows a schematic diagram of the removal of the metal layer and the etching protection layer according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0034] The following specific examples illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please refer to Figure 1 , the present invention provides a method for improving the load of field effect transistors, including:

[0036] Step 1, please refer to Figure 2, a substrate 101 is provided. A shallow trench isolation 102 is formed on the substrate 101 to define active regions. N wells and P wells are formed in the active regions on the substrate 101 by ion implantation. A gate stack is formed on the substrate 101, and then an etch protection layer 109 is formed on the gate stack;

[0037] In an embodiment of the present invention, the substrate 101 in step one includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer that serves as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material can be doped or undoped. Other substrates that can be used include multi-layer substrates, gradient substrates, or mixed-orientation substrates.

[0038] In an embodiment of the present invention, the material of the etch protection layer 109 in step one is titanium nitride. That is, by using the high selectivity of SiN relative to TiN during the etching process, the gate oxide layer 108 is protected during the subsequent etching of the epitaxial layer 122 and the sidewall etching, preventing a loading effect from occurring between the NFET (N-type field effect transistor) and the PFET (P-type field effect transistor) due to over-etching effects. It should be noted that the material of the etch protection layer 109 here can also be other materials known to those skilled in the art that can protect the gate oxide layer 108.

[0039] Step two, please refer to Figure 3 , etch the etch protection layer 109 and the gate stack below it to form gate structures respectively located on the N well and the P well; form a first hard mask layer covering the gate structures on the substrate 101, and then back-etch the first hard mask layer to form a first sidewall structure 113, forming a structure as shown in Figure 4 , and the method of back-etching is dry etching;

[0040] In an embodiment of the present invention, the gate stack in step two is composed of a titanium nitride layer 103, a hafnium oxide layer 104, a first NF DARC (nitrogen-free dielectric anti-reflection coating) layer 105, an amorphous silicon layer 106, a gate silicon nitride layer 107, and a gate oxide layer 108 stacked in sequence from bottom to top.

[0041] In an embodiment of the present invention, please continue to refer to Figure 2, in Step 2, the method of etching the etch protection layer 109 and the gate stack below it to form gate structures respectively on the N-well and P-well is as follows: form an APF (Advanced Thin Film) layer 110, a second NF DARC layer 111, and a capping oxide layer 112 stacked from bottom to top on the etch protection layer 109. Then, use photolithography to define the etch area. After that, etch the APF layer 110, the second NF DARC layer 111, the capping oxide layer 112, and the gate stack below them to form the gate structures.

[0042] In an embodiment of the present invention, the material of the first hard mask layer in Step 2 is silicon nitride.

[0043] Step 3, please refer to Figure 5 , form a protection layer 114 covering the first sidewall structure 113 and the gate structure. Then, use photolithography, that is, use a photoresist layer 115 to cover the NMOS region, remove the protection layer 114 in the PMOS region, form grooves in the N-well regions on both sides of the gate structure. After that, remove the remaining protection layer 114 in the NMOS region to form a structure as Figure 6 shown;

[0044] In an embodiment of the present invention, the material of the protection layer 114 in Step 3 is silicon dioxide or silicon nitride.

[0045] Step 4, form an epitaxial layer 122 filling the grooves. Then, form second and third hard mask layers (116, 117) covering the epitaxial layer 122, the gate structure, and the first sidewall structure 113 on the substrate 101. The thickness of the third hard mask layer 117 is greater than that of the second hard mask layer 116 to form a structure as Figure 7 shown. After that, etch back the second and third hard mask layers (116, 117) to form second sidewall structures (118, 119), where the second sidewall structures are composed of a second sidewall 118 and a second sidewall 119. The method of etch back is dry etching to form a structure as Figure 8 shown;

[0046] In an embodiment of the present invention, the epitaxial layer 122 in Step 4 is a germanium-silicon epitaxial layer 122.

[0047] In an embodiment of the present invention, the materials of the second and third hard mask layers (116, 117) in Step 4 are both silicon nitride.

[0048] Step 5, form a first metal layer 120 covering the epitaxial layer 122, the gate structure, and the second sidewall structures (118, 119) on the substrate 101 and a second metal layer 121 on the first metal layer 120. Then, use an annealing process to form metal silicide on the active region in the PMOS region to form a structure as Figure 9 shown;

[0049] In an embodiment of the present invention, the material of the first metal layer 120 in step five is NiPt, that is, NiSi metal silicide is formed in the subsequent annealing process.

[0050] In an embodiment of the present invention, the material of the second metal layer 121 in step five is titanium nitride.

[0051] Step six, remove the first and second metal layers and the etch protection layer 109 to form a structure as shown in Figure 10 After the NiSi metal silicide is formed, the first and second metal layers and the etch protection layer 109 can be removed simultaneously through an etching process.

[0052] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] In summary, the present invention avoids the consumption of the gate oxide layer during the subsequent etching process by pre-growing an etch protection layer with a relatively high selectivity, thereby improving the load effect between NFET and PFET. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0054] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the load of a field effect transistor, characterized in that, At least including: Step 1: Provide a substrate, a shallow trench isolation is formed on the substrate to define an active region, an N-well and a P-well are formed in the active region on the substrate by ion implantation, a gate stack is formed on the substrate, and then an etching protection layer is formed on the gate stack; Step 2: Etch the etching protection layer and the gate stack thereunder to form gate structures respectively located on the N-well and the P-well; form a first hard mask layer covering the gate structures on the substrate, and then back-etch the first hard mask layer to form a first sidewall structure; Step 3: Form a protection layer covering the first sidewall structure and the gate structures, then use a photolithography process to cover the NMOS region, remove the protection layer in the PMOS region, form grooves in the N-well regions on both sides of the gate structures, and then remove the remaining protection layer in the NMOS region; Step 4: Form an epitaxial layer filling the grooves, then form second and third hard mask layers covering the epitaxial layer, the gate structures and the first sidewall structure on the substrate, and then back-etch the second and third hard mask layers to form a second sidewall structure; Step 5: Form a first metal layer covering the epitaxial layer, the gate structures and the second sidewall structure and a second metal layer on the first metal layer on the substrate, and then use an annealing process to form a metal silicide on the active region in the PMOS region; Step 6: Remove the first and second metal layers and the etching protection layer.

2. The method for improving the field effect transistor load according to claim 1, wherein: The substrate in Step 1 includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method for improving the field effect transistor load according to claim 1, wherein: The material of the etching protection layer in Step 1 is titanium nitride.

4. The method for improving the field effect transistor load according to claim 1, wherein: The gate stack in Step 2 is composed of a titanium nitride layer, a hafnium oxide layer, a first NF DARC layer, an amorphous silicon layer, a gate silicon nitride layer and a gate oxide layer stacked in sequence from bottom to top.

5. The method for improving the field effect transistor load according to claim 1, wherein: The method of etching the etching protection layer and the gate stack thereunder to form gate structures respectively located on the N-well and the P-well in Step 2 is: form an APF layer, a second NF DARC layer and a cap oxide layer stacked in sequence from bottom to top on the etching protection layer, then use a photolithography process to define an etching region, and then etch the APF layer, the second NF DARC layer, the cap oxide layer and the gate stack thereunder to form the gate structures.

6. The method for improving the field effect transistor load according to claim 1, wherein: The material of the first hard mask layer in Step 2 is silicon nitride.

7. The method for improving the field effect transistor load according to claim 1, wherein: The material of the protection layer in Step 3 is silicon dioxide or silicon nitride.

8. The method for improving the field effect transistor load according to claim 1, wherein: The epitaxial layer in Step 4 is a germanium-silicon epitaxial layer.

9. The method for improving the field effect transistor load according to claim 1, wherein: The materials of the second and third hard mask layers in Step 4 are both silicon nitride.

10. The method for improving the field effect transistor load according to claim 1, wherein: The material of the first metal layer in Step 5 is NiPt.

11. The method for improving the field effect transistor load according to claim 1, wherein: The material of the second metal layer in Step 5 is titanium nitride.

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