Parasitic inductance suppression structure and method, power circuit module

Abstract

This invention provides a structure for suppressing parasitic inductance, a power circuit module, and a method for suppressing parasitic inductance. The suppression structure includes: a first suppression sheet made of conductive material covering a first surface of the power circuit; a second suppression sheet made of conductive material covering a second surface of the power circuit, wherein the first surface and the second surface are located in opposite directions of the power circuit; and at least one decoupling capacitor, with a first end connected to the first suppression sheet and a second end connected to the second suppression sheet, for absorbing induced current reversed from the operating current of the power circuit from the first suppression sheet and the second suppression sheet during operation of the power circuit.

Description

Technical Field

[0001] This invention belongs to the field of power device packaging technology, and particularly relates to a parasitic inductance suppression structure, a power circuit module, and a method for suppressing parasitic inductance. Background Technology

[0002] Reducing parasitic parameters is one of the core issues in power device packaging. Currently, the main approach to reducing parasitic parameters is to decrease the overall trace length of the package. For example, some existing technologies increase system integration by grouping multiple chips into a single package, thereby reducing the trace length between these three chips and lowering their inter-chip resistance. Another example is the use of leadless packaging to reduce unnecessary wiring, thus improving the length of external pins and their corresponding inductance. Yet another example is the use of three-dimensional stacked structures to reduce the package size of power devices, thereby reducing parasitic inductance.

[0003] However, existing technologies that reduce parasitic parameters by reducing the overall trace length of the package generally have the following drawbacks: (1) the process is complex and will increase the cost; (2) under the limitations of existing processes, the reduction of bus length is limited; (3) the parasitic parameters of a single component will only really affect the circuit parameters after forming a loop and generating loop inductance, so it is difficult to predict the circuit characteristics of the parasitic parameters in the actual loop and it is also difficult to compensate for the circuit parameters in advance.

[0004] In order to overcome the above-mentioned defects in the existing technology, there is an urgent need in the field for a power device packaging technology to reduce the parasitic inductance of power modules or even the entire power circuit in a low cost and with high efficiency. Summary of the Invention

[0005] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] In order to overcome the above-mentioned defects of the prior art, the present invention provides a parasitic inductance suppression structure, a power circuit module, and a method for suppressing parasitic inductance, which can reduce the parasitic inductance of the power module or even the entire power circuit in a low cost and with high efficiency.

[0007] Specifically, the parasitic inductance suppression structure provided according to the first aspect of the present invention includes: a first suppression sheet made of conductive material covering a first surface of a power circuit; a second suppression sheet made of conductive material covering a second surface of the power circuit, wherein the first surface and the second surface are located in opposite directions of the power circuit; and at least one decoupling capacitor having a first end connected to the first suppression sheet and a second end connected to the second suppression sheet, for absorbing induced current opposite to the operating current of the power circuit from the first suppression sheet and the second suppression sheet during operation of the power circuit.

[0008] Furthermore, in some embodiments of the present invention, the suppression structure includes only one decoupling capacitor, wherein the two ends of the decoupling capacitor are respectively connected to the first end of the first suppression sheet and the first end of the second suppression sheet, and the second ends of the first suppression sheet and the second suppression sheet remain separated. Alternatively, the suppression structure includes multiple decoupling capacitors, wherein the two ends of the first decoupling capacitor are respectively connected to the first end of the first suppression sheet and the first end of the second suppression sheet, and the two ends of the second decoupling capacitor are respectively connected to the second end of the first suppression sheet and the second suppression sheet.

[0009] Further, in some embodiments of the present invention, the power circuit includes at least one power tube, wherein the power tube is arranged laterally, the first suppression sheet covers the upper surface of the power circuit, and the second suppression sheet covers the lower surface of the power circuit. Alternatively, the power circuit includes at least one power tube, wherein the power tube is arranged longitudinally, the first suppression sheet covers the front surface of the power circuit, and the second suppression sheet covers the rear surface of the power circuit. Alternatively, the power circuit includes at least one power tube, wherein the power tube is arranged longitudinally, the first suppression sheet covers the left surface of the power circuit, and the second suppression sheet covers the right surface of the power circuit.

[0010] Furthermore, in some embodiments of the present invention, the second suppression sheet covering the lower surface of the power circuit is selected from a circuit board with a grounded copper layer, and the first suppression sheet covering the upper surface of the power circuit is selected from copper foil, wherein the power electron tube of the power circuit is disposed on the circuit board.

[0011] Furthermore, in some embodiments of the present invention, the power electron tube is disposed between the first suppression sheet and the second suppression sheet in a leadless stacked configuration.

[0012] Furthermore, in some embodiments of the present invention, the first suppression sheet and / or the second suppression sheet are made of a flexible conductive material.

[0013] Furthermore, in some embodiments of the present invention, the power circuit includes a plurality of power electron tubes, wherein an electromagnetic isolation sheet made of conductive material is provided between each adjacent power electron tube, and the electromagnetic isolation sheet is kept separate from the first suppression sheet and the second suppression sheet respectively.

[0014] Furthermore, in some embodiments of the present invention, the power circuit includes at least one of a half-bridge circuit, a full-bridge circuit, and a multi-phase bridge circuit.

[0015] Furthermore, a second aspect of the present invention provides a power circuit module. A first surface of the power circuit module is covered with a first suppression sheet made of a conductive material. A second surface of the power circuit module is covered with a second suppression sheet made of a conductive material. The first surface and the second surface are located in opposite directions of the power circuit module. The first suppression sheet is connected to a first terminal of at least one decoupling capacitor. The second suppression sheet is connected to a second terminal of the at least one decoupling capacitor. During operation of the power circuit module, the at least one decoupling capacitor absorbs an induced current opposite to the operating current of the power circuit module from the first suppression sheet and the second suppression sheet.

[0016] Furthermore, a third aspect of the present invention provides a method for suppressing parasitic inductance, comprising the steps of: covering a first suppressor sheet made of a conductive material on a first surface of a power circuit; covering a second suppressor sheet made of a conductive material on a second surface of the power circuit, wherein the first surface and the second surface are located in opposite directions of the power circuit; and connecting the first suppressor sheet to a first terminal of at least one decoupling capacitor and connecting the second suppressor sheet to a second terminal of the at least one decoupling capacitor, so as to utilize the at least one decoupling capacitor to absorb induced current opposite to the operating current of the power circuit module from the first suppressor sheet and the second suppressor sheet during operation of the power circuit module. Attached Figure Description

[0017] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0018] Figure 1 A circuit diagram of a power circuit module provided according to some embodiments of the present invention is shown.

[0019] Figure 2 A schematic diagram of the structure of a power circuit module provided according to some embodiments of the present invention is shown.

[0020] Figure 3A flowchart illustrating a method for suppressing parasitic inductance according to some embodiments of the present invention is shown.

[0021] Figure 4A A schematic diagram of the forward current of a power circuit module and a first suppression chip provided according to some embodiments of the present invention is shown.

[0022] Figure 4B A schematic diagram of the back current of a power circuit module and a second suppression chip provided according to some embodiments of the present invention is shown.

[0023] Figure 4C A top-view current diagram of a power circuit module and suppression chip provided according to some embodiments of the present invention is shown.

[0024] Figure 5 A three-dimensional schematic diagram of a power circuit module provided according to some embodiments of the present invention is shown.

[0025] Figure 6 A cross-sectional schematic diagram of a power circuit module provided according to some embodiments of the present invention is shown.

[0026] Figure 7 A top view schematic diagram of a power electron tube provided according to some embodiments of the present invention is shown.

[0027] Figure 8A A side-view current schematic diagram of a power circuit module and a suppression chip provided according to some embodiments of the present invention is shown.

[0028] Figure 8B A top-view current diagram of a power circuit module and a suppression chip provided according to some embodiments of the present invention is shown.

[0029] Figure 8C A top-view current diagram of a power circuit module and suppression chip provided according to some embodiments of the present invention is shown. Detailed Implementation

[0030] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0033] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0034] As mentioned above, existing solutions for reducing parasitic parameters mainly achieve this by reducing the overall trace length of the package. However, these solutions suffer from drawbacks such as complex processes, high costs, limited effectiveness, and uncertain results, making it difficult to meet the further development needs of power devices.

[0035] In order to overcome the above-mentioned defects of the prior art, the present invention provides a parasitic inductance suppression structure, a power circuit module, and a method for suppressing parasitic inductance, which can reduce the parasitic inductance of the power module or even the entire power circuit in a low cost and with high efficiency.

[0036] In some non-limiting embodiments, the parasitic inductance suppression structure provided in the first aspect of the present invention can be disposed in the power circuit module provided in the second aspect of the present invention to implement the parasitic inductance suppression method provided in the third aspect of the present invention, thereby reducing the parasitic inductance of the power module, or even the entire power circuit, at low cost and with high efficiency. Here, the power circuit module provided in the second aspect of the present invention can be selected from power electronic circuits including at least one power electronic component such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT), including but not limited to at least one of a half-bridge circuit, a full-bridge circuit, and a multiphase bridge circuit.

[0037] The following will describe the working principle of the parasitic inductance suppression structure and its installation method in a power circuit module, using examples of methods for suppressing parasitic inductance. Those skilled in the art will understand that these examples of methods for suppressing parasitic inductance are merely non-limiting embodiments provided by this invention, intended to clearly demonstrate the main concepts of the invention and provide specific solutions convenient for public implementation, rather than limiting all functions, operating modes, or installation methods of the suppression structure. Similarly, these suppression structures and power circuit modules are also merely non-limiting embodiments provided by this invention and do not limit the executing subject, object, or method of execution of each step in these methods for suppressing parasitic inductance.

[0038] Please refer to the following first. Figures 1 to 3 . Figure 1 A circuit diagram of a power circuit module provided according to some embodiments of the present invention is shown. Figure 2 A schematic diagram of the structure of a power circuit module provided according to some embodiments of the present invention is shown. Figure 3 A flowchart illustrating a method for suppressing parasitic inductance according to some embodiments of the present invention is shown.

[0039] by Figure 1 Taking the half-bridge circuit shown as an example, this power circuit module includes two power tubes S H S L And the supporting capacitor C at both ends of the DC bus connecting the power circuit module. dc Its specific circuit structure and working principle are well-known in this field and will not be elaborated here.

[0040] like Figure 2 and Figure 3As shown, in some embodiments of the present invention, the two power tubes S of the power circuit module H S L Infineon's IPW60R190P6 package can be selected, and it can be vertically mounted on the circuit board 20 via pin insertion. To suppress the parasitic inductance of this power circuit module, technicians can first address the issue on the first surface of the power circuit (e.g., the power tube S). H S L The front surface of the power circuit is covered with a first suppression sheet 11 made of conductive material, and the second surface of the power circuit (e.g., the power tube S) .... H S L A second suppression sheet 12, made of conductive material, is covered over the rear surface of the power circuit module to form a fully enclosed shielding structure. The conductive material used to fabricate the first suppression sheet 11 and / or the second suppression sheet 12 can be copper, aluminum, silver, or other materials, and is not limited thereto. Subsequently, a technician can connect the first suppression sheet 11 to the first terminals of multiple decoupling capacitors C1 and C2, and connect the second suppression sheet 12 to the second terminals of the decoupling capacitors C1 and C2. Thus, during operation of the power circuit, at least one decoupling capacitor C1 and C2 absorbs induced currents opposite to the operating current of the power circuit from the first suppression sheet 11 and the second suppression sheet 12, thereby eliminating electromagnetic radiation emitted by the power circuit module and reducing the parasitic inductance of the power circuit module in the entire loop.

[0041] Please refer to the reference. Figure 2 and Figures 4A to 4C . Figure 4A A schematic diagram of the forward current of a power circuit module and a first suppression chip provided according to some embodiments of the present invention is shown. Figure 4B A schematic diagram of the back current of a power circuit module and a second suppression chip provided according to some embodiments of the present invention is shown. Figure 4C A top-view current diagram of a power circuit module and suppression chip provided according to some embodiments of the present invention is shown.

[0042] like Figure 2 and Figures 4A to 4C As shown, during the operation of the power circuit module, the operating current (solid line) will flow from the supporting capacitor C. dc The high-voltage end flows out from the power tube S H The drain (D) flows into the power tube S H Then, the power electron tube S flows out through its source (S). H Or from the supporting capacitor C dc The low-voltage side flows out, from the power tube S H The source (S) flows into the power tube S LThen, the power electron tube S flows out through its drain (D). L By constructing the above-mentioned fully enclosed shielding structure, the first suppression sheet 11 and the second suppression sheet 12 will generate an induced current (dashed line) that is opposite to the operating current of the power circuit module when the power circuit module is running.

[0043] like Figure 4A and Figure 4C As shown, by connecting the first suppression plate 11 and the second suppression plate 12 to the two ends of the decoupling capacitors C1 and C2, the decoupling capacitors C1 and C2 can absorb the induced current from the first suppression plate 11 and the second suppression plate 12 to eliminate the electromagnetic radiation emitted by the power circuit module, thereby reducing the parasitic inductance of the power circuit module in the entire circuit.

[0044] Furthermore, experiments have shown that the parasitic inductance of the power circuit module in the loop depends on the size of its external radiation space. In some embodiments, to further reduce the parasitic inductance of the power circuit module, the first suppression sheet 11 and / or the second suppression sheet 12 can be made of flexible conductive materials such as copper foil. Figure 4C As shown, the first suppression sheet 11, made of copper foil, can be adapted to the first surface of the power circuit (i.e., the power tube S). H S L The shape of the front surface of the power circuit is deformed to fit snugly over the first surface of the power circuit, thereby further reducing the radiation space of the power circuit module and further reducing its parasitic inductance.

[0045] Those skilled in the art will understand that Figure 2 The embodiment shown, in which multiple power tubes are arranged in parallel and longitudinally, and the first suppression sheet 11 and the second suppression sheet 12 are respectively covered on the front and rear surfaces of the power circuit, is only a non-limiting implementation provided by the present invention. It is intended to clearly demonstrate the main concept of the present invention and provide some specific solutions that are easy for the public to implement, rather than to limit the scope of protection of the present invention.

[0046] Optionally, in other embodiments, the present invention may also arrange multiple power electron tubes longitudinally in a front-to-back arrangement, and cover the left and right surfaces of the power circuit with the first and second suppression sheets respectively, perpendicular to the main flow direction of the operating current in the power circuit, so as to similarly achieve the effect of eliminating the electromagnetic radiation of the power circuit module and reducing the parasitic inductance of the power circuit module in the entire circuit.

[0047] Optionally, in other embodiments, the present invention may also arrange multiple power electron tubes laterally along the circuit board, and cover the upper and lower surfaces of the power circuit with the first suppression sheet and the second suppression sheet respectively, so as to achieve the same effect of eliminating the electromagnetic radiation emitted by the power circuit module and reducing the parasitic inductance of the power circuit module in the whole circuit.

[0048] Furthermore, those skilled in the art will understand that Figure 2 and Figures 4A to 4C The arrangement of multiple decoupling capacitors C1 and C2 at both ends of the first suppression plate 11 and the second suppression plate 12 shown is only a preferred embodiment provided by the present invention. It aims to shorten the distance between the decoupling capacitors C1 and C2 and the induced current, so as to enhance the absorption effect of the decoupling capacitors C1 and C2 on the induced current, thereby further reducing the parasitic inductance of the power circuit module, rather than limiting the scope of protection of the present invention.

[0049] Optionally, in other embodiments, the present invention may also provide a decoupling capacitor only at one end of the first suppression plate 11 and the second suppression plate 12, with the first end of the decoupling capacitor connected to the first suppression plate 11 and the second end connected to the second suppression plate 12, and the other ends of the first suppression plate 11 and the second suppression plate 12 separated by an air gap or insulating material, so as to achieve the same effect of using the decoupling capacitor to absorb the induced current reversed from the operating current of the power circuit from the first suppression plate 11 and the second suppression plate 12.

[0050] Furthermore, those skilled in the art will understand that Figure 2 and Figures 4A to 4C The embodiment shown, in which the first suppression sheet 11 and the second suppression sheet 12 are covered on the surface of the packaged power electron tube, is only a non-limiting implementation provided by the present invention. It is intended to clearly demonstrate the main concept of the present invention and provide some specific solutions that are easy for the public to implement, rather than to limit the scope of protection of the present invention.

[0051] Please refer to the reference. Figures 5 to 7 . Figure 5 A three-dimensional schematic diagram of a power circuit module provided according to some embodiments of the present invention is shown. Figure 6 A cross-sectional schematic diagram of a power circuit module provided according to some embodiments of the present invention is shown. Figure 7 A top view schematic diagram of a power electron tube provided according to some embodiments of the present invention is shown.

[0052] like Figures 5 to 7 As shown, in some preferred embodiments, the power tubes S of the power circuit H S LIt can be horizontally arranged on the circuit board in a leadless stacked configuration. Technicians can select a circuit board with a grounded copper layer (i.e., a ground plane) as the second suppression sheet 52, lay it down and cover the lower surface of the power circuit, and select a shaping copper foil as the first suppression sheet 51 to cover and adhere to the upper surface of the power circuit. At this time, the power tubes S of the power circuit... H S L Located between the first suppressor 51 and the second suppressor 52. Then, as described above, a technician can connect one end (e.g., the right end) of the first suppressor 51 to the first end (e.g., DC+ or DC-) of the decoupling capacitor C3, and connect the same end (e.g., the right end) of the second suppressor 52 to the second end (e.g., DC- or DC+) of the decoupling capacitor C3, thereby allowing the decoupling capacitor C3 to absorb induced currents that are reversed from the operating current of the power circuit from the first suppressor 51 and the second suppressor 52 during power circuit operation.

[0053] Please refer to further information. Figures 8A to 8C . Figure 8A A side-view current schematic diagram of a power circuit module and a suppression chip provided according to some embodiments of the present invention is shown. Figure 8B A top-view current diagram of a power circuit module and a suppression chip provided according to some embodiments of the present invention is shown. Figure 8C A top-view current diagram of a power circuit module and suppression chip provided according to some embodiments of the present invention is shown.

[0054] like Figures 8A to 8C As shown, during the operation of the power circuit module, the operating current (solid line) will flow from the supporting capacitor C. dc The high-voltage terminal (DC+) flows out from the power tube S H The drain (D) flows into the power tube S H Then, the power electron tube S flows out through its source (S). H Or from the supporting capacitor C dc The low-voltage side (DC-) flows out from the power tube S H The source (S) flows into the power tube S L Then, the power electron tube S flows out through its drain (D). LBy constructing the aforementioned fully enclosed shielding structure, the first suppression plate 51 and the second suppression plate 52 will generate an induced current (dashed line) that is opposite to the operating current of the power circuit module during operation. Furthermore, by connecting the first suppression plate 51 and the second suppression plate 52 to the two ends of the decoupling capacitor C3, the decoupling capacitor C3 can absorb this induced current from the first suppression plate 51 and the second suppression plate 52, thereby eliminating the electromagnetic radiation emitted by the power circuit module and reducing the parasitic inductance of the power circuit module in the entire loop. Even further, by using a copper foil with shaping capabilities as the first suppression plate 51, the first suppression plate 51 can adapt to the shape of the upper surface of the power circuit and deform to fit snugly over the upper surface of the power circuit, thereby further reducing the radiation space of the power circuit module and, in conjunction with the leadless stacking configuration, reducing the parasitic inductance of the power circuit module to less than 10 times the original parasitic inductance.

[0055] In addition, such as Figure 5 and Figure 6 As shown, this relates to multiple power electron tubes S arranged laterally on a circuit board in a leadless stacked configuration. H S L Each adjacent power tube S H S L An electromagnetic isolation sheet 53 made of conductive material can preferably be provided between them. This electromagnetic isolation sheet 53 can be kept separate from the first suppression sheet 51 and the second suppression sheet 52 to avoid affecting their circuit characteristics. By providing this electromagnetic isolation sheet 53, the present invention can further divide the fully enclosed shielding space between the first suppression sheet 51 and the second suppression sheet 52, thereby further reducing the voltage drop across each power tube S. H S L The external radiation space, thereby further reducing the S of each power tube. H S L Parasitic inductance.

[0056] Those skilled in the art will understand that the above-described embodiment, in which a copper foil with shaping function is used as the first suppressor 51 to cover and adhere to the upper surface of the power circuit, is merely a non-limiting implementation provided by the present invention. It is intended to clearly demonstrate the main concept of the present invention and provide a preferred solution for reducing the radiation space of the power circuit module, rather than to limit the scope of protection of the present invention.

[0057] Optionally, in other embodiments, the present invention may also use a flexible circuit board as the second suppression sheet 52, covering and adhering to the lower surface of the power circuit, to similarly reduce the external radiation space of the power circuit module and reduce the parasitic inductance of the power circuit module in the entire loop. Here, the driving circuit components of the power circuit module can be integrally fabricated on the flexible circuit board using microelectronic inkjet printing technology to provide modularity, customization, miniaturization, and portability.

[0058] Furthermore, those skilled in the art will understand that the above-described half-bridge circuit embodiment is merely a non-limiting implementation method provided by the present invention. Compared to the basic implementation method of covering a single power electronic device with a suppression sheet, this solution can reduce the overall loop inductance on a functional circuit basis. On the one hand, it reduces the device cost and space requirements of the suppression structure; on the other hand, it avoids the uncertainty of the parasitic parameters of individual components after they are connected to the loop, thereby suppressing the parasitic inductance of the entire power circuit more accurately and reliably.

[0059] Alternatively, in other embodiments, based on the above-described inventive concept and implementation of the present invention, those skilled in the art can also install the above-described parasitic inductance suppression structure on various power circuit modules such as full-bridge circuits, multi-phase bridge circuits, Boost circuits, and Buck circuits to achieve the same technical effect of reducing their parasitic inductance, which will not be elaborated here.

[0060] In summary, the parasitic inductance suppression structure, power circuit module, and method for suppressing parasitic inductance provided by this invention can overcome the shortcomings of existing technologies, such as complex processes, high costs, limited effectiveness, and uncertain compensation effects. It can reduce the parasitic inductance of power modules and even the entire power circuit in a low-cost and efficient manner, which is of positive significance for the promotion and development of power electronics technology.

[0061] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0062] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A structure for suppressing parasitic inductance, characterized in that, include: The first suppression sheet, made of conductive material, covers the first surface of the power circuit; A second suppression sheet, made of conductive material, covers a second surface of the power circuit, wherein the first surface and the second surface are located in opposite directions of the power circuit; as well as At least one decoupling capacitor, with its first end connected to the first suppression plate and its second end connected to the second suppression plate, is used to absorb induced current in the opposite direction to the operating current of the power circuit from the first suppression plate and the second suppression plate during operation of the power circuit.

2. The suppression structure as described in claim 1, characterized in that, The suppression structure includes only one decoupling capacitor, wherein the two ends of the decoupling capacitor are respectively connected to the first end of the first suppression sheet and the first end of the second suppression sheet, and the second ends of the first suppression sheet and the second suppression sheet remain separated, or The suppression structure includes a plurality of decoupling capacitors, wherein the two ends of the first decoupling capacitor are respectively connected to the first end of the first suppression sheet and the first end of the second suppression sheet, and the two ends of the second decoupling capacitor are respectively connected to the second end of the first suppression sheet and the second end of the second suppression sheet.

3. The suppression structure as described in claim 1, characterized in that, The power circuit includes at least one power vacuum tube, wherein... The power tube is arranged laterally, the first suppression sheet covers the upper surface of the power circuit, and the second suppression sheet covers the lower surface of the power circuit, or... The power tube is arranged longitudinally, the first suppression sheet covers the front surface of the power circuit, and the second suppression sheet covers the rear surface of the power circuit, or... The power tube is arranged longitudinally, the first suppression sheet covers the left surface of the power circuit, and the second suppression sheet covers the right surface of the power circuit.

4. The suppression structure as described in claim 3, characterized in that, The second suppression sheet covering the lower surface of the power circuit is made of a circuit board with a grounded copper layer, and the first suppression sheet covering the upper surface of the power circuit is made of copper foil, wherein the power electron tube of the power circuit is disposed on the circuit board.

5. The suppression structure as described in claim 3, characterized in that, The power electron tubes are arranged in a leadless stack between the first suppression plate and the second suppression plate.

6. The suppression structure as described in claim 1 or 5, characterized in that, The first and / or the second suppression sheet are made of a flexible conductive material.

7. The suppression structure as described in claim 3, characterized in that, The power circuit includes a plurality of power electron tubes, wherein an electromagnetic isolation sheet made of conductive material is provided between each adjacent power electron tube, and the electromagnetic isolation sheet is kept separate from the first suppression sheet and the second suppression sheet respectively.

8. The suppression structure as described in claim 1, characterized in that, The power circuit includes at least one of a half-bridge circuit, a full-bridge circuit, and a multi-phase bridge circuit.

9. A power circuit module, characterized in that, The first surface of the power circuit module is covered with a first suppression sheet made of conductive material, and the second surface of the power circuit module is covered with a second suppression sheet made of conductive material. The first surface and the second surface are located in opposite directions of the power circuit module. The first suppression sheet is connected to the first terminal of at least one decoupling capacitor, and the second suppression sheet is connected to the second terminal of the at least one decoupling capacitor. The at least one decoupling capacitor absorbs an induced current that is opposite to the operating current of the power circuit module from the first suppression sheet and the second suppression sheet when the power circuit module is running.

10. A method for suppressing parasitic inductance, characterized in that, Includes the following steps: A first suppression sheet made of conductive material is covered on the first surface of the power circuit; A second suppression sheet made of conductive material is covered on the second surface of the power circuit, wherein the first surface and the second surface are located in opposite directions of the power circuit; as well as The first suppression plate is connected to the first terminal of at least one decoupling capacitor, and the second suppression plate is connected to the second terminal of the at least one decoupling capacitor, so that the at least one decoupling capacitor can absorb induced current that is opposite to the operating current of the power circuit module from the first suppression plate and the second suppression plate when the power circuit module is running.

Images