Integrated circuit and method and system for testing the same

Abstract

Embodiments of the invention provide an integrated circuit comprising a first circuit formed based on one or more III-V compound materials, the first circuit configured to operate at a first voltage range. The integrated circuit comprises a second circuit also formed based on one or more III-V compound materials, the second circuit operably connected to the first circuit and configured to operate at a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit comprises a first set of test terminals connected to the first circuit. The integrated circuit comprises a second set of test terminals connected to the second circuit. Test signals applied to the first set of test terminals and the second set of test terminals, respectively, are independent of each other. Embodiments of the invention also provide methods and systems for testing integrated circuits.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to integrated circuits and their testing methods and systems. Background Technology

[0002] Over the past few decades, silicon-based electronics (such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) have been quite successful and represent the current standard for power supply applications ranging from tens of watts to hundreds or even kilowatts (e.g., AC / DC power supplies, DC / DC power supplies, and motor control). These silicon-based electronics have seen continuous improvements in key parameters such as on-resistance RDS(ON), rated voltage, switching speed, packaging, and other properties. However, the rate of improvement in these silicon-based electronics has plateaued as their performance now approaches the theoretical limits determined by the underlying physical properties of these materials and processes. Summary of the Invention

[0003] One aspect of the present invention provides an integrated circuit comprising: a first circuit formed based on one or more III-V compound materials and configured to operate in a first voltage range; a second circuit, also formed based on the one or more III-V compound materials, operatively connected to the first circuit and configured to operate in a second voltage range, wherein the second voltage range is significantly higher than the first voltage range; a set of first test terminals connected to the first circuit; and a set of second test terminals connected to the second circuit; wherein test signals applied to the set of first test terminals and the set of second test terminals are independent of each other.

[0004] Another aspect of the present invention provides a method for testing an integrated circuit, comprising: providing an integrated circuit including a first circuit and a second circuit operatively connected to each other, wherein the first circuit includes at least a first transistor operating in a first voltage range, and the second circuit includes at least a second transistor operating in a second voltage range, wherein the second voltage range is significantly higher than the first voltage range; applying a plurality of first test signals to the first transistor through a plurality of first test terminals of the integrated circuit; and applying a plurality of second test signals to the second transistor through a plurality of second test terminals of the integrated circuit; wherein the plurality of first test signals are configured independently of the plurality of second test signals.

[0005] Another aspect of the present invention provides a test system for testing an integrated circuit, comprising: a signal generator configured to: apply a plurality of first test signals to a first transistor of the integrated circuit via a plurality of first test terminals of the integrated circuit, wherein the first transistor includes gallium nitride and is configured to operate at a first voltage range; and apply a plurality of second test signals to a second transistor of the integrated circuit via a plurality of second test terminals of the integrated circuit, wherein the second transistor includes gallium nitride and is configured to operate at a second voltage range significantly higher than the first voltage range; and a controller operatively connected to the signal generator and configured to determine the plurality of first test signals independent of the plurality of second test signals. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A block diagram of a GaN-based integrated circuit according to some embodiments is shown.

[0008] Figure 2 Illustrations are shown according to some embodiments Figure 1 Detailed block diagram of GaN-based integrated circuits.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 Illustrations are shown according to some embodiments Figure 1 Cross-sectional views of various GaN-based components in GaN-based integrated circuits.

[0010] Figure 9 , Figure 10 and Figure 11 Illustrations are shown according to some embodiments Figure 1 Example circuit diagrams of various GaN-based integrated circuits.

[0011] Figure 12 A test is shown according to some embodiments. Figure 1 A flowchart illustrating an example method for GaN-based integrated circuits.

[0012] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 The diagram illustrates the use of some embodiments by Figure 12 The method applies to various test signals.

[0013] Figure 19 A block diagram of a test system for testing GaN-based integrated circuits, according to some embodiments, is shown. Detailed Implementation

[0014] This invention provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one component or component and another (or other components or parts) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] Group III-V (or III-V) semiconductor compounds are generally considered alternatives to silicon due to their superior material properties compared to silicon. For example, gallium nitride (GaN)-based materials have been extensively studied in various electronic and / or optoelectronic applications. GaN-based materials typically refer to gallium nitride (GaN) and its alloys, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). In particular, GaN-based materials are wide-bandgap semiconductors that maintain their electrical properties at higher temperatures compared to other semiconductors such as silicon or gallium arsenide. GaN-based materials also exhibit higher carrier saturation velocities compared to silicon. Furthermore, GaN-based materials have a wurtzite crystal structure, are hard materials with high thermal conductivity, and have much higher melting points than other conventional semiconductors such as silicon, germanium, and gallium arsenide. Therefore, GaN-based materials can be used in high-voltage and high-power applications.

[0017] Typically, only high-voltage devices are formed from GaN-based materials, while low-voltage devices can still be formed from silicon. This hybrid integration can sometimes have adverse effects, such as increased manufacturing costs / complexity, additional substrate area consumption, and relatively large parasitic inductance. With advancements in semiconductor fabrication technology, high-voltage and low-voltage devices that are monolithically integrated using the same GaN-based material have become common, sometimes referred to as GaN-based integrated circuits. For example, a GaN-based integrated circuit can include multiple circuits operating in a relatively high voltage range (e.g., control circuits, drivers, protection circuits, etc.) and multiple circuits operating in a relatively low voltage range (e.g., power transistors), each of which can include at least one GaN-based material formed as one of its active components (e.g., transistor channels).

[0018] Despite the significant commercial importance of GaN-based optoelectronic and electronic devices, their quality and reliability are often affected by relatively high defect levels in one or more semiconductor layers. Such defects can arise from: (1) lattice mismatch between the GaN-based semiconductor layer and a non-GaN substrate (such as silicon, sapphire, or silicon carbide); (2) coalescence front of the epitaxial growth layer; (3) thermal expansion mismatch; (4) impurities; and (5) tilted boundaries. The presence of defects has a detrimental effect on the epitaxial growth layer. This effect includes impairing the performance of electronic / optoelectronic devices.

[0019] To overcome these drawbacks, techniques have been proposed that require complex and cumbersome manufacturing processes to reduce the concentration and / or impact of defects. While numerous conventional growth methods for GaN-based crystals have been proposed, limitations remain. For example, conventional techniques can only detect, test, screen, or otherwise identify such defects before fabricating a complete GaN-based integrated circuit. Although some techniques have been proposed to identify certain defects in high-voltage devices, these techniques cannot identify any defects on the low-voltage side and sometimes cause additional damage to the low-voltage devices during high-voltage testing. For example, existing GaN-based integrated circuits typically have corresponding power supplies for low-voltage and high-voltage circuits interconnected, which may inherently lead to at least the aforementioned adverse effects. In other words, no effective and efficient techniques have been proposed at the circuit level to detect, test, screen, or otherwise identify those "material-level" defects in GaN-based integrated circuits.

[0020] This disclosure provides various embodiments of GaN-based integrated circuits that allow for the detection of defects in either the low-voltage or high-voltage circuitry of the GaN-based integrated circuit at the circuit level. In various embodiments, as disclosed herein, the GaN-based integrated circuit includes a corresponding number of test terminals (pads or pins) connected to each of the low-voltage and high-voltage circuits. According to various embodiments, these test terminals, distributed across the different high / low-voltage circuits, can be electrically isolated from each other or otherwise operatively isolated. In this way, defects or faults present in the high-voltage and low-voltage circuits can be identified jointly or individually. For example, this disclosure provides various embodiments of methods utilizing these test terminals to jointly identify epitaxial defects that may be present in both the high-voltage and low-voltage circuits, individually identify surface defects that may be present in the high-voltage circuit, individually identify defects that may be present in the gate-to-source junction of the high-voltage circuit while significantly suppressing leakage current from the low-voltage circuit, and separately identify faults in each of the low-voltage and high-voltage circuits.

[0021] Figure 1 Block diagrams of a GaN-based integrated circuit 100 according to various embodiments are shown. It should be understood that... Figure 1 The block diagram is simplified for illustrative purposes. Therefore, the GaN-based integrated circuit 100 may include any of a variety of other (e.g., functional) blocks while remaining within the scope of this disclosure.

[0022] As will be discussed below, the GaN-based integrated circuit 100 includes multiple components formed from GaN-based materials, such as gallium nitride (GaN) and its alloys, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Examples of these components include, but are not limited to, transistors, resistors, capacitors, diodes, etc. This GaN-based material can be epitaxially grown on a non-GaN-based material (e.g., silicon, sapphire, and / or silicon carbide) used as a substrate for the GaN-based integrated circuit 100. The GaN-based integrated circuit 100 can be implemented as a single system-on-a-chip (SoC) architecture or a multi-SoC architecture. Therefore, the GaN-based integrated circuit 100 can be formed on a single substrate or multiple substrates.

[0023] As shown in the figure, the GaN-based integrated circuit 100 includes at least one high-voltage circuit (or circuitry) 110 and at least one low-voltage circuit (or circuitry) 160. In various embodiments, the high-voltage circuit 110 and the low-voltage circuit 110 and the voltage circuit 160 are operatively connected to each other. Each of the high-voltage circuit 110 and the low-voltage circuit 160 includes multiple GaN-based components. Therefore, the high-voltage circuit 110 and the low-voltage circuit 160 can sometimes be referred to as monolithically integrated in the GaN-based integrated circuit 100, which can be used, for example, as an all-GaN power integrated circuit (e.g., a power converter).

[0024] In various embodiments, components of the high-voltage circuit 110 can operate at voltage ranges significantly higher than the voltage range at which components of the low-voltage circuit 160 can operate. For example, components of the high-voltage circuit 110 can operate at voltage ranges exceeding 40 volts (e.g., around 600 volts), while components of the low-voltage circuit 160 can operate at voltage ranges up to 12 volts. However, it should be understood that the corresponding components of the high-voltage circuit 110 and the low-voltage circuit 160 can operate at any of a variety of other voltage ranges while remaining within the scope of this disclosure.

[0025] In various embodiments, the GaN-based integrated circuit 100 further includes a plurality of (test) terminals 102-1, 102-2, 102-3, 102-4, 102-5, 102-6, 102-7, 102-8, 102-9, 102-10, 102-11, and 102-12. Terminals 102-1 to 102-12 are operatively (e.g., electrically) isolated from each other. Furthermore, terminals 102-1 to 102-5 and terminals 102-10 to 102-12 are operatively connected to a low-voltage circuit 160, and terminals 102-6, 102-8, and 102-9 are operatively connected to a high-voltage circuit 110, while terminal 102-7 is connected to one or more substrates of the GaN-based integrated circuit 100. With each set of terminals correspondingly connected to the high-voltage circuit 110 and the low-voltage circuit 160, various defects in the high-voltage circuit 110 and / or the low-voltage circuit 160 can be efficiently and effectively identified, which will be discussed in more detail below. In various embodiments, each of terminals 102-1 to 102-12 is electrically connected via multiple interconnect structures (e.g., metal wires, metal vias, etc.) to one or more bump structures (e.g., solder balls, copper bumps, copper pillars, or other connecting elements) of the GaN-based integrated circuit 100, and electrically connected to electrodes of GaN-based components (e.g., transistors, capacitors, resistors, diodes, etc.) of the GaN-based integrated circuit 100.

[0026] According to various embodiments, reference Figure 2A further detailed block diagram of a GaN-based integrated circuit 100 is shown as a representative example. It should be understood that... Figure 2 The block diagram is simplified for illustrative purposes. Therefore, each of the high-voltage circuit 110 and the low-voltage circuit 160 may include any of other various (e.g., functional) blocks or components, while remaining within the scope of this disclosure. As shown, the high-voltage circuit 110 includes a plurality of power transistors 210 (e.g., connected in series with each other); the low-voltage circuit 160 includes an electrostatic discharge (ESD) protection circuit 260, a control circuit 262, and a drive circuit 264.

[0027] On the high-voltage side, the power transistor 210 has a gate (G), source (S), and drain (D) connected to terminals 102-9, 102-6, and 102-8, respectively. On the low-voltage side, an ESD protection circuit can be connected to terminals 102-1, 102-2, 102-3, and 102-4; a control circuit 262 can be connected to terminals 102-1, 102-2, and 102-12 (and connected to terminal 102-4 via the ESD protection circuit 260); and a drive circuit 264 is connected to terminals 102-5, 102-10, and 102-11. According to various embodiments, each of terminals 102-1 to 102-12 can be implemented as a pin of a GaN-based integrated circuit 100.

[0028] In various embodiments, ESD protection circuit 260 can prevent ESD events from occurring to (or damaging) connected circuitry, such as control circuitry 262. Terminals 102-2 (which can be used as input / output (I / O) pins of GaN-based integrated circuit 100) and 102-4 can be used as the high side and low side of ESD protection circuit 260, respectively. For example, terminals 102-2 and 102-4 can respectively prevent ESD pulses from being connected to control circuitry 262. Terminal 102-3 can be connected as a probe terminal to one or more internal nodes of ESD protection circuitry 260 to test whether ESD protection circuitry 260 is functioning correctly. Terminal 102-3 is optionally formed. Control circuitry 262, which can receive one or more input signals through terminal 102-2 and power supply voltage through terminal 103-12, can provide one or more control signals to drive circuitry 264. Terminal 102-1 can be connected as a probe terminal to one or more internal nodes of control circuitry 262 to test whether control circuitry 262 is functioning correctly. Terminal 102-11 can be connected to the input terminal of drive circuit 264, which can provide a functional signal (e.g., functional voltage) to test drive circuit 264. Terminals 102-10 and 102-5 can provide different power supplies to apply voltages to drive circuit 264 respectively. Terminal 102-9 can be connected to the input terminal of power transistor 210, which can provide a functional signal (e.g., functional voltage) to power transistor 210. Terminals 102-8 and 102-6 can provide different power supply voltages to power transistor 210 respectively. Power transistor 210, which can be implemented as a switch or linear regulator, can charge the load of GaN-based integrated circuit 100 through the I / O pins (not shown) of GaN-based integrated circuit 100.

[0029] According to various embodiments, Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8Various exemplary GaN-based components 300, 400, 500, 600, 700, and 800 are shown, which can be implemented as at least one of the high-voltage circuit 110 and low-voltage circuit 160 constituting the GaN-based integrated circuit 100. Each of the GaN-based components 300 to 800 includes at least one GaN-based material (e.g., GaN, AlGaN, InGaN, AlInGaN, etc.) used as its active element (e.g., the active channel of a transistor). Furthermore, the GaN-based components 300 to 800 can be formed on the same or different non-GaN-based substrates (e.g., silicon) of the integrated circuit 100. Thus, each of the GaN-based components 300 to 800 has one or more GaN-based materials epitaxially grown on a non-GaN-based substrate, which may have some of the defects described above present in the GaN-based material layers or at the interfaces of different GaN-based layers.

[0030] It should be understood that this information is provided for illustrative purposes only. Figure 3 - Figure 8 The schematic cross-sectional view shown is not intended to limit the scope of this disclosure. Therefore, the GaN-based integrated circuit 100 may include any of a variety of other GaN-based and / or non-GaN-based components while remaining within the scope of this disclosure.

[0031] First refer to Figure 3 Component 300 can be implemented as a power transistor that can be used in the high-voltage circuit 110. In some embodiments, component 300 can be a high electron mobility transistor (HEMT) with high current density, high breakdown voltage (the ability of a HEMT to withstand high gate and / or drain voltages without being damaged and / or exhibiting irregular current behavior) and low on-resistance, which allows component 300 to maintain operation in a voltage range of about 40 volts to about 650 volts. Therefore, component 300 is referred to below as "power HEMT 300". The two-dimensional electron gas (2DEG) discussed below is typically used as the charge carrier in such a HEMT.

[0032] like Figure 3 As shown in the cross-sectional view, the power HEMT 300 includes a substrate 310, a transition structure 320 above the substrate 310, a buffer layer 330 above the transition structure 320, a channel layer 340 above the buffer layer 330, and an active layer 350 above the channel layer 340. The power HEMT 300 optionally includes a barrier structure 360 ​​between the substrate 310 and the channel layer 340. The power HEMT 300 also includes a source electrode 372 and a drain electrode 374 located above the channel layer 340, and a gate electrode 380 located above the active layer 350. In some embodiments, the source electrode 372 and the drain electrode 374 are formed above the active layer 350.

[0033] The substrate 310 includes a silicon carbide (SiC) substrate, a sapphire substrate or a silicon (Si) substrate. In at least one embodiment, the substrate 310 includes a Si (111) wafer to provide an optimal lattice mismatch with an overlying layer (such as the GaN layer described herein).

[0034] The transition structure 320 includes a nucleation layer 322 over the substrate 310. The nucleation layer 322 has a lattice structure and / or a thermal expansion coefficient (TEC) that is suitable for reducing the lattice mismatch and / or the TEC mismatch between the substrate 310 and an overlying layer (such as the GaN layer described herein). In some embodiments, the nucleation layer 322 includes aluminum nitride (AlN). In some embodiments, the nucleation layer 322 has a thickness of 70 to 300 nanometers (nm). In some embodiments, the nucleation layer 322 is omitted.

[0035] In one or more embodiments where the nucleation layer 322 is omitted, the transition structure 320 further includes a transition layer 324 over the nucleation layer 322 or over the substrate 310. The transition layer 324 also facilitates a gradual change in the lattice structure and TEC between the nucleation layer 322 (or the substrate 310) and an overlying layer (such as the GaN layer described herein). In some embodiments, the transition layer 324 includes a graded aluminum-gallium nitride (Al x Ga (1-x) N, where x is the aluminum content ratio in the aluminum-gallium component, 0 < x < 1) layer. In some embodiments, the graded aluminum gallium nitride layer includes a plurality of layers from a bottom layer adjacent to the substrate 310 to a top layer adjacent to the buffer layer 330, each layer having a reduced ratio x. In at least one embodiment, the graded aluminum gallium nitride layer has three layers, with the x ratio of the bottom layer in the range of 0.7 - 0.9, the x ratio of the middle layer in the range of 0.4 - 0.6, and the x ratio of the top layer in the range of 0.15 - 0.3. In some embodiments, instead of having a plurality of layers with different x ratios, the graded aluminum gallium nitride layer has a continuously graded ratio x. In some embodiments, the transition layer 324 has a thickness of 500 nm to 1050 nm. In some embodiments, the transition layer 324 is omitted.

[0036] Buffer layer 330 defines a high resistivity layer for increasing the breakdown voltage (e.g., up to about 650 volts) of the power HEMT 300. In some embodiments, buffer layer 330 includes one or more III-V compound layers. Examples of III-V compound layers include, but are not limited to, GaN, AlGaN, InGaN, and InAlGaN. In some embodiments, buffer layer 330 includes a dopant to achieve a predetermined high resistivity. In at least one embodiment, the dopant is a p-type dopant. In at least one embodiment, buffer layer 330 includes GaN doped with a p-type dopant. Examples of p-type dopant include, but are not limited to, C, Fe, Mg, and Zn. In at least one embodiment, the concentration of the p-type dopant in buffer layer 330 is greater than or equal to about 5 × 10⁻⁶. 18 ions / cm 3 In at least one embodiment, the buffer layer 330 has a thickness of 500 nm to 2000 nm.

[0037] The channel layer 340 has a lower resistivity than the buffer layer 330, thereby improving the current performance of the power HEMT300. In some embodiments, the channel layer 340 comprises one or more III-V compound layers. Examples of III-V compound layers include, but are not limited to, GaN, AlGaN, InGaN, and InAlGaN. In at least one embodiment, one or more of the III-V compound layers are doped. In one or more embodiments, the channel layer 340 comprises alternating p-type and n-type doped III-V compound layers. In at least one embodiment, the channel layer 340 comprises a p-type doped GaN layer. Examples of p-type dopants in the p-type doped GaN layer include, but are not limited to, C, Fe, Mg, and Zn. In at least one embodiment, the concentration of the p-type dopant in the channel layer 340 is lower than that in the buffer layer 330. For example, the concentration of the p-type dopant in the channel layer 340 is less than or equal to 1 × 10⁻⁶. 17 ions / cm 3 In at least one embodiment, the channel layer 340 has a thickness of 200 nm to 500 nm.

[0038] The active layer 350 includes one or more III-V compound layers that differ in composition from the III-V compound layers of the channel layer 340. In some embodiments, the active layer 350 includes AlN, Al y Ga (1-y)N (where y is the aluminum content ratio, 0 < y < 1) or a combination thereof. The active layer 350 is configured to form a two-dimensional electron gas (2DEG) in the channel layer 340 along the interface 341 between the channel layer 340 and the active layer 350. A heterojunction is formed between the active layer 350 and the channel layer 340 having two different semiconductor materials. There is a bandgap discontinuity between the active layer 350 and the channel layer 340. Electrons generated by the piezoelectric effect in the active layer 350 fall into the channel layer 340, and thus a thin layer 343 with highly mobile conductive electrons, i.e., 2DEG, is formed in the channel layer 340 and adjacent to the interface 341 between the channel layer 340 and the active layer 350. The electrons in the 2DEG are charge carriers in the channel layer 340. In some embodiments, when a sufficient voltage is applied to the gate electrode 380, it is possible to adjust the current flowing from the drain electrode 374 through the channel layer 340 to the source electrode 372 (i.e., the drain current).

[0039] The 2DEG is naturally generated at the interface 341 of different III-V compound materials forming the heterojunction between the channel layer 340 and the active layer 350. Due to the naturally generated 2DEG, the power HEMT 300 is conductive without applying a voltage to the gate electrode 380, i.e., in some embodiments, the semiconductor device 300 is a normally-on device (sometimes referred to as depletion mode).

[0040] In some embodiments, the power HEMT 300 can be converted into a normally-off device (sometimes referred to as enhancement mode). For example, the gate electrode 380 includes a gate structure configured to deplete the 2DEG below it, i.e., deplete the 2DEG in the region 344 below the depletion electrode 380, while leaving the 2DEG in the regions 345, 346 between (i) the gate electrode 380 and (ii) the source electrode 372 and the drain electrode 374 respectively. In at least one embodiment, the gate structure of the electrode 380 includes a p-doped layer above the active layer 350 and an n-doped layer above the p-doped layer. Example materials for the p-doped layer and / or the n-doped layer include but are not limited to GaN, AlGaN, InGaN, and InAlGaN. Example p-type dopants include but are not limited to carbon, iron, magnesium, and zinc. Example n-type dopants include but are not limited to silicon and oxygen. In at least one embodiment, the n-doped layer is omitted.

[0041] The optional blocking structure 360 includes at least one of a first blocking layer 362 and a second blocking layer 364. The first blocking layer 362 is formed between the transition structure 320 and the buffer layer 330. The first blocking layer 362 is configured to block the diffusion of the material of the substrate 310 into the buffer layer 330. The second blocking layer 364 is formed between the buffer layer 330 and the channel layer 340. The second blocking layer 364 is configured to block the diffusion of p-type dopants from the buffer layer 330 into the channel layer 340.

[0042] Next reference Figure 4 Component 400 can be implemented as a HEMT that can be used in the low-voltage circuit 160. Furthermore, component 400 can operate in enhancement mode. Therefore, component 400 is referred to hereinafter as "E-HEMT 400". E-HEMT 400 is substantially similar to power HEMT 300, but is configured to operate over a relatively low voltage range, for example, from about 6 volts to about 12 volts (or up to 40 volts). Therefore, the components of E-HEMT 400 will be briefly described below.

[0043] like Figure 4 As shown in the cross-sectional view, the E-HEMT 400 includes a substrate 410, a buffer layer 430 above the substrate 410, a channel layer 440 above the buffer layer 430, and an active layer 450 above the channel layer 440. The E-HEMT 400 also includes a source electrode 472 and a drain electrode 474 above the channel layer 440, and a gate electrode 480 above the active layer 450. In some embodiments, the source electrode 472 and the drain electrode 474 are formed above the active layer 450. Components 410, 430, 440, 450, 472, 474, and 480 are respectively associated with… Figure 3 The elements 310, 330, 340, 350, 372, 374 and 380 are basically similar, except that the gate electrode 480 also includes a p-doped layer or an n-doped layer (e.g., GaN) 492 located between the active layer 450 and the metal contact 490.

[0044] Next reference Figure 5 Component 500 can be implemented as a HEMT for use in low-voltage circuit 160. Furthermore, component 500 can operate in depletion mode. Therefore, component 500 is referred to hereinafter as "D-HEMT 500". D-HEMT 500 is substantially similar to power supply HEMT 300, but is configured to operate over a relatively low voltage range, for example, from about 6 volts to about 12 volts (or up to 40 volts). Therefore, the components of D-HEMT 500 will be briefly described below.

[0045] like Figure 5 As shown in the cross-sectional view, the D-HEMT 500 includes a substrate 510, a buffer layer 530 above the substrate 510, a channel layer 540 above the buffer layer 530, and an active layer 550 above the channel layer 540. The D-HEMT 500 also includes a source electrode 572 and a drain electrode 574 above the channel layer 540, and a gate electrode 580 above the active layer 550. In some embodiments, the source electrode 572 and the drain electrode 574 are formed above the active layer 550. Components 510, 530, 540, 550, 572, 574, and 580 are substantially similar to... Figure 3 The components are 310, 330, 340, 350, 372, 374 and 380.

[0046] Next reference Figure 6 Component 600 can be implemented as a HEMT structure that can be used in high-voltage circuit 110 and / or low-voltage circuit 160. Component 600 is substantially similar to power HEMT 300, but is configured to function as a two-terminal device, such as a resistor. Therefore, component 600 is referred to below as "HEMT resistor 600", and the components of HEMT resistor 600 will be briefly described below.

[0047] like Figure 6 As shown in the cross-sectional view, the HEMT resistor 600 includes a substrate 610, a buffer layer 630 above the substrate 610, a channel layer 640 above the buffer layer 630, and an active layer 650 above the channel layer 640. The HEMT resistor 600 also includes a first electrode 672 and a second electrode 674 located above the channel layer 640, which can serve as the two terminals of the HEMT resistor 600, respectively. In some embodiments, the first electrode 672 and the second electrode 674 are formed above the active layer 650. Elements 610, 630, 640, 650, 672, and 674 are substantially similar to... Figure 3 The components are 310, 330, 340, 350, 372 and 374.

[0048] In addition to GaN-based resistors (e.g., 600), the GaN-based integrated circuit 100 may also include several other types of resistors not formed of GaN-based materials. For example, the GaN-based integrated circuit 100 may include thin-film resistors formed of silicon-chromium (SiCr). Typically, such thin-film resistors have a SiCr thin film formed in a dielectric layer disposed on those HEMT structures. The two terminals of the SiCr thin film are respectively connected to two contacts / electrodes, which are the two terminals of the thin-film resistor.

[0049] Next reference Figure 7 Component 700 can be implemented as a HEMT structure that can be used in high-voltage circuit 110 and / or low-voltage circuit 160. Component 700 is substantially similar to power HEMT 300, but is configured to operate as a two-terminal device, for example, a capacitor. Therefore, component 700 is referred to below as "HEMT capacitor 700", and the components of HEMT capacitor 700 will be briefly described below.

[0050] like Figure 7As shown in the cross-sectional view, the HEMT capacitor 700 includes a substrate 710, a buffer layer 730 above the substrate 710, a channel layer 740 above the buffer layer 730, and an active layer 750 above the channel layer 740. The HEMT capacitor 700 also includes a source electrode 772 and a drain electrode 774 above the channel layer 740, and a gate electrode 780 above the active layer 750. In some embodiments, the source electrode 772 and the drain electrode 774 are formed above the active layer 750. The source electrode 772 and the drain electrode 774 may be shorted together, and the source electrode 772 and the drain electrode 774 serve as a first terminal of the HEMT capacitor 700, while the gate electrode 780 serves as a second terminal of the HEMT capacitor 700. Components 710, 730, 740, 750, 772, 774, and 780 are substantially similar to... Figure 3 Components 310, 330, 340, 350, 372, 374 and 380.

[0051] Besides GaN-based capacitors (e.g., 700), the GaN-based integrated circuit 100 can also include many other types of capacitors not formed of GaN-based materials. For example, the GaN-based integrated circuit 100 can include metal-insulator-metal (MIM) capacitors disposed above those HEMT structures. Typically, a MIM capacitor includes a first interconnect (e.g., metal) structure and a second interconnect (e.g., metal) structure, with a dielectric layer between them. The first interconnect structure and the second interconnect structure can each serve as a terminal of the MIM capacitor.

[0052] Next reference Figure 8 Component 800 can be implemented as a HEMT structure that can be used in high-voltage circuit 110 and / or low-voltage circuit 160. Component 800 is substantially similar to power HEMT 300, but configured to operate as a two-terminal device, such as a diode. Therefore, component 800 is referred to below as "HEMT diode 800", and the components of HEMT diode 800 will be briefly described below.

[0053] like Figure 8As shown in the cross-sectional view, the HEMT diode 800 includes a substrate 810, a buffer layer 830 above the substrate 810, a channel layer 840 above the buffer layer 830, and an active layer 850 above the channel layer 840. The HEMT diode 800 also includes a source electrode 872 and a drain electrode 874 above the channel layer 840, and a gate electrode 880 above the active layer 850. In some embodiments, the source electrode 872 and the drain electrode 874 are formed above the active layer 850. The source electrode 872 and the gate electrode 880 may be shorted together, and the source electrode 872 and the gate electrode 880 together serve as a first terminal (e.g., anode) of the HEMT diode 800, while the drain electrode 874 serves as a second terminal (e.g., cathode) of the HEMT diode 800. Elements 810, 830, 840, 850, 872, 874, and 880 are substantially similar to... Figure 3 The components are 310, 330, 340, 350, 372, 374 and 380.

[0054] Figure 9 , Figure 10 and Figure 11 Example circuit diagrams 900, 1000, and 1100 are shown respectively of the ESD protection circuit 260, control circuit 262, and drive circuit 264 in the low-voltage circuit 160 of the GaN-based integrated circuit 100 according to various embodiments. It should be understood that... Figure 9 - Figure 11 The circuit diagrams shown are provided for illustrative purposes only and are not intended to limit the scope of this disclosure. Therefore, each circuit of the low-voltage circuit 160 can be implemented as any of a variety of other circuit arrangements while remaining within the scope of this disclosure.

[0055] exist Figure 9 In the example circuit diagram 900, the ESD protection circuit 260 may include a plurality of GaN-based gate-source shorted transistors 902, GaN-based or non-GaN-based resistors 904, and GaN-based shunt transistors 906 connected in series. In some embodiments, the high side of the ESD protection circuit 260 is operably (e.g., electrically) connected between terminal 102-2 and the next stage (e.g., control circuit 262) of the circuit, and the low side of the ESD protection circuit 260 is operably (e.g., electrically) connected to terminal 102-4.

[0056] exist Figure 10In the example circuit diagram 1000, the control circuit 262 may include a plurality of GaN-based transistors 1002 and 1004, as shown, which are operatively (e.g., electrically) connected to each other and also between a first supply voltage (e.g., VDD) and a second supply voltage (e.g., VSS). Transistor 1002 may have a first conductivity type (e.g., p-type) or a first operating mode (e.g., depletion mode), and transistor 1004 may have a second conductivity type (e.g., n-type) or a second operating mode (e.g., enhancement mode), thus forming the control circuit 262 as a complementary logic circuit. However, it should be understood that the control circuit 262 may be constructed as a resistor-transistor logic circuit (where, for example, the p-type transistor is formed by a HEMT resistor, and the n-type transistor is formed by a p-GaN-gated HEMT), while remaining within the scope of this disclosure. In some embodiments, the first supply voltage and the second supply voltage may be received via terminals 102-12 and 102-4, respectively. In some embodiments, the control circuit 262 may have an input terminal connected to terminal 102-2 (which can receive command signals) and an output terminal connected to a circuit in the next stage (e.g., drive circuit 264). The control circuit 262 may, for example, output a clock signal to the drive circuit 264.

[0057] exist Figure 11 In the example circuit diagram 1100, the driving circuit 264 may include a plurality of GaN-based transistors 1102 and 1104, as shown, which are operatively (e.g., electrically) connected to each other and also between a first supply voltage (e.g., VDD) and a second supply voltage (e.g., VSS). Transistor 1102 may have a first conductivity type (e.g., p-type) or a first operating mode (e.g., depletion mode), and transistor 1104 may have a second conductivity type (e.g., n-type) or a second operating mode (e.g., enhancement mode), thus forming the driving circuit 264 as a complementary logic circuit. However, it should be understood that the driving circuit 264 may be constructed as a resistor-transistor logic circuit (where, for example, the p-type transistor is formed by a HEMT resistor, and the n-type transistor is formed by a p-GaN-gated HEMT), while remaining within the scope of this disclosure. In some embodiments, the first supply voltage and the second supply voltage may be received via terminals 102-10 and 102-5, respectively. The driving circuit 264 may also include one or more GaN-based or non-GaN-based capacitors 1106. In some embodiments, the drive circuit 264 may have an input terminal connected to the control circuit 262 and an output terminal connected to a next-stage circuit (e.g., power transistor 210). The drive circuit 264 may provide a gate signal to the power transistor 210.

[0058] Now for reference Figure 12 This document depicts a flowchart of an example method 1200 for identifying various defects in a disclosed GaN-based integrated circuit 100, according to various embodiments. As disclosed herein, the GaN-based integrated circuit 100 includes a plurality of spaced terminals (e.g., 102-1 to 102-12), thereby enabling method 1200 to detect, test, screen, or otherwise identify various (e.g., growth) defects in the GaN-based integrated circuit 100 at the circuit level. Therefore, Figure 12 The following discussion will incorporate some of the diagrams above (e.g., Figure 2 The method is performed on a GaN-based integrated circuit 100. The illustrated embodiment of method 1200 is merely an example. Therefore, it should be understood that any of a variety of operations may be omitted, reordered, and / or added while remaining within the scope of this disclosure.

[0059] In short, method 1200 begins with operation 1202 providing a GaN-based integrated circuit including at least one high-voltage circuit and at least one low-voltage circuit. The high-voltage circuit and the low-voltage circuit are operatively connected to each other. Furthermore, the high-voltage circuit includes a plurality of first GaN-based components operating in a first voltage range, and the low-voltage circuit includes a plurality of second GaN-based components operating in a second voltage range, wherein the first voltage range is significantly higher than the second voltage range. Next, method 1200 proceeds to operation 1204, applying a plurality of first test signals to the high-voltage circuit via a plurality of first test terminals connected to the integrated circuit of the high-voltage circuit. Simultaneously or separately from operation 1204, method 1200 proceeds to operation 1206, applying a plurality of second test signals to the low-voltage circuit via a plurality of second test terminals connected to the integrated circuit of the low-voltage circuit. In various embodiments, the first test signals are configured independently of the second test signals.

[0060] Figure 13 A set of first test signals and a set of second test signals, according to various embodiments, are shown being applied respectively to high-voltage circuit 110 and low-voltage circuit 160 to identify epitaxial defects. Such epitaxial defects can be present in any GaN-based component of high-voltage circuit 110 and low-voltage circuit 160. For example, such epitaxial defects can be global defects (e.g., due to screw dislocations, grain boundaries, strain, etc.) in one or more GaN-based layers throughout the substrate. Figure 3 As a representative example, component 300 (implementation of power transistor 210) can have such epitaxial defects in any of layers 322 to 350, or at their corresponding interfaces with adjacent layers.

[0061] As shown, a first test signal applied to the high-voltage circuit 110 via terminals 102-6 to 102-9, and a second test signal applied to the low-voltage circuit 160 via terminals 102-1 to 102-5 and terminals 102-10 to 102-12, are configured at relatively high voltage levels (e.g., within the operating voltage range of the high-voltage circuit 110), except for terminal 102-7 connected to the substrate, which is connected to ground. Since all terminals except substrate terminal 102-7 are connected to such high stress voltages, any epitaxial defects can be identified in response to the detection of a sudden voltage drop at any of these terminals. This is because such global epitaxial defects typically cause additional leakage in GaN-based components (e.g., HEMTs). Furthermore, since terminal 102-6 is operatively isolated from terminals 102-4 or 102-5, and terminal 102-9 is specifically connected to the gate of the power transistor 210, damage to the gates of other circuits (due to the connection) can be advantageously prevented.

[0062] Figure 14 Another set of first test signals and another set of second test signals, according to various embodiments, are shown being applied separately to high-voltage circuit 110 and low-voltage circuit 160 to identify surface crystal defects. Such surface crystal defects can be present in any GaN-based component of high-voltage circuit 110. For example, such surface crystal defects can be localized defects (e.g., due to contamination, irregular growth, etc.) along the top surface of one or more GaN-based layers of power transistor 210. Figure 3 As a representative example, component 300 (an embodiment of power transistor 210) can exhibit surface crystal defects along any one of the top layers 322 to 350.

[0063] As shown in the figure, the first test signal applied to the high-voltage circuit 110 through terminals 102-6, 102-8, and 102-9 is ground voltage, a first voltage scan (e.g., from 0 volts to 650 volts), and a second voltage scan (e.g., from 0 volts to 6 volts); and the second test signal applied to the low-voltage circuit 160 through terminals 102-1 to 102-5 and terminals 102-10 to 102-12 is configured as a floating voltage, while terminal 102-7 connected to the substrate is connected to ground voltage. In the example where the power transistor 210 is formed as n-type, the signal applied to terminal 102-9 can scan from 6 volts to 0 volts (from turning on to turning off the power transistor 210), while the signal applied to terminal 102-8 also scans from 0 volts to 650 volts. Specifically, when the power transistor 210 is turned on, its on-resistance is expected to be small. However, when surface crystal defects are present, such a small on-resistance may become irregularly large. On the other hand, when the power transistor 210 is turned off, the voltage level that its drain can withstand is expected to be large. However, when surface crystal defects exist that interfere with the electric field distribution along the GaN-based layer, the breakdown voltage at the drain of the power transistor 210 may irregularly decrease. Furthermore, since the terminals (102-1 to 102-5 and 102-10 to 102-12) connected to the low-voltage circuit 110 are operatively isolated from and floated with the terminals (102-6 to 102-9) connected to the high-voltage circuit 160, damage to the low-voltage circuit 110 can be advantageously prevented.

[0064] Figure 15 Another set of first test signals and another set of second test signals, according to various embodiments, are applied to high-voltage circuit 110 and low-voltage circuit 160 respectively to identify defects present in the gate of the HEMT of integrated circuit 100. Such gate defects can be localized defects around the gate of power transistor 210 (e.g., due to contamination, irregular growth, etc.). Figure 3 As a representative example, component 300 (implementation of power transistor 210) can have such gate defects at the interface between gate electrode 380 and active layer 350, or in active layer 350.

[0065] As shown in the figure, the first test signals applied to the high-voltage circuit 110 through terminals 102-6, 102-8, and 102-9 are respectively a first voltage significantly higher than 0 volts (e.g., about 8 volts), a second voltage close to 0 volts (e.g., about 0.1 volts), and a ground voltage; and the second test signals applied to the low-voltage circuit 160 through terminals 102-1 to 102-5 and terminals 102-10 to 102-12 are all configured as floating voltages, while terminal 102-7 connected to the substrate is connected to the ground voltage. In the example where the power transistor 210 is formed as n-type, the signal applied to terminal 102-6 (source) is significantly higher than the signal applied to terminal 102-9 (gate), which can still identify whether there is leakage between the source and the gate (e.g., due to gate defects) while preventing damage to the low-voltage circuit 160. More specifically, with the terminals (102-1 to 102-5 and 102-10 to 102-12) connected to the low-voltage circuit 110 operatively isolated from and floating with the terminal (102-9) connected to the gate of the power transistor 210, if leakage current is present, the leakage current can only be conducted from terminal 102-6 to terminal 102-9. In other words, this leakage current is away from the low-voltage circuit 160.

[0066] Figure 16 Another set of first test signals and another set of second test signals are shown, respectively applied to the high-voltage circuit 110 and the low-voltage circuit 160 according to various embodiments to identify faults in the ESD protection circuit 260 of the low-voltage circuit 160 of the integrated circuit 100.

[0067] As shown in the figure, the first test signals applied to the high-voltage circuit 110 via terminals 102-6, 102-8, and 102-9 are all configured as floating voltages; the second test signals applied to the ESD protection circuit 260 via terminals 102-3 and 102-4 are a functional signal (e.g., a functional voltage) and a ground voltage, respectively; and the second test signals applied to other circuits of the low-voltage circuit 160 via terminals 102-1 to 102-2, 102-5, and 102-10 to 102-12 are all configured as floating voltages, while terminal 102-7 connected to the substrate is connected to the ground voltage. In some embodiments, the functional signal (received via terminal 102-3) may include any of a variety of signals corresponding to the function of the ESD protection circuit 260. For example, the functional signal may be used as an excitation signal for the ESD protection circuit 260, so that when the ESD protection circuit 260 receives such an excitation signal, the ESD protection circuit 260 may provide a corresponding response, for example, at its output terminal or internal node. By examining the response signals, it can be determined whether the ESD protection circuit 260 itself is functioning as intended. Specific functional signals may include pulse voltages, wave signals, etc. By making the corresponding test terminals of the low-voltage circuit 160 available, each circuit of the low-voltage circuit 160 can be tested individually, and the root cause of any fault in the entire integrated circuit 100 can be effectively identified.

[0068] Figure 17 Another set of first test signals and another set of second test signals are shown, respectively applied to the high-voltage circuit 110 and the low-voltage circuit 160 according to various embodiments to identify faults in the control circuit 262 of the low-voltage circuit 160 of the integrated circuit 100.

[0069] As shown, the first test signals applied to the high-voltage circuit 110 via terminals 102-6, 102-8, and 102-9 are all configured as floating voltages; the second test signals applied to the control circuit 262 via terminals 102-2, 102-4, and 102-12 are respectively a functional signal (e.g., a functional voltage), a ground voltage, and a power supply voltage (e.g., approximately 6 volts according to the design of the control circuit 262); and the second test signals applied to other circuits of the low-voltage circuit 160 via terminals 102-1 to 102-3, 102-5, and 102-10 to 102-11 are all configured as floating voltages, while terminal 102-7 connected to the substrate is connected to the ground voltage. In some embodiments, the functional signal (received via terminal 102-2) may include any of a variety of signals corresponding to the function of the control circuit 262. For example, the functional signal may be used as an excitation signal for the control circuit 262, so that when the control circuit 262 receives such an excitation signal, the control circuit 262 may provide a corresponding response, for example, at its output terminal or internal node. By examining the response signals, it can be determined whether the control circuit 262 itself is functioning as intended. Specific functional signals may include pulse voltages, wave signals, etc. By making the corresponding test terminals of the low-voltage circuit 160 available, each circuit of the low-voltage circuit 160 can be tested individually, and the root cause of any fault in the entire integrated circuit 100 can be effectively identified.

[0070] Figure 18 Another set of first test signals and another set of second test signals are shown, respectively applied to the high-voltage circuit 110 and the low-voltage circuit 160 according to various embodiments to identify a fault in the drive circuit 264 of the low-voltage circuit 160 of the integrated circuit 100.

[0071] As shown, the first test signals applied to the high-voltage circuit 110 via terminals 102-6, 102-8, and 102-9 are all configured as floating voltages; the second test signals applied to the drive circuit 264 via terminals 102-11, 102-5, and 102-10 are respectively a functional signal (e.g., a functional voltage), a ground voltage, and a power supply voltage (e.g., approximately 6 volts, depending on the design of the drive circuit 264); and the second test signals applied to other circuits of the low-voltage circuit 160 via terminals 102-1 to 102-4 and 102-12 are all configured as floating voltages, while terminal 102-7 connected to the substrate terminal is connected to the ground voltage. In some embodiments, the functional signal (received via terminal 102-11) may include any of a variety of signals corresponding to the function of the drive circuit 264. For example, the functional signal may be used as an excitation signal for the drive circuit 264, so that when the drive circuit 264 receives such an excitation signal, the drive circuit 264 may provide a corresponding response, for example, at its output terminal or at an internal node. By examining the response signals, it can be determined whether the control circuit 262 itself is functioning as intended. Specific functional signals may include pulse voltages, wave signals, etc. By making the corresponding test terminals of the low-voltage circuit 160 available, each circuit of the low-voltage circuit 160 can be tested individually, and the root cause of any fault in the entire integrated circuit 100 can be effectively identified.

[0072] Figure 19 A simplified block diagram of a test system 1900, according to various embodiments, capable of identifying various defects and / or faults in GaN-based integrated circuits, is shown. Such a GaN-based integrated circuit under test may at least include low-voltage and high-voltage circuits monolithically integrated together. Furthermore, the high-voltage and low-voltage circuits of the GaN-based integrated circuit have a corresponding number of operably isolated test terminals, which allows the test system 1900 to independently configure the test signals for the low-voltage and high-voltage circuits.

[0073] As shown, the test system 1900 includes at least a controller 1910 and a signal generator 1920 operatively connected to each other. Although shown as separate blocks, the signal generator 1920 can be integrated into the controller 1910 while remaining within the scope of this disclosure. In various embodiments, the controller 1910 can determine a first set of test signals and a second set of test signals for the low-voltage and high-voltage circuits of the GaN-based integrated circuit 1950 under test, respectively, placed on the support 1960. Since the high-voltage and low-voltage circuits of the GaN-based integrated circuit 1950 have corresponding test terminals that are isolated from each other (e.g., GaN-based integrated circuit 100), the controller 1910 can independently configure the first set of test signals and the second set of test signals. In configuring the first and second sets of test signals, the signal generator 1920 can apply those test signals to the GaN-based integrated circuit 1950 to identify defects and / or faults in the GaN-based integrated circuit 1950.

[0074] The test system 1900 may also include a probe card 1930 configured to support probe 1940. In operation, probe card 1930 is moved until probe 1940 contacts a specific location on the GaN-based integrated circuit 1950. The movement is... Figure 19 The vertical arrows indicate this. Alignment devices, such as microscopes or visual display devices with magnification, can be used to move the wafer in the X and Y directions to place probes 1940 onto one or more test terminals of, for example, a GaN-based integrated circuit 1950. After probes 1940 are placed in electrical contact with the test terminals, a first and second set of test signals, as described above, can be applied to the GaN-based integrated circuit 1950 to identify defects and / or faults. Although not shown, the test system 1900 may include multiple (e.g., voltage and / or current) monitors to monitor the response of the GaN-based integrated circuit 1950 after those test signals have been applied. The monitors can be electrically contacted with the GaN-based integrated circuit 1950 through terminals that are the same as or different from the test terminals on which the test signals are applied.

[0075] In one aspect of this disclosure, an integrated circuit is disclosed. The integrated circuit includes a first circuit formed based on one or more III-V compound materials, configured to operate within a first voltage range. The integrated circuit includes a second circuit, also formed based on one or more III-V compound materials, operatively connected to the first circuit and configured to operate within a second voltage range, wherein the second voltage range is significantly higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and the set of second test terminals are independent of each other.

[0076] In some embodiments, the one or more III-V compound materials include gallium nitride.

[0077] In some embodiments, the set of first test terminals are operably connected to the gate, drain, and source of at least one of a plurality of first transistors in the first circuit, and the set of second test terminals are operably connected to the gate, drain, and source of at least one of a plurality of second transistors in the second circuit.

[0078] In some embodiments, the test signals applied to the set of first test terminals respectively include a first signal, a second signal, and a third signal, wherein the first signal, the second signal, and the third signal are all first fixed voltages within the second voltage range, and the test signals applied to the set of second test terminals respectively include a fourth signal, a fifth signal, and a sixth signal, wherein the fourth signal, the fifth signal, and the sixth signal are all second fixed voltages within the second voltage range.

[0079] In some embodiments, the test signal applied to the set of first test terminals and the set of second test terminals is configured to identify epitaxial defects in at least one of the first circuit and the second circuit.

[0080] In some embodiments, the test signals applied to the set of first test terminals respectively include a seventh signal, an eighth signal, and a ninth signal, all of which are floating voltages, and the test signals applied to the set of second test terminals respectively include a tenth signal, an eleventh signal, and a twelfth signal, wherein the tenth signal, the eleventh signal, and the twelfth signal are respectively a first voltage scan, a second voltage scan, and a ground voltage.

[0081] In some embodiments, the test signal applied to the set of first test terminals and the set of second test terminals is configured to identify surface crystal defects in the second circuit.

[0082] In some embodiments, the test signals applied to the set of first test terminals respectively include a thirteenth signal, a fourteenth signal, and a fifteenth signal, all of which are floating voltages, and the test signals applied to the set of second test terminals respectively include a sixteenth signal, a seventeenth signal, and an eighteenth signal, wherein the sixteenth signal, the seventeenth signal, and the eighteenth signal are ground voltage, a third fixed voltage, and a fourth fixed voltage, wherein the fourth fixed voltage is significantly higher than the ground voltage.

[0083] In some embodiments, the test signal applied to the set of first test terminals and the set of second test terminals is configured to test the gate of at least one of the second transistors in the second circuit.

[0084] In some embodiments, the test signals applied to the set of first test terminals include a nineteenth signal, a twentieth signal, and a twenty-first signal, wherein the nineteenth signal, the twentieth signal, and the twenty-first signal are a functional voltage, a fifth fixed voltage, and a ground voltage, respectively, and the test signals applied to the set of second test terminals include a twenty-second signal, a twenty-third signal, and a twenty-fourth signal, all of which are floating voltages.

[0085] In some embodiments, the test signal applied to the set of first test terminals and the set of second test terminals is configured to test the functionality of the first circuit.

[0086] In another aspect of this disclosure, a method for testing an integrated circuit is disclosed. The method includes providing an integrated circuit comprising a first circuit and a second circuit operatively connected to each other. The first circuit includes at least a first transistor operating in a first voltage range, and the second circuit includes at least a second transistor operating in a second voltage range. The second voltage range is significantly higher than the first voltage range. The method includes applying a plurality of first test signals to the first transistor through a plurality of first test terminals of the integrated circuit. The method includes applying a plurality of second test signals to the second transistor through a plurality of second test terminals of the integrated circuit. The plurality of first test signals are configured independently of the plurality of second test signals.

[0087] In some embodiments, each of the first transistor and the second transistor includes an active channel formed in one or more III-V compound materials.

[0088] In some embodiments, the method further includes: applying all of the plurality of first test signals and the plurality of second test signals as fixed voltages within the second voltage range to identify epitaxial defects in at least one of the first circuit and the second circuit.

[0089] In some embodiments, the method further includes: applying the plurality of first test signals as floating voltages and applying the plurality of second test signals as a first voltage scan, a second voltage scan, and a ground voltage, respectively, to identify surface crystal defects in the second circuit.

[0090] In some embodiments, the method further includes: applying the plurality of first test signals as floating voltages and applying the plurality of second test signals as ground voltage, near-ground voltage, and fixed voltage significantly higher than the ground voltage, respectively, to test the gate of the second transistor.

[0091] In some embodiments, the method further includes: applying the plurality of first test signals, which are respectively a functional voltage, a power supply voltage, and a ground voltage, and applying the plurality of second test signals, which are all floating voltages, to test the function of the first circuit.

[0092] In some embodiments, the plurality of first test terminals and the plurality of second test terminals are operatively isolated from each other.

[0093] In another aspect of this disclosure, a test system is disclosed. The test system includes a signal generator configured to: apply a plurality of first test signals to a first transistor of an integrated circuit via a plurality of first test terminals of the integrated circuit, wherein the first transistor comprises gallium nitride and is configured to operate within a first voltage range; and apply a plurality of second test signals to a second transistor of the integrated circuit via a plurality of second test terminals of the integrated circuit, wherein the second transistor comprises gallium nitride and is configured to operate within a second voltage range significantly higher than the first voltage range. The test system includes a controller operatively connected to the signal generator and configured to determine the plurality of first test signals independently of the plurality of second test signals.

[0094] In some embodiments, the plurality of first test terminals and the plurality of second test terminals are operatively isolated from each other.

[0095] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0096] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: A first circuit, formed based on one or more III-V compound materials, is configured to operate within a first voltage range; The second circuit includes a transistor formed based on one or more III-V compound materials, operatively connected to the first circuit and configured to operate in a second voltage range, wherein the second voltage range is significantly higher than the first voltage range; A set of first test terminals is connected to the first circuit; and A set of second test terminals is connected to the transistor of the second circuit; The test signals applied to the set of first test terminals and the set of second test terminals are independent of each other, and at least one second test terminal connected to the transistor is used to apply a voltage within the second voltage range to the transistor.

2. The integrated circuit according to claim 1, wherein, The one or more III-V compound materials include gallium nitride.

3. The integrated circuit according to claim 1, wherein, The transistor is a second transistor, and the set of first test terminals are operably connected to the gate, drain and source of at least one of the plurality of first transistors in the first circuit, and the set of second test terminals are operably connected to the gate, drain and source of at least one of the plurality of second transistors in the second circuit.

4. The integrated circuit according to claim 3, wherein, The test signals applied to the set of first test terminals include a first signal, a second signal, and a third signal, wherein the first signal, the second signal, and the third signal are all first fixed voltages within the second voltage range. The test signals applied to the set of second test terminals include a fourth signal, a fifth signal, and a sixth signal, wherein the fourth signal, the fifth signal, and the sixth signal are all second fixed voltages within the second voltage range.

5. The integrated circuit according to claim 4, wherein, The test signals applied to the set of first test terminals and the set of second test terminals are configured to identify epitaxial defects in at least one of the first circuit and the second circuit.

6. The integrated circuit according to claim 3, wherein, The test signals applied to the first set of test terminals include a seventh signal, an eighth signal, and a ninth signal, all of which are floating voltages. The test signals applied to the second set of test terminals include a tenth signal, an eleventh signal, and a twelfth signal, wherein the tenth signal, the eleventh signal, and the twelfth signal are respectively a first voltage scan, a second voltage scan, and a ground voltage.

7. The integrated circuit according to claim 6, wherein, The test signals applied to the set of first test terminals and the set of second test terminals are configured to identify surface crystal defects in the second circuit.

8. The integrated circuit according to claim 3, wherein, The test signals applied to the first set of test terminals include the thirteenth, fourteenth, and fifteenth signals, all of which are floating voltages. The test signals applied to the second set of test terminals include the sixteenth, seventeenth, and eighteenth signals. The sixteenth, seventeenth, and eighteenth signals are ground voltage, a third fixed voltage, and a fourth fixed voltage, respectively, wherein the fourth fixed voltage is significantly higher than the ground voltage.

9. The integrated circuit according to claim 1, wherein, The transistor is a second transistor, and the test signal applied to the set of first test terminals and the set of second test terminals is configured to test the gate of at least one of the second transistors in the second circuit.

10. The integrated circuit according to claim 1, wherein, The test signals applied to the first set of test terminals include the nineteenth signal, the twentieth signal, and the twenty-first signal, wherein the nineteenth signal, the twentieth signal, and the twenty-first signal are a functional voltage, a fifth fixed voltage, and a ground voltage, respectively. The test signals applied to the second set of test terminals include the twenty-second signal, the twenty-third signal, and the twenty-fourth signal, which are all floating voltages.

11. The integrated circuit according to claim 10, wherein, The test signal applied to the set of first test terminals and the set of second test terminals is configured to test the function of the first circuit.

12. A method for testing integrated circuits, comprising: An integrated circuit is provided, the integrated circuit including a first circuit and a second circuit operatively connected to each other, wherein the first circuit includes at least a first transistor operating in a first voltage range, and the second circuit includes at least a second transistor operating in a second voltage range and formed based on one or more III-V compound materials, and the second voltage range is significantly higher than the first voltage range; Multiple first test signals are applied to the first transistor through multiple first test terminals of the integrated circuit; and Multiple second test signals are applied to the second transistor through multiple second test terminals of the integrated circuit; The plurality of first test signals are configured independently of the plurality of second test signals, and at least one second test signal applied to the second transistor is a voltage within the second voltage range.

13. The method according to claim 12, wherein, Each of the first transistor and the second transistor includes an active channel formed in one or more III-V compound materials.

14. The method of claim 12, further comprising: All of the plurality of first test signals and the plurality of second test signals are applied as fixed voltages within the second voltage range to identify epitaxial defects in at least one of the first circuit and the second circuit.

15. The method of claim 12, further comprising: The plurality of first test signals are applied as floating voltages and the plurality of second test signals are applied as first voltage scan, second voltage scan and ground voltage, respectively, to identify surface crystal defects in the second circuit.

16. The method of claim 12, further comprising: The gate of the second transistor is tested by applying the plurality of first test signals as floating voltages and applying the plurality of second test signals as ground voltage, near-ground voltage, and fixed voltage significantly higher than the ground voltage, respectively.

17. The method of claim 12, further comprising: The first circuit is tested by applying the plurality of first test signals, which are respectively function voltage, power supply voltage and ground voltage, and the plurality of second test signals, which are all floating voltages.

18. The method according to claim 12, wherein, The plurality of first test terminals and the plurality of second test terminals are operatively isolated from each other.

19. A test system for testing integrated circuits, comprising: A signal generator is configured to: apply a plurality of first test signals to a first transistor of an integrated circuit via a plurality of first test terminals of the integrated circuit, wherein the first transistor comprises gallium nitride and is configured to operate within a first voltage range; and apply a plurality of second test signals to a second transistor of the integrated circuit via a plurality of second test terminals of the integrated circuit, wherein the second transistor comprises gallium nitride and is configured to operate within a second voltage range, the second voltage range being significantly higher than the first voltage range, and at least one second test signal applied to the second transistor being a voltage within the second voltage range; and A controller is operatively connected to the signal generator and configured to determine the plurality of first test signals, independent of the plurality of second test signals.

20. The testing system according to claim 19, wherein, The plurality of first test terminals and the plurality of second test terminals are operatively isolated from each other.

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