An FPGA placement and routing method based on sparse technology
By abstracting the internal hardware modules of an FPGA into software modules and using sparse routing techniques, the signal congestion problem caused by insufficient internal wire network resources of the FPGA is solved, thereby improving chip performance and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI XINLU TECH CO LTD
- Filing Date
- 2022-12-07
- Publication Date
- 2026-05-29
AI Technical Summary
In the existing technology, insufficient internal net resources of FPGAs lead to signal congestion, which causes placement and routing tools to be unable to complete their tasks or to fail to meet design requirements. In addition, excess routing resources waste chip area and cost.
By employing sparse technology, the internal hardware modules of the FPGA are abstracted into software modules with electrical ports. The sparse properties and sparse rules are used for routing, and the signal congestion problem is solved through iterative judgment and sparsification processing, thereby reducing the use of routing resources.
Without increasing physical wiring resources, it improves chip performance and computing power, reduces hardware costs and layout and wiring burden, and solves signal congestion problems.
Smart Images
Figure CN115859884B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of FPGA placement and routing technology, and in particular to an FPGA placement and routing method based on sparse technology. Background Technology
[0002] FPGA (Field Programmable Gate Array) is a product of further development based on programmable devices such as PAL (Programmable Array Logic) and GAL (General Purpose Array Logic).
[0003] Currently, FPGA hardware architectures require a large number of net resources. During use, net resources are used to connect the various physical nodes within the FPGA and ensure that the delays between nodes meet the constraints. However, insufficient net resources can easily lead to signal congestion. In severe cases, placement and routing tools may be unable to connect the various physical nodes according to the delay constraints, resulting in performance that fails to meet design requirements. When the congestion problem is more severe, the placement and routing tools may even be unable to complete the routing task, making it impossible to achieve the full functionality of the design.
[0004] In applications such as artificial intelligence and image processing, massive amounts of data processing are required. During processing, data is distributed across one or more DSPs, RAMs, or other hardware resources within an FPGA. Assuming the data source used for AI computation is 16-bit encoded, after one integer multiplication operation by the DSP, the output becomes 32 bits. If the result is accumulated multiple times, the data encoding needs to exceed 32 bits or even more. Typically, each data bit or each byte requires corresponding wiring resources, resulting in a large amount of wiring around the DSP and RAM in these applications. In existing technologies, to meet performance requirements, the wiring resources within the FPGA often need to reserve sufficient margin, leading to increased chip area and cost. Furthermore, these excess wiring resources are often unused in most application scenarios, wasting chip area.
[0005] Therefore, it is necessary to provide an FPGA placement and routing method based on sparse technology to solve the problem of signal congestion caused by insufficient wire resources in the existing technology. Summary of the Invention
[0006] The purpose of this invention is to provide an FPGA placement and routing method based on sparse technology to solve the problem of signal congestion caused by insufficient wire network resources in the prior art.
[0007] To address the problems existing in the prior art, this invention provides an FPGA placement and routing method based on sparse technology, comprising the following steps:
[0008] The internal hardware modules of the FPGA are abstracted into software modules with electrical ports, and each software module has corresponding attributes. Some software modules have attributes including sparsity and its sparsity rules.
[0009] Read the fully connected netlist;
[0010] Perform full-connectivity layout and routing based on the fully connected netlist and the software module;
[0011] Determine if the routing meets the requirements. If the routing requirements are met, complete the routing and output the hardware netlist.
[0012] If the routing requirements are not met, return to the fully connected placement and routing step if the iteration is not finished; if the routing requirements are not met, determine whether the corresponding software module has the property of being sparse if the iteration is finished; if it does not have the property of being sparse, report an exception and exit.
[0013] If the property is sparse, then perform sparsification and sparse routing, and check again whether the routing meets the requirements. If the routing requirements are met, then complete the routing and output the hardware netlist. If the routing requirements are not met, return to the sparsification and sparse routing steps if the iteration is not over, and exit if the iteration is over.
[0014] Optionally, in the FPGA placement and routing method based on sparse technology,
[0015] The sparsity rules include, but are not limited to: prioritizing high-order bits, randomizing bit sparsity, disallowing sparsity for specific bits, and / or setting default values for sparsity bits.
[0016] Optionally, in the FPGA placement and routing method based on sparse technology, the sparse bits are defaulted to 0, 1, or random values.
[0017] Optionally, in the FPGA placement and routing method based on sparse technology, the attributes are described according to software tools and hardware functions.
[0018] Optionally, in the FPGA placement and routing method based on sparse technology, the attributes also include the input / output direction and driving capability of the port.
[0019] Optionally, the FPGA placement and routing method based on sparse technology further includes the following steps:
[0020] Record the sparsed connection signals and output them to the runtime log or a report in a specific format;
[0021] Performance evaluation is performed based on runtime logs or reports in a specific format.
[0022] Optionally, in the FPGA placement and routing method based on sparse technology, the performance evaluation method is as follows:
[0023] Based on the sparsification results in the operation log or a report in a specific format, locate the source and receiver ends of the signal connection, and perform a qualitative evaluation of the sparsification results.
[0024] Optionally, the FPGA placement and routing method based on sparse technology further includes the following steps:
[0025] Quantitative analysis is performed based on the sparsification results and / or the hardware netlist generated after sparsification.
[0026] Optionally, in the FPGA placement and routing method based on sparse technology, the quantitative analysis is performed as follows:
[0027] Simulations are performed based on the hardware netlist generated after sparsification, and quantitative analysis is conducted on the sparsed routing results.
[0028] Optionally, in the FPGA placement and routing method based on sparse technology, the method switches to sparse routing mode when performing sparsification processing and sparse routing.
[0029] In the FPGA placement and routing method based on sparse technology provided in this invention, without increasing physical routing resources, the performance or computing power of the chip can be significantly improved by developing the sparsity and sparsity rules of each software module. This allows for a significant reduction in the use of routing resources in applications such as AI computing or image processing. It effectively solves the problem of signal congestion caused by insufficient network resources in existing technologies, and also reduces hardware costs and the burden of placement and routing. Attached Figure Description
[0030] Figure 1 A flowchart of an FPGA placement and routing method provided in an embodiment of the present invention. Detailed Implementation
[0031] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0032] Furthermore, in the following text, the terms "first," "second," etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be substituted where appropriate. Similarly, if the methods described herein comprise a series of steps, the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0033] In existing technologies, to meet performance requirements, FPGA internal wiring resources often need to reserve sufficient margin, resulting in increased chip area and cost. Furthermore, these excess wiring resources are often unused in most application scenarios, wasting chip area.
[0034] Therefore, it is necessary to provide an FPGA placement and routing method based on sparse technology, such as... Figure 1 As shown, the FPGA placement and routing method includes the following steps:
[0035] S1: Abstract the internal hardware modules of the FPGA into software modules with electrical ports, and each software module has corresponding attributes. Some software modules have attributes including sparsity and its sparsity rules.
[0036] S2: Read the fully connected netlist;
[0037] S3: Perform full-connectivity layout and routing based on the full-connectivity netlist and the software module;
[0038] S4: Determine if the routing meets the requirements. If the routing requirements are met, complete the routing and output the hardware netlist.
[0039] S5: If the routing requirements are not met, return to the fully connected layout and routing step if the iteration is not finished; if the routing requirements are not met, determine whether the corresponding software module has the property of being sparse if the iteration is finished; if it does not have the property of being sparse, report an exception and exit.
[0040] S6: If the property is sparse, perform sparsification and sparse routing, and check again whether the routing meets the requirements. If the routing requirements are met, complete the routing and output the hardware netlist. If the routing requirements are not met, return to the sparsification and sparse routing steps if the iteration is not over, and return to the exception and exit if the iteration is over.
[0041] Specifically, the present invention includes a modeling stage, a placement and routing stage, and a performance evaluation stage.
[0042] In the modeling phase, S1, each software module (primitive) has corresponding attributes. These attributes are described based on the software tools and hardware functions, and therefore, the attributes of different software modules may be the same or different. Besides sparsity and its rules, these attributes also include port input / output directions and driving capabilities. After using sparsification methods, the software module or its port attributes need to have a descriptive field related to "sparseness" added, along with optional "sparse rules." These rules include, but are not limited to: prioritizing high-order bits, randomizing bit sparsity, disallowing sparsity for specific bits, and / or default values for sparse bits, where the default value for sparse bits is 0, 1, or a random value. In specific implementations, the keywords and format of this field are not limited to the examples mentioned in this paper, but the "sparseness" characteristic needs to be passed as a flag or specific semantic to the place-and-route tool, which executes S2-S6.
[0043] During the placement and routing phase, specifically steps S2-S6 executed by the placement and routing tool, the tool initially attempts to plan routing using a fully connected approach. However, if signal congestion or performance issues persist after the predetermined number of iterations, and the software module supports sparse routing, the tool switches to sparse routing mode. Based on the sparse rules defined in the modeling phase, the tool gradually reduces the signal connections in the congested network according to rule priority until the congestion problem is resolved or performance is achieved. If the software module did not define sparse rules during the modeling phase, the placement and routing tool will use the default sparse rules.
[0044] The performance evaluation phase also includes the following steps: recording the sparsified connection signals and outputting them to the operation log or a report in a specific format; and performing performance evaluation based on the operation log or the report in a specific format. The performance evaluation method is as follows: based on the sparsification results in the operation log or the report in a specific format, locate the source and receiver ends of the signal connections, and perform a qualitative evaluation of the sparsification results. Additionally, in complex designs, quantitative analysis can be performed based on the sparsification results and / or the hardware netlist generated after sparsification. The quantitative analysis method is as follows: perform simulation based on the hardware netlist generated after sparsification, and perform quantitative analysis on the sparsed routing results.
[0045] In one embodiment, sparsification is performed on the output of an integer-type DSP (Digital Signal Processing Module):
[0046] Assume the FPGA chip contains 4 rows of DSP modules, with 16 processing units in each row, for a total of 64 DSP units. During the modeling phase, the 12-bit wide DSP processing unit is abstracted into the following software module:
[0047] mul12x12(input[11:0]a,input[11:0]b,output[21:0]p);
[0048] / *attribution:enable_sparse=1,sparse_priority=output,sparse_mode1=0,sparse_mode2=random* /
[0049] During the placement and routing phase, assume the user uses 60 DSP units, and that the most complex part of the signal connections in the user's logic is located in the right half of the second row of the DSP. Due to already high resource utilization, the placement and routing tool will be unable to optimize the placement of the DSP and related processing logic. The DSP has many input and output signals; in this example, each processing unit uses 24 inputs and 24 outputs. Each output may connect to multiple driver nodes, leading to network signal congestion. If the signal congestion problem cannot be effectively resolved, some signal lines will need to be connected over longer distances via detours, resulting in increased transmission delay, reduced operating frequency, or even failure to complete the routing task. Using the sparsity technique of this invention, the placement and routing tool will activate sparsification mode after several routing attempts, attempting to reduce the number of sparseable signals according to the sparsification rules mentioned above. These rules can be interpreted as prioritizing sparse output data, prioritizing the lower bits of sparse data, and filling the sparsed data bits with random numbers. The placement and routing tool can attempt to sparse the lowest 8 bits of the output data, while simultaneously randomly padding the driven endpoints with 8 bits. This can reduce at least 8 wiring resources, which is especially important around modules with congested signals, and layout and routing tools will be able to more easily meet the wiring requirements according to the constraints.
[0050] Assuming that after the above sparsification, the output signals of 6 DSP units have been partially sparsified, the number of signals sparsified in each DSP unit varies from 4 to 8. The placement and routing tool will generate a sparsified hardware netlist based on this result, which users can then use for further simulation analysis.
[0051] In summary, the FPGA placement and routing method based on sparse technology provided by this invention can significantly improve chip performance or computing power without increasing physical routing resources by developing sparsity and sparsity rules for each software module. This allows for a significant reduction in routing resource usage in applications such as AI computing or image processing. It effectively solves the problem of signal congestion caused by insufficient network resources in existing technologies and reduces hardware costs and the burden of placement and routing.
[0052] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. An FPGA placement and routing method based on sparse technology, characterized in that, Includes the following steps: The internal hardware modules of the FPGA are abstracted into software modules with electrical ports, and each software module has corresponding attributes. Some software modules have attributes including sparsity and its sparsity rules. The sparsity rules include: high bits are reserved first, bits are randomly sparsified, specific bits are not allowed to be sparsified, and / or default values for sparsity bits. Read the fully connected netlist; Perform full-connectivity layout and routing based on the fully connected netlist and the software module; Determine if the routing meets the requirements. If the routing requirements are met, complete the routing and output the hardware netlist. If the routing requirements are not met, return to the fully connected placement and routing step if the iteration is not finished; if the routing requirements are not met, determine whether the corresponding software module has the property of being sparse if the iteration is finished; if it does not have the property of being sparse, report an exception and exit. If the property is sparse, then perform sparsification and sparse routing, and check again whether the routing meets the requirements. If the routing requirements are met, then complete the routing and output the hardware netlist. If the routing requirements are not met, return to the sparsification and sparse routing steps if the iteration is not over, and exit if the iteration is over.
2. The FPGA placement and routing method based on sparse technology as described in claim 1, characterized in that, The sparse bits default to 0, 1, or a random value.
3. The FPGA placement and routing method based on sparse technology as described in claim 1, characterized in that, The attributes are described based on the software tools and hardware functions.
4. The FPGA placement and routing method based on sparse technology as described in claim 1, characterized in that, The attributes also include the port's input / output direction and drive capability.
5. The FPGA placement and routing method based on sparse technology as described in claim 1, characterized in that, It also includes the following steps: Record the sparsed connection signals and output them to the runtime log or a report in a specific format; Performance evaluation is performed based on runtime logs or reports in a specific format.
6. The FPGA placement and routing method based on sparse technology as described in claim 5, characterized in that, The performance evaluation methods are as follows: Based on the sparsification results in the operation log or a report in a specific format, locate the source and receiver ends of the signal connection, and perform a qualitative evaluation of the sparsification results.
7. The FPGA placement and routing method based on sparse technology as described in claim 1, characterized in that, It also includes the following steps: Quantitative analysis is performed based on the sparsification results and / or the hardware netlist generated after sparsification.
8. The FPGA placement and routing method based on sparse technology as described in claim 7, characterized in that, The quantitative analysis method is as follows: Simulations are performed based on the hardware netlist generated after sparsification, and quantitative analysis is conducted on the sparsed routing results.
9. The FPGA placement and routing method based on sparse technology as described in claim 1, characterized in that, Switch to sparse routing mode when performing sparsification and sparse routing.