A trench gate MOSFET and a manufacturing process thereof

Abstract

The trench gate MOSFET and the manufacturing process thereof provided by the embodiment of the application reduce the heat manufacturing process and optimize the process.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a trench gate MOSFET and a preparation process thereof. BACKGROUND

[0002] Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is a kind of three-terminal electronic device of using gate voltage to control drain current.

[0003] The prior art process is long in manufacturing the trench gate MOSFET, because the first injection area and the second injection area are formed by two times of injection respectively through independent injection processes, and a separate annealing activation process is needed subsequently. SUMMARY

[0004] Therefore, the present application provides a trench gate MOSFET and a preparation process thereof, which greatly reduces the thermal process and optimizes the process flow.

[0005] In order to achieve the above object, the present application provides the following technical scheme:

[0006] In a first aspect, the present application provides a preparation process of a trench gate MOSFET, comprising:

[0007] etching a plurality of spaced grooves on an epitaxial layer;

[0008] forming a first injection area at the bottom of the plurality of grooves and a second injection area on the surface of the epitaxial layer by ion implantation at the same time;

[0009] growing a gate oxide layer on the inner wall of the plurality of grooves and the surface of the epitaxial layer, and simultaneously activating the impurity atoms doped in the first injection area and the second injection area;

[0010] depositing polysilicon in the plurality of grooves;

[0011] forming a third injection area by ion implantation in the second injection area;

[0012] forming an isolation protective layer on the surface of the epitaxial layer;

[0013] etching a first contact hole in the plurality of grooves and etching a second contact hole in the second injection area;

[0014] filling the first contact hole with a metal gate lead and filling the second contact hole with a metal source lead.

[0015] As a preferred embodiment of the present application, after depositing the polysilicon in the plurality of grooves, the process comprises:

[0016] etching back the polysilicon until the polysilicon upper surface is not higher than the epitaxial layer upper surface.

[0017] As a preferred embodiment of the present application, the forming the first implant region in the plurality of trench bottoms and the second implant region on the epitaxial layer upper surface by ion implantation comprises:

[0018] sequentially performing a first ion implantation, a second ion implantation and a third ion implantation to form the first implant region in the plurality of trench bottoms and the second implant region on the epitaxial layer upper surface.

[0019] As a preferred embodiment of the present application, the first ion implantation has an energy of 40 keV and a dose of 7.5 e 12 / cm 2 , the second ion implantation has an energy of 100 keV and a dose of 5.5 e 12 / cm 2 , and the third ion implantation has an energy of 200 keV and a dose of 4.5 e 12 / cm 2 .

[0020] As a preferred embodiment of the present application, the gate oxide layer is grown on the inner walls of the plurality of trenches and the epitaxial layer upper surface at a temperature of 900-1050 °C and a thickness of 250-500 A.

[0021] As a preferred embodiment of the present application, the ion implantation for forming the third implant region has an energy of 65 keV and a dose of 1.5 e 14 / cm 2 .

[0022] As a preferred embodiment of the present application, the first implant region and the second implant region are implanted with the same impurity, and the first implant region and the second implant region are implanted with a different impurity from the third implant region.

[0023] As a preferred embodiment of the present application, the first ion implantation, the second ion implantation and the third ion implantation are implanted with boron ions, and the third implant region is implanted with arsenic ions.

[0024] As a preferred embodiment of the present application, after etching the first contact hole in the plurality of trenches and etching the second contact hole in the second implant region, the method further comprises:

[0025] forming a fourth implant region at the bottom of the second contact hole by ion implantation.

[0026] Compared with the prior art, the preparation process of the trench gate MOSFET provided in the embodiment of the application reduces the heat process and optimizes the process.

[0027] In the second aspect, the embodiment of the application provides a trench gate MOSFET prepared by the preparation process in the first aspect.

[0028] Compared with the prior art, the trench gate MOSFET provided in the embodiment of the application has the same beneficial effects as the technical solution provided in the first aspect, and details are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only exemplary, and for those skilled in the art, other drawings can be obtained from the provided drawings without creative labor.

[0030] The structures, proportions, sizes, etc. shown in the specification are only used to cooperate with the content disclosed in the specification, to be understood and read by those skilled in the art, and are not used to limit the conditions that the application can be implemented, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects that the application can produce and the purposes that the application can achieve, should still fall within the scope of the technical content disclosed by the application.

[0031] Figure 1 A preparation process flow diagram of a trench gate MOSFET provided in the embodiment of the application is shown in the following table:

[0032] Figures 2-7 A cross-sectional structure diagram corresponding to each step of the preparation process of a trench gate MOSFET provided in the embodiment of the application is shown in the following table: DETAILED DESCRIPTION

[0033] The embodiments of the application are described below by specific examples, and those skilled in the art can easily understand other advantages and effects of the application from the content disclosed in the specification. Obviously, the described embodiments are part of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the application.

[0034] As Figure 1 shown, the embodiment of the present application provides a preparation process of trench gate MOSFET, comprising:

[0035] Step S01, etching a plurality of interval arranged grooves 02 on the epitaxial layer 01;

[0036] Referring to Figure 1 and Figure 2 , the embodiment of the present application sets an epitaxial layer 01 on the substrate 03, and then etches a plurality of interval arranged grooves 03 on the epitaxial layer 01 by photolithography and etching process to form a trench gate MOSFET.

[0037] Step S02, forming a first implantation region 04 at the bottom of the plurality of grooves 02 and a second implantation region 05 on the surface of the epitaxial layer 01 by ion implantation at the same time;

[0038] Referring to Figure 1 and Figure 3 , after the etching of the grooves 02 is completed, the photoresist is removed, and boron ion implantation is performed multiple times, and energy 40keV / dose 7.5e 12 / cm 2 , energy 100keV / dose 5.5e 12 / cm 2 , and energy 200keV / dose 4.5e 12 / cm 2 are implanted each time to form the first implantation region 04 at the bottom of the grooves 02 and the second implantation region 05 on the surface of the epitaxial layer 01;

[0039] Step S03, growing a gate oxide layer 06 on the inner wall of the plurality of grooves 02 and the surface of the epitaxial layer 01, and activating the impurity atoms doped in the first implantation region 04 and the second implantation region 05;

[0040] Referring to Figure 1 and Figure 4 , the temperature of growing the gate oxide layer 06 on the inner wall of the plurality of grooves 02 and the surface of the epitaxial layer 01 is 900-1050℃, and the thickness is 250A-500A. The activation of the impurities in the first implantation region 04 and the second implantation region 05 is completed in the process of forming the gate oxide layer 06 on the side wall of the grooves 02, so that the embodiment of the present application reduces the heat process and optimizes the process.

[0041] Step S04, depositing polycrystalline silicon in the plurality of grooves 03;

[0042] Referring to Figure 1 and Figure 4 , in Figure 4The trench is filled with polysilicon, and after the polysilicon is deposited in the plurality of trenches 02, the polysilicon is etched back until the upper surface of the polysilicon is not higher than the upper surface of the epitaxial layer 01 to facilitate subsequent deposition of an isolation protective layer.

[0043] Step S05, ion implantation is performed in the second implantation region 05 to form a third implantation region 07.

[0044] Reference Figure 1 and Figure 5 Specifically, the ion implantation for forming the third implantation region 07 has an energy of 65 keV and a dose of 1.5e 14 / cm 2 The third implantation region 07 can form a PN junction with the second implantation region 05 to form a source region, the impurities implanted in the first implantation region 04 and the second implantation region 05 are the same, the impurities implanted in the first implantation region 04 and the second implantation region 05 are different from the impurities implanted in the third implantation region 07, and the impurities implanted in the third implantation region 07 are arsenic ions.

[0045] Step S06, forming an isolation protective layer 08 on the upper surface of the epitaxial layer 01.

[0046] Reference Figure 1 and Figure 6 The isolation protective layer 08 is provided to protect the wafer surface.

[0047] Step S07, etching a first contact hole in the plurality of trenches 02 and etching a second contact hole in the second implantation region.

[0048] Step S08, filling the first contact hole 09 with a metal gate and filling the second contact hole 10 with a metal source.

[0049] Reference 1 and Figure 7 The first contact hole 09 in the trench 02 and the second contact hole 10 in the second implantation region 05 are etched, then a fourth implantation region 11 is formed at the bottom of the second contact hole 10 by ion implantation, the impurities implanted in the fourth implantation region 11 are boron ions, then the first contact hole 09 is filled with a metal gate and the second contact hole 10 is filled with a metal source.

[0050] In a second aspect, the embodiments of the present application provide a trench gate MOSFET prepared by the preparation process of the first aspect.

[0051] Compared with the prior art, the trench gate MOSFET provided by the embodiments of the present application has the same beneficial effects as the technical solutions provided by the first aspect, and will not be described here.

[0052] In the application, when the epitaxial layer is N type, the first and second implantation regions 04 and 05 are P type, and the third implantation region is N type; when the epitaxial layer is P type, the first and second implantation regions 04 and 05 are N type, and the third implantation region is P type.

[0053] Although the present application has been described in detail with general description and specific embodiments above, some modifications or improvements can be made on the basis of the present application, which is obvious to those skilled in the art. Therefore, these modifications or improvements made on the basis of not deviating from the spirit of the present application, all belong to the scope of the present application claimed.

Claims

1. A trench gate MOSFET fabrication process, characterized by, The method comprises: etching a plurality of spaced-apart grooves on the epitaxial layer; forming a first implantation region at the bottom of the plurality of grooves and a second implantation region on the surface of the epitaxial layer by ion implantation; growing a gate oxide layer on the inner wall of the plurality of grooves and the surface of the epitaxial layer, and simultaneously activating the impurity atoms doped in the first implantation region and the second implantation region; depositing polysilicon in the plurality of grooves; forming a third implantation region in the second implantation region by ion implantation; forming an isolation protection layer on the surface of the epitaxial layer; etching a first contact hole in the plurality of grooves and a second contact hole in the second implantation region; filling the first contact hole with a metal gate lead and the second contact hole with a metal source lead; after depositing the polysilicon in the plurality of grooves, the method further comprises: etching back the polysilicon until the upper surface of the polysilicon is not higher than the upper surface of the epitaxial layer; the method of forming the first implantation region at the bottom of the plurality of grooves and the second implantation region on the surface of the epitaxial layer by ion implantation comprises: sequentially performing a first ion implantation, a second ion implantation and a third ion implantation to form the first implantation region at the bottom of the plurality of grooves and the second implantation region on the surface of the epitaxial layer; the impurities implanted in the first implantation region and the second implantation region are the same, and the impurities implanted in the first implantation region and the second implantation region are different from the impurities implanted in the third implantation region.

2. The process of claim 1, wherein: the trench-gate MOSFET is a vertical trench-gate MOSFET. The first ion implantation has an energy of 40 keV and a dose of 7.5 e 12 / cm 2 , the second ion implantation has an energy of 100 keV and a dose of 5.5 e 12 / cm 2 , and the third ion implantation has an energy of 200 keV and a dose of 4.5 e 12 / cm 2 .

3. The process of claim 1, wherein: the trench-gate MOSFET is a vertical trench-gate MOSFET. The temperature for growing the gate oxide layer on the inner wall of the plurality of grooves and the surface of the epitaxial layer is 900-1050℃, and the thickness is 250-500A.

4. The process for preparing a trench-gate MOSFET according to claim 1, wherein: The energy of the ion implantation forming the third implant region is 65 keV with a dose of 1.5 e 14 / cm 2 .

5. The fabrication process of a trench gate MOSFET as described in claim 1, characterized in that: The impurities for the first ion implantation, the second ion implantation and the third ion implantation are boron ions, and the impurities implanted in the third implantation region are arsenic ions.

6. The process for preparing a trench-gate MOSFET according to claim 1, wherein: after etching the first contact hole in the plurality of grooves and the second contact hole in the second implantation region, the method further comprises: forming a fourth implantation region at the bottom of the second contact hole by ion implantation.

7. A trench-gate MOSFET, characterized by, Prepared by the preparation process of any one of claims 1-6.

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