Semiconductor device and method for manufacturing semiconductor memory device

Abstract

The present application relates to a semiconductor device, and a manufacturing method of a semiconductor memory device. The semiconductor device is provided with a laminate and a memory pillar formed in a memory hole of the laminate. The memory pillar has a configuration in which a semiconductor portion (61b), a tunnel insulating film (62a), and a charge storage layer (62b) are sequentially laminated. A barrier insulating film (53) is provided between the charge storage layer (62b) and a conductive layer (52). The conductive layer (52) contains molybdenum. The barrier insulating film (53) has a silicon oxide film (53a) and an aluminum oxide film (53b). In a region from the conductive layer (52) to the aluminum oxide film (53b), chlorine that inhibits diffusion of OH is contained. The concentration of chlorine in a second portion of the conductive layer that is closer to the aluminum oxide film (53b) than the first portion is higher than the concentration of impurities in the first portion of the conductive layer (52).

Description

[0001] [Citation of relevant applications]

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2021-152938 filed on September 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0004] For example, a semiconductor device such as a NAND flash memory includes a substrate and a multilayer stack disposed on the substrate. The multilayer stack is constructed by alternately stacking conductive layers and insulating layers. Multiple memory vias are formed in the multilayer stack. In each memory via, a core, a semiconductor layer, a tunnel insulating film, and a charge storage layer are sequentially stacked from its center outwards. Barrier insulating films are disposed between the conductive layers and the insulating layers, and between the conductive layers and the charge storage layers. Summary of the Invention

[0005] Comparing a semiconductor device with a tungsten conductor layer to one with a molybdenum conductor layer, the latter is more prone to hydrogen and oxygen diffusion through the conductor layer to the OH diffusion in the barrier insulating film. If this phenomenon creates energy levels in the barrier insulating film, there is a possibility of charge leakage—a phenomenon known as charge leakage—from the charge storage layer into the barrier insulating film. This can worsen data retention characteristics.

[0006] One embodiment provides a semiconductor device capable of improving data retention characteristics, and a method for manufacturing the semiconductor device.

[0007] The semiconductor device of the embodiment includes a multilayer stack and memory pillars. The multilayer stack has a structure in which multiple conductive layers and insulating layers are alternately stacked in a predetermined direction, and memory holes are formed in a through-type manner in the predetermined direction. Memory pillars are formed within the memory holes. The memory pillars have a structure in which a semiconductor portion, a tunnel insulating film, and a charge storage layer are sequentially stacked from their inner side to their outer side. A barrier insulating film is disposed between the charge storage layer and the conductive layer. The conductive layer contains molybdenum. The barrier insulating film has a first film disposed in contact with the charge storage layer and a second film disposed between the first film and the conductive layer. In the region from the conductive layer to the second film, impurities that inhibit OH diffusion are included. Compared to the impurity concentration in the first portion of the conductive layer, the impurity concentration in the second portion of the conductive layer, which is closer to the second film than the first portion, is higher.

[0008] In the method for manufacturing a semiconductor memory device according to the embodiment, a barrier insulating film is formed by sequentially forming a first film and a second film on the surface of a charge storage layer, a molybdenum nitride film is formed on the surface of the second film by alternately passing MoO2Cl2 gas and ammonia gas through the surface of the second film, and a conductive layer containing molybdenum is formed on the surface of the second film by alternately passing MoO2Cl2 gas and hydrogen gas through the molybdenum nitride film.

[0009] Based on the aforementioned configuration, a semiconductor device capable of improving data retention characteristics and a method for manufacturing the semiconductor device can be provided. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the general configuration of a memory system according to an implementation method.

[0011] Figure 2 This is a block diagram illustrating the schematic configuration of a semiconductor device in an embodiment.

[0012] Figure 3 It is a circuit diagram showing the equivalent circuit of the semiconductor device in the embodiment.

[0013] Figure 4 This is a perspective view showing the cross-sectional three-dimensional structure of a semiconductor device according to an embodiment.

[0014] Figure 5 This is a cross-sectional view showing the cross-sectional structure of the memory column in the embodiment.

[0015] Figure 6 It means along Figure 5 A sectional view of the cross-sectional structure of the VI-VI line.

[0016] Figure 7 It means along Figure 5 A cross-sectional view of the section structure along line VII-VII.

[0017] Figure 8 This is a cross-sectional view showing a portion of the manufacturing process of a semiconductor device according to an embodiment.

[0018] Figure 9 This is a cross-sectional view showing a portion of the manufacturing process of a semiconductor device according to an embodiment.

[0019] Figure 10 This is a cross-sectional view showing a portion of the manufacturing process of a semiconductor device according to an embodiment.

[0020] Figure 11 This is a cross-sectional view showing a portion of the manufacturing process of a semiconductor device according to an embodiment.

[0021] Figure 12This is a cross-sectional view showing a portion of the manufacturing process of a semiconductor device according to an embodiment.

[0022] Figure 13 This is a cross-sectional view showing a portion of the manufacturing process of a semiconductor device according to an embodiment.

[0023] Figure 14 It represents the depth D from the outer surface of the conductive layer. p With chlorine concentration C Cl A graph showing the relationship between the two.

[0024] Figure 15 This represents the maximum value C of the molybdenum nitride film thickness Tm versus the chlorine concentration. Cl，max A graph showing the relationship between the two.

[0025] Figure 16 This represents the interfacial chlorine concentration C. Cl，if With respect to the threshold voltage V of the charge storage layer inv A graph showing the relationship between the offset and the value.

[0026] Figure 17 This is a cross-sectional view showing the cross-sectional structure of the conductor layer periphery of a memory pillar according to another embodiment. Detailed Implementation

[0027] Hereinafter, embodiments will be described with reference to the accompanying drawings. For ease of understanding, the same reference numerals will be used as much as possible to denote the same constituent elements in each drawing, and repeated descriptions will be omitted. <Embodiment> (Configuration of the memory system) As shown... Figure 1 As shown, the memory system of this embodiment includes a memory controller 1 and a semiconductor device 2. The semiconductor device 2 is a non-volatile memory device configured as a NAND flash memory. The memory system can be connected to a host device. The host device is, for example, an electronic device such as a personal computer or a mobile terminal. Furthermore, in Figure 1 The diagram shows only one semiconductor device 2, but in an actual memory system, multiple semiconductor devices 2 are used.

[0028] The memory controller 1 controls the writing of data to the semiconductor device 2 based on write requests from the host. Additionally, the memory controller 1 controls the reading of data from the semiconductor device 2 based on read requests from the host. Between the memory controller 1 and the semiconductor device 2, the following signals are received: transmit chip enable signal / CE, standby / busy signal / RB, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protection signal / WP, data signals DQ<7:0>, and data strobe signals DQS, / DQS.

[0029] The chip enable signal / CE is used to start semiconductor device 2. The standby / busy signal / RB is used to indicate whether semiconductor device 2 is in standby or busy state. "Standby state" means accepting commands from external sources. "Busy state" means not accepting commands from external sources. The instruction latch enable signal CLE indicates that the signal DQ<7:0> represents an instruction. The address latch enable signal ALE indicates that the signal DQ<7:0> represents an address. The write enable signal / WE is used to fetch received signals into semiconductor device 2, and is activated whenever the memory controller 1 receives instructions, addresses, and data. The memory controller 1 instructs semiconductor device 2 to fetch the signal DQ<7:0> while the signal / WE is at a "L" (low) level.

[0030] The read enable signal RE, / RE is used by the memory controller 1 to read data from the semiconductor device 2. The read enable signal RE, / RE is used, for example, to control the timing of the operation of the semiconductor device 2 when the output signal DQ<7:0> is displayed. The write protect signal / WP is used to instruct the semiconductor device 2 to prohibit data writing and erasure. The signal DQ<7:0> is the entity that receives and transmits data between the semiconductor device 2 and the memory controller 1, including instructions, addresses, and data. The data strobe signal DQS, / DQS is used to control the timing of the input and output of the signal DQ<7:0>.

[0031] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0032] The host interface 13 outputs requests and user data (write data) received from the host to the internal bus 16. Additionally, the host interface 13 sends user data read from the semiconductor device 2 and responses from the processor 12 to the host.

[0033] The memory interface 15, based on instructions from the processor 12, controls the processes of writing user data to and reading data from the semiconductor device 2. The processor 12 comprehensively controls the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the processor 12 receives a request from the host via the host interface 13, it performs control according to that request. For example, based on a request from the host, the processor 12 instructs the memory interface 15 to write user data and perform parity checks to the semiconductor device 2. Additionally, based on a request from the host, the processor 12 instructs the memory interface 15 to read user data and perform parity checks from the semiconductor device 2.

[0034] Processor 12 determines the memory region (memory area) on semiconductor device 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory region for data in page units (page data) written as units. Hereinafter, user data stored in one page of semiconductor device 2 will also be referred to as "cell data". Cell data is generally encoded and stored in semiconductor device 2 as codewords. In this embodiment, encoding is not necessarily required. Memory controller 1 may also store cell data in semiconductor device 2 without encoding. Figure 1 The following example illustrates the encoding structure. When the memory controller 1 does not perform encoding, the page data and the cell data are identical. Furthermore, a codeword can be generated based on a single cell data unit, or it can be generated based on segmented data formed by dividing the cell data. Alternatively, a codeword can be generated using multiple cell data units.

[0035] Processor 12 determines the memory region of semiconductor device 2 as the destination for each unit of data. It allocates physical addresses to the memory regions of semiconductor device 2. Processor 12 uses these physical addresses to manage the memory regions as the destinations for writing unit data. Processor 12 instructs memory interface 15 to write user data to semiconductor device 2 by specifying the determined memory region (physical address). Processor 12 manages the mapping between logical addresses (host-managed logical addresses) and physical addresses of user data. Upon receiving a read request containing a logical address from the host, processor 12 identifies the physical address corresponding to the logical address and instructs memory interface 15 to read user data by specifying the physical address.

[0036] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes the codewords read from semiconductor device 2. RAM 11 temporarily stores the user data received from the host before storing it in semiconductor device 2, or temporarily stores the data read from semiconductor device 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0037] exist Figure 1 The diagram illustrates a configuration where the memory controller 1 includes both an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the semiconductor device 2. Figure 1 The specific composition or configuration of the elements shown is not particularly limited.

[0038] In the event that a write request is received from the host Figure 1 The memory system operates as follows: Processor 12 temporarily stores data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the code word to memory interface 15. Memory interface 15 writes the input code word to semiconductor device 2.

[0039] When a read request is received from the host Figure 1 The memory system operates as follows: The memory interface 15 inputs the codeword read from the semiconductor device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0040] (The structure of a semiconductor device) is as follows: Figure 2 As shown, the semiconductor device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a line decoder 27, a sense amplifier 28, an input / output pad group 30, a logic control pad group 31, and a power input terminal group 32.

[0041] The memory cell array 21 is the data storage section. The memory cell array 21 is composed of multiple memory cell transistors associated with multiple bit lines and multiple word lines. The input / output circuit 22 receives the transmit signal DQ<7:0> and the data strobe signal DQS, / DQS between itself and the memory controller 1. Furthermore, the input / output circuit 22 transmits the instruction and address contained in the signal DQ<7:0> to the register 24. Additionally, the input / output circuit 22 receives and transmits write data and read data between itself and the sense amplifier 28.

[0042] The logic control circuit 23 receives the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP from the memory controller 1. Additionally, the logic control circuit 23 transmits the standby / busy signal / RB to the memory controller 1, thus informing the external system of the status of the semiconductor device 2.

[0043] Register 24 temporarily stores various data. For example, register 24 stores instructions indicating write, read, and erase operations. After the instruction is input from memory controller 1 to input / output circuit 22, it is transferred from input / output circuit 22 to register 24 and stored therein. Register 24 also stores the address corresponding to the instruction. After the address is input from memory controller 1 to input / output circuit 22, it is transferred from input / output circuit 22 to register 24 and stored therein. Furthermore, register 24 also stores status information indicating the operating state of semiconductor device 2. The status information is updated by sequencer 25 each time according to the operating state of memory cell array 21, etc. Based on requests from memory controller 1, the status information is output as a status signal from input / output circuit 22 to memory controller 1.

[0044] The sequencer 25 controls the operation of each part of the memory cell array 21 based on control signals input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23. The voltage generation circuit 26 generates the voltages required for writing, reading, and erasing data in the memory cell array 21. These voltages include, for example, the voltages applied to multiple word lines and multiple bit lines of the memory cell array 21. The operation of the voltage generation circuit 26 is controlled by the sequencer 25.

[0045] The row decoder 27 is a circuit consisting of a group of switches used to apply voltage to multiple word lines of the memory cell array 21. The row decoder 27 receives a block address and a row address from register 24, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the switching state of the switch group by applying a voltage from voltage generation circuit 26 to the selected word line. The operation of the row decoder 27 is controlled by sequencer 25.

[0046] The sense amplifier 28 is a circuit that adjusts the voltage applied to the bit lines of the memory cell array 21, or reads out the voltage of the bit lines and converts it into data. During data readout, the sense amplifier 28 acquires the data read from the memory cell transistors of the memory cell array 21 to the bit lines and transmits the acquired readout data to the input / output circuit 22. During data writeout, the sense amplifier 28 transmits the data written via the bit lines to the memory cell transistors. The operation of the sense amplifier 28 is controlled by the sequencer 25.

[0047] The input / output pad group 30 is a portion that has multiple terminals (pads) for receiving and transmitting various signals between the memory controller 1 and the input / output circuit 22. Each terminal is individually configured to correspond to the signal DQ<7:0> and the data strobe signal DQS, / DQS.

[0048] The logic control pad group 31 is a portion that has multiple terminals for receiving and transmitting various signals between the memory controller 1 and the logic control circuit 23. Each terminal is individually configured to correspond to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protection signal / WP, and standby / busy signal / RB.

[0049] The power input terminal group 32 is a portion provided with multiple terminals for receiving the voltages required for the operation of the semiconductor device 2. The voltages applied to each terminal include the power supply voltage Vcc, VccQ, Vpp, and the ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage supplied externally as the operating power supply, for example, approximately 3.3 V. The power supply voltage VccQ is, for example, 1.2 V. The power supply voltage VccQ is the voltage used when receiving and transmitting signals between the memory controller 1 and the semiconductor device 2. The power supply voltage Vpp is a higher voltage than the power supply voltage Vcc, for example, 12 V.

[0050] (Structure of the electronic circuitry of the memory cell array) Next, the structure of the electronic circuitry of the memory cell array 21 will be explained. For example... Figure 3As shown, the memory cell array 21 has multiple string cells SU0 to SU3. Each string cell SU0 to SU3 has multiple NAND string SRs. Each NAND string SR has, for example, eight memory cell transistors MT0 to MT7 and two select transistors STD and STS. Furthermore, the number of memory cell transistors and the number of select transistors in the NAND string SR can be arbitrarily changed.

[0051] Multiple string units SU0 to SU3 collectively constitute one block. Furthermore, in Figure 3 The diagram only shows a single block, but in reality, multiple such blocks are arranged in the memory cell array 21. Hereinafter, each of the serial cells SU0 to SU3 will be referred to as "serial cell SU" without distinction. Similarly, each of the memory cell transistors MT0 to MT7 will be referred to as "memory cell transistor MT" without distinction.

[0052] The memory cell array 21 has N bit lines BL0 to BL(N-1). Furthermore, "N" is a positive integer. Each string cell SU has the same number of NAND strings SR as the number of bit lines BL0 to BL(N-1). Memory cell transistors MT0 to MT7, disposed in the NAND strings SR, are connected in series between the source of the select transistor STD and the drain of the select transistor STS. The drain of the select transistor STD is connected to any one of the multiple bit lines BL0 to BL(N-1). The source of the select transistor STS is connected to the source line SL. In the following description, bit lines BL0 to BL(N-1) are sometimes referred to as "bit line BL" without distinction.

[0053] Each memory cell transistor (MT) is configured as a transistor having a charge storage layer in its gate portion. The amount of charge stored in the charge storage layer is equivalent to the data stored in the memory cell transistor (MT). The memory cell transistor (MT) can be, for example, a charge-trapping type using a silicon nitride film or the like as the charge storage layer, or a floating-gate type using a silicon film or the like as the charge storage layer.

[0054] The gates of the multiple selection transistors STDs in the serial unit SU0 are all connected to the selection gate line SGD0. A voltage is applied to the selection gate line SGD0 to switch the STDs. Serial units SU1 to SU3 are also connected to the selection gate lines SGD1 to SGD3 respectively.

[0055] The gates of the multiple selection transistors STS in the serial cell SU0 are all connected to the selection gate line SGS0. A voltage is applied to the selection gate line SGS0 to switch the individual selection transistors STS. Serial cells SU1 to SU3 are also connected to the selection gate lines SGS1 to SGS3 respectively. Alternatively, the serial cells SU0 to SU3 constituting one block may share a common selection gate line, with the gates of the individual selection transistors STS in the serial cells SU0 to SU3 connected to this common selection gate line.

[0056] The gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7. In order to switch the memory cell transistors MT0 to MT7 on and off, or to change the amount of charge stored in the charge storage layers of the memory cell transistors MT0 to MT7, a voltage is applied to the word lines WL0 to WL7.

[0057] Data writing and reading in semiconductor device 2 are performed uniformly on a per-page basis, consisting of multiple memory cell transistors MT connected to a word line WL in any string cell SU. On the other hand, data erasure in semiconductor device 2 is performed uniformly on all memory cell transistors MT contained in a block. Various well-known methods can be used to perform such data writing, reading, and erasure, so detailed descriptions are omitted.

[0058] (Structure of the Semiconductor Device) Next, the structure of the semiconductor device 2, especially the structure near the memory cell array 21, will be described in detail. Figure 4 As shown, the semiconductor device 2 includes a substrate 40, an insulating layer 41, a semiconductor layer 42, and a laminate 50.

[0059] Substrate 40 is a plate-shaped component with a flat surface in the direction indicated by arrow Z in the figure. Substrate 40 is, for example, a silicon wafer. On the upper surface of substrate 40, an insulating layer 41 and a semiconductor layer 42 are formed as a multilayer film, for example, by CVD (Chemical Vapor Deposition). Furthermore, the direction indicated by arrow Z will be referred to below as the "Z-direction". Additionally, Figure 4 The directions indicated by arrow X and arrow Y are referred to as the "X direction" and "Y direction," respectively. The X and Y directions are orthogonal to each other and also orthogonal to the Z direction. Furthermore, in this embodiment, the Z direction corresponds to a predetermined direction.

[0060] The insulating layer 41 is formed, for example, of an insulating material such as silicon oxide. At the bottom of the insulating layer 41, in contact with the substrate 40, a peripheral circuit, including a transistor Tr, wiring LN, etc., is formed. This peripheral circuit constitutes... Figure 2The sensor amplifier 28, line decoder 27, etc. are shown. The insulating layer 41 covers the entire surrounding circuit.

[0061] Semiconductor layer 42 is used as Figure 3 The source line SL is the functional layer. The semiconductor layer 42 is formed, for example, from a silicon-containing material such as polycrystalline silicon doped with impurities. The semiconductor layer 42 is buried in the insulating layer 41 below the memory cell array 21.

[0062] Furthermore, the entire semiconductor layer 42 can also be formed of a semiconductor material like silicon, but it can also be formed as... Figure 4 The structure shown is formed by at least two laminated layers, including a semiconductor layer 42a and a conductive layer 22b. The semiconductor layer 42a is formed, for example, from a semiconductor material such as silicon. The conductive layer 22b is formed, for example, from a metallic material such as tungsten.

[0063] A multilayer body 50 is disposed on the upper surface of the semiconductor layer 42. The multilayer body 50 has a structure formed by alternately depositing multiple layers of insulating layer 51 and conductive layer 52 in the Z direction. The insulating layer 51 and conductive layer 52 are formed as a multilayer film on the upper surface of the semiconductor layer 42, for example, by CVD deposition. The conductive layer 52 is a conductive layer. The conductive layer 52 is formed of a material containing molybdenum. Each conductive layer 52 serves as… Figure 3 The word lines WL0 to WL7, select gate lines SGS1, SGD1, etc.

[0064] An insulating layer 51 is disposed between adjacent conductive layers 52, 52, electrically insulating these conductive layers. The insulating layer 51 is formed, for example, of a material containing silicon oxide. In the laminate 50, a plurality of memory vias MH are formed in a through-plane manner in the Z direction. Memory pillars 60 are formed inside each memory via MH. Each memory pillar 60 is formed in the region from the uppermost insulating layer 51 to the semiconductor layer 42. Each memory pillar 60 and... Figure 3 The NAND string SR shown corresponds to this.

[0065] Figure 5 This is a diagram showing the cross-sectional structure of the stack 50 when the memory column 60 is cut through a plane (YZ plane) passing through its central axis. Figure 6 It means along Figure 5 A diagram showing the cross-sectional structure of the VI-VI line. (See diagram.) Figure 6 As shown, the memory column 60 has a circular or elliptical cross-sectional shape. The memory column 60 has a body 61 and a laminated film 62.

[0066] The main body 61 has a core 61a and a semiconductor portion 61b. The semiconductor portion 61b contains a semiconductor material, such as a material containing amorphous silicon. The semiconductor portion 61b is the portion that forms the channel for the memory cell transistor MT, etc. The core 61a is disposed inside the semiconductor portion 61b. The core 61a is formed, for example, of an insulating material such as silicon oxide. Alternatively, the entire main body 61 may be a semiconductor portion 61b, or it may be a structure in which the core 61a is not disposed inside.

[0067] The multilayer film 62 is formed by covering the outer periphery of the host 61. The multilayer film 62 includes, for example, a tunnel insulating film 62a and a charge storage layer 62b. The tunnel insulating film 62a is a film disposed on the outer periphery of the host 61. The tunnel insulating film 62a may contain, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 62a acts as a potential barrier between the host 61 and the charge storage layer 62b. For example, when electrons are injected from the host 61 into the charge storage layer 62b (writing operation), the electrons pass through the potential barrier of the tunnel insulating film 62a. Similarly, when holes are injected from the host 61 into the charge storage layer 62b (erasing operation), the holes pass through the potential barrier of the tunnel insulating film 62a.

[0068] The charge storage layer 62b is a film formed to cover the outer side of the tunnel insulating film 62a. The charge storage layer 62b may contain, for example, silicon nitride. The charge storage layer 62b has trapping points for capturing charge within the film. The portion of the charge storage layer 62b separated from the conductive layer 52 and the body 61 constitutes the charge storage layer, i.e., the storage region of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT varies depending on the presence or absence of charge in the charge storage layer 62b, or the amount of that charge.

[0069] like Figure 5 As shown, the outer peripheral surface of the conductive layer 52 is covered by a barrier insulating film 53. The barrier insulating film 53 is a film used to suppress reverse tunneling of charge from the conductive layer 52 to the laminated film 62 side. The barrier insulating film 53 is formed, for example, from a material comprising silicon oxide and aluminum oxide.

[0070] A cover insulating film 54 is disposed between the insulating layer 51 and the charge storage layer 62b. The cover insulating film 54 may contain, for example, silicon oxide. The cover insulating film 54 is used to protect the charge storage layer 62b from etching during the replacement process in which the sacrificial layer is replaced with the conductive layer 52. If the replacement process is not used in the formation of the conductive layer 52, the cover insulating film 54 may be omitted.

[0071] The portion of each conductive layer 52 located inside the memory pillar 60 functions as a transistor. That is, in each memory pillar 60, multiple transistors are electrically connected in series along the long side of each memory pillar 60. Each conductive layer 52 is connected to the gate of each transistor via a multilayer film 62. The semiconductor portion 61b located inside the transistor functions as a channel for that transistor.

[0072] A portion of the transistors arranged in series along the long side of the memory column 60, as Figure 3 The multiple memory cell transistors MT shown function. Additionally, transistors formed at both ends of the multiple memory cell transistors MT arranged in series serve as… Figure 3 The selected transistors STD and STS shown in the diagram perform their respective functions.

[0073] like Figure 4 As shown, multiple bit lines BL are disposed above each memory cylinder 60. Each bit line BL is formed as a straight line extending along the X direction. The bit lines BL are arranged in a manner along the Y direction. The upper end of the memory cylinder 60 is connected to any one of the multiple bit lines BL via a contact Cb. With this configuration, the semiconductor portion 61b of each memory cylinder 60 is electrically connected to the bit line BL.

[0074] The laminate 50 is broken into multiple parts by slit ST. Slit ST is along... Figure 4 A straight trench is formed extending in the Y direction, for example, to the depth of semiconductor layer 42. The upper portion of the stack 50 is interrupted by a slit SHE. The slit SHE is a shallow trench formed extending along the Y direction. The slit SHE is formed to a depth that interrupts only the conductive layer of the plurality of conductive layers 52 that is used as the select gate line SGD.

[0075] The stacked film 62 is removed from the lower end of the memory column 60. This connects the lower end of the semiconductor section 61b to the semiconductor layer 42. With this configuration, the semiconductor layer 42, which functions as the source line SL, is electrically connected to the channels of each transistor. (Construction of the Conductor Layer and the Barrier Insulating Film) Next, the specific constructions of the conductor layer 52 and the barrier insulating film 53 will be described.

[0076] like Figure 7As shown, the barrier insulating film 53 has a double-layer structure consisting of a silicon oxide film 53a and an aluminum oxide film 53b. The silicon oxide film 53a is disposed in contact with the charge storage layer 62b. The silicon oxide film 53a is formed, for example, of a material containing silicon dioxide. The aluminum oxide film 53b is disposed between the silicon oxide film 53a and the conductive layer 52. The aluminum oxide film 53b is formed, for example, of a material containing aluminum oxide. In this embodiment, the silicon oxide film 53a corresponds to the first film, and the aluminum oxide film 53b corresponds to the second film.

[0077] In the conductive layer 52, a chlorine-rich portion 52a is provided at a predetermined thickness from the portion that contacts the barrier insulating film 53. The chlorine-rich portion 52a contains more chlorine than the other portions 52b. Furthermore, the boundary between the conductive layer 52 and the barrier insulating film 53 is illustrated as interface 90. In this embodiment, portion 52b of the conductive layer 52 corresponds to the first portion. Additionally, the chlorine-rich portion 52a of the conductive layer 52 corresponds to the second portion, which is closer to the alumina film 53b than the first portion. (Semiconductor Device Manufacturing Method) Next, a semiconductor device manufacturing method will be described.

[0078] like Figure 8 As shown, firstly, a multilayer structure 70 is formed by alternately depositing multiple layers of insulating layer 51 and sacrificial layer 55 on a substrate (not shown) having arbitrary layers, as follows... Figure 9 As shown, a memory hole MH is formed in the stacked body 70. Then, as... Figure 10 As shown, a covering insulating film 54, a charge storage layer 62b, a tunnel insulating film 62a, a semiconductor portion 61b, and a core portion 61a are sequentially formed on the inner surfaces of the conductive layer 52 and the sacrificial layer 55 within the memory hole MH. Next, after a trench (not shown) is formed in the laminate 70, the sacrificial layer 55 is removed using a solution such as phosphoric acid through this trench. Thus, as... Figure 11 As shown, a cavity C is formed between adjacent insulating layers 51, 51. The Z-direction surface of insulating layer 51 and the surface covering the insulating film 54 are exposed within the cavity C.

[0079] Then, after exposing the Y-direction surface of the charge storage layer 62b by removing the insulating film 54 exposed in the cavity C, a silicon oxide film 53a and an aluminum oxide film 53b are sequentially formed on the Z-direction surface of the insulating layer 51 and the Y-direction surface of the charge storage layer 62b using methods such as thermal CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). Thus, as... Figure 12 As shown, a barrier insulating film 53 is formed inside the cavity C.

[0080] Next, as Figure 13As shown, a molybdenum nitride (MoN) film 80 is formed on the surface of an alumina film 53b using the ALD method. For example, in an environment of 300°C to 400°C, a molybdenum nitride film 80 is formed on the surface of the alumina film 53b by alternately circulating MoO2Cl2 gas as a material gas and ammonia (NH3) gas as a reducing gas into the cavity C. The molybdenum nitride film 80 has good adhesion to the alumina film 53b. Therefore, by forming the molybdenum nitride film 80 on the surface of the alumina film 53b before forming the molybdenum layer as a material of the conductive layer 52, a molybdenum layer can be easily formed relative to the alumina film 53b. In addition, the growth during molybdenum film formation can be reduced, and the coverage of the formed molybdenum film can be improved.

[0081] Next, a molybdenum layer is formed on the surface of the molybdenum nitride film 80 using the ALD method. For example, in an environment of about 600°C, a molybdenum layer is formed on the surface of the barrier insulating film 53 by alternately circulating MoO2Cl2 gas as a material gas and hydrogen (H2) gas as a reducing gas into the cavity C. At this time, the nitrogen contained in the molybdenum nitride layer 80, which is formed at a low temperature (300°C to 400°C), is removed from the film by heating it to the molybdenum film-forming temperature (600°C). As a result, the appearance becomes similar to that of a molybdenum layer formed only on an alumina film 53b, forming a structure like... Figure 5 The conductive layer 52 containing molybdenum is shown. The conductive layer 52 containing molybdenum is, for example, a layer of molybdenum monomers containing 99% or more of metallic molybdenum.

[0082] (Chlorine Concentration in Conductor Layer and Alumina Film) When the conductor layer 52 and the barrier insulating film 53 are formed using the manufacturing method described above, chlorine contained in the MoO2Cl2 gas used during the formation of the molybdenum nitride film 80 remains in the conductor layer 52 and the alumina film 53b, thereby forming portions with higher chlorine concentrations in the conductor layer 52 and the barrier insulating film 53. For example, in the conductor layer 52, portions with higher chlorine concentrations are formed in the areas where the molybdenum nitride film 80 is formed. This is based on the following reasons.

[0083] First, because the formation process of the molybdenum nitride film 80 is carried out at a low temperature of 300°C to 400°C, the probability of MoO2Cl2 molecules reacting with ammonia molecules is low. Therefore, in the portion where the molybdenum nitride film 80 is formed, the probability of chlorine removal due to the reaction is reduced. As a result, the chlorine content increases in the portion of the conductive layer 52 where the molybdenum nitride film 80 is formed.

[0084] Furthermore, ammonia is used as the reducing gas in the process of forming the molybdenum nitride film 80. In contrast, hydrogen is used as the reducing gas in the process of forming the conductive layer 52 containing molybdenum. Hydrogen molecules are less reactive with MoO2Cl2 molecules than ammonia molecules. As a result, the amount of chlorine in the portion forming the molybdenum nitride film 80 in the conductive layer 52 is increased.

[0085] The inventors and others experimentally determined the extent of chlorine present in the conductive layer 52 and the barrier insulating film 53 of the semiconductor device 2 in the embodiment. Specifically, as... Figure 7 As shown, the depth from the outer surface of the conductor layer 52 in the Y direction to any position inside the laminate 50 is defined as "D". p At that time, the chlorine concentration C was determined experimentally using SIMS (Secondary Ion Mass Spectrometry). Cl Relative to depth D p The distribution. In the... Figure 13 When the thickness of the molybdenum nitride film 80 shown is set to "Tm", the chlorine concentration C is measured for each case where the thickness Tm of the molybdenum nitride film 80 is 1.0 [nm], 2.0 [nm], 3.0 [nm], and 4.5 [nm]. Cl Distribution determination. Figure 14 It is a diagram that visualizes the results of experiments conducted by the inventors and others.

[0086] like Figure 14 As shown, in the conductive layer 52, the chlorine concentration is higher in the portion near the alumina film 53b, that is, in the portion where the molybdenum nitride film 80 is formed. Therefore, this portion with higher chlorine concentration in the conductive layer 52 forms a chlorine-rich portion 52a. The chlorine concentration C of the chlorine-rich portion 52a of the conductive layer 52 is... Cl The chlorine concentration C is higher than that of other parts 52b of the conductive layer 52. Cl high.

[0087] Furthermore, a portion of the alumina film 53b exhibits a higher chlorine concentration than the conductive layer 52. The inventors speculate that this is because chlorine contained in the MoO2Cl2 gas used to form the molybdenum nitride film 80 diffuses into the alumina film 53b.

[0088] Thus, a region with a high chlorine concentration is formed in the conductive layer 52 or the alumina film 53b. For this region with a high chlorine concentration, the chlorine concentration can, for example, reach a maximum value in the alumina film 53b. Figure 14 As shown, chlorine concentration C Cl The maximum value will vary depending on the thickness Tm of the molybdenum nitride film 80. Figure 15 This represents the maximum value C of the molybdenum nitride film 80, which is the thickness Tm.Cl，max A graph showing the relationship between the two. Figure 15 The measurement points P1 to P4 shown correspond to the thickness Tm of the molybdenum nitride film 80 being 1.0 nm, 2.0 nm, 3.0 nm, and 4.5 nm, respectively. Figure 15 As shown, the thicker the molybdenum nitride film 80 (Tm), the higher the maximum chlorine concentration (C). Cl，max The larger.

[0089] in addition, Figure 15 The extrapolation line M, representing the measurement points P1 to P4, is represented by a single-point chain. Within this extrapolation line M, the maximum chlorine concentration C is [value missing] when the thickness Tm of the molybdenum nitride film 80 is 0 nm. Cl，max Display 5.1×10 18 [atoms / cm 3 The maximum chlorine concentration C. Cl，max This is equivalent to the value when the conductive layer 52 is formed without setting the molybdenum nitride film 80. In other words, as described above, by forming the conductive layer 52 after setting the molybdenum nitride film 80, the maximum value of the chlorine concentration C can be achieved. Cl，max For greater than 5.1×10 18 [atoms / cm 3 The value of ].

[0090] (The relationship between chlorine concentration and data retention characteristics) was determined by the inventors through experiments. Figure 7 The chlorine concentration C at the interface 90 between the conductive layer 52 and the barrier insulating film 53 shown is... Cl，if With respect to the threshold voltage V of charge storage layer 62b inv The relationship between the offsets. Figure 16 This is a graph representing the results of experiments conducted by the inventors and others. Below, the chlorine concentration C at the interface between the conductive layer 52 and the barrier insulating film 53 is shown. Cl，if This is called "interfacial chlorine concentration C". Cl，if ".

[0091] like Figure 16 As shown, the interfacial chlorine concentration C Cl，if The higher the threshold voltage V of charge storage layer 62b, the higher the threshold voltage V. inv The smaller the offset, the lower the threshold voltage V of the charge storage layer 62b. inv The offset is related to the high-temperature data retention (HTDR) characteristic of the storage cell transistor MT. Specifically, the threshold voltage V of the charge storage layer 62b... inv The lower the offset, the better the HTDR characteristics. Therefore, from Figure 16 The curve shown indicates that the interfacial chlorine concentration C Cl，ifThe higher the concentration of chloride ions (C), the better the HTDR characteristics of the memory cell transistor (MT). This is considered to be influenced by the interfacial chloride concentration (C). Cl，if The higher the concentration of chlorine at the interface, the less likely it is to cause the so-called OH diffusion effect, where hydrogen and oxygen diffuse through the conductive layer 52 to the silicon oxide film 53a. In particular, if the interfacial chlorine concentration C... Cl，if 1.0×10 19 [atom / cm 3 The above can significantly improve the HTDR characteristics of the memory cell transistor MT. Furthermore, the hydrogen and oxygen diffused via OH diffusion contain oxygen atoms, oxygen ions, hydrogen atoms, hydrogen ions, and OH molecules.

[0092] As explained above, in the semiconductor device 2 of this embodiment, chlorine is included as an impurity to suppress OH diffusion in the region from the conductive layer 52 to the aluminum oxide film 53b. Figure 14 As shown, the chlorine concentration C of the chlorine-rich portion 52a of the conductive layer 52 is... Cl The chlorine concentration C of portion 52b of conductor layer 52 Cl High. Based on this configuration, a higher concentration of chlorine can be used to suppress OH diffusion from the conductive layer 52 to the silicon oxide film 53a, thus making it less likely for energy levels to form in the silicon oxide film 53a. Therefore, so-called charge leakage, where charge trapped by the charge storage layer 62b leaks into the silicon oxide film 53a, is less likely to occur, thus improving data retention compared to the past.

[0093] In the semiconductor device 2 of this embodiment, such as Figure 15 As shown, its maximum chlorine concentration C Cl，max Greater than 5.1×10 18 [atoms / cm 3 According to this configuration, more chlorine will be present in the alumina film 53b compared to when a molybdenum nitride film 80 is not used when forming the conductive layer 52, thus enabling more accurate suppression of OH diffusion. As a result, data retention characteristics can be improved more accurately.

[0094] The chlorine concentration C at the interface 90 between the conductive layer 52 and the barrier insulating film 53 Cl，if Preferably 1.0×10 19 [atoms / cm 3 That's all. Therefore, as... Figure 16 The threshold voltage V of the charge storage layer 62b is shown. inv The offset is further reduced, which means that the data retention characteristics can be significantly improved.

[0095] <Other Embodiments> The present invention is not limited to the specific examples described. For example, in the described embodiment, a maximum chlorine concentration C in the alumina film 53b is illustrated. Cl，maxGreater than 5.1×10 18 [atoms / cm 3 However, this can be substituted by having a chlorine concentration greater than 5.1 × 10⁻⁶ in the chlorine-rich portion 52a of the conductor layer 52. 18 [atoms / cm 3 ].

[0096] Chlorine concentration C Cl It can also have a maximum value in the conductive layer 52. Additionally, as... Figure 17 As shown, a chlorine-rich film 56 can also be formed between the conductive layer 52 and the alumina film 53b, and the chlorine concentration C at the interface between the conductive layer 52 and the alumina film 53b can be increased. Cl It has a maximum value. Therefore, the chlorine concentration C Cl It may not have a maximum value, but a chlorine concentration C exists near the interface 90 between the conductive layer 52 and the alumina film 53b. Cl The higher concentration. Consequently, the chlorine concentration C within the alumina film 53b. Cl It may not have a maximum value, but rather a gradient, such as the value increasing monotonically as it gets closer to the silicon oxide film 53a.

[0097] The impurity used to suppress OH diffusion is not limited to chlorine; silicon or titanium can also be used. For example, if SiH4 or SiH6 is used as the material gas, silicon can be added to the conductive layer 52 or the alumina film 53b. Alternatively, if TiCl4 is used as the material gas, titanium can be added to the conductive layer 52 or the alumina film 53b.

[0098] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor device comprising: a multilayer body having a structure in which multiple conductive layers and insulating layers are alternately deposited in a predetermined direction, and a memory aperture is formed therethrough in the predetermined direction; and a memory pillar formed within the memory aperture; the memory pillar having a structure in which a semiconductor portion, a tunnel insulating film, and a charge storage layer are sequentially deposited from its inner side to its outer side, and a barrier insulating film is disposed between the charge storage layer and the conductive layers, the conductive layer comprising molybdenum, and the barrier insulating film having: a first film disposed in contact with the charge storage layer; And a second film, disposed between the first film and the conductive layer; The region from the conductor layer to the second film contains impurities, and the concentration of impurities in the second part of the conductor layer, which is closer to the second film than the first part, is higher than the concentration of impurities in the first part of the conductor layer.

2. The semiconductor device according to claim 1, wherein the concentration of the impurity has a maximum value in the conductive layer.

3. The semiconductor device according to claim 1, wherein the concentration of the impurity has a maximum value in the second film.

4. The semiconductor device according to claim 1, wherein the concentration of the impurity has a maximum value at the interface between the conductor layer and the second film.

5. The semiconductor device according to any one of claims 1 to 4, wherein the impurity is chlorine.

6. The semiconductor device of claim 5, wherein the concentration of chlorine in the second part is greater than 5.1 × 10⁻⁶. 18 [atoms / cm 3 ].

7. The semiconductor device according to claim 5, wherein the concentration of chlorine at the interface between the conductive layer and the second film is 1.0 × 10⁻⁶. 19 [atoms / cm 3 ]above.

8. A method for manufacturing a semiconductor memory device, comprising forming a barrier insulating film by sequentially forming a first film and a second film on the surface of a charge storage layer, forming a molybdenum nitride film on the surface of the second film by alternately passing MoO2Cl2 gas and ammonia gas through the surface of the second film, forming a conductive layer containing molybdenum on the surface of the second film by alternately passing MoO2Cl2 gas and hydrogen gas through the molybdenum nitride film, wherein an impurity is contained in the region from the conductive layer to the second film, and the concentration of the impurity in the second part of the conductive layer, which is closer to the second film than the first part, is higher than the concentration of the first part of the conductive layer, and the concentration of Cl, which is the impurity, is extremely high in the second film.

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