Memory device and method of forming the same

Abstract

Embodiments of the present invention provide a memory device and a method of forming the same. The memory device includes a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are located above a substrate. The channel region is located between the source region and the drain region. The gate dielectric layer is located above the channel region. The MTJ stack is located above the gate dielectric layer. The MTJ stack includes a first ferromagnetic layer, a second ferromagnetic layer having a switchable magnetization, and a tunnel barrier layer located between the first and second ferromagnetic layers. The metal gate is located above the MTJ stack.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and more specifically, to memory devices and methods of forming the same. Background Technology

[0002] Many modern electronic devices contain electronic memory, such as hard disk drives (HDDs) or random access memory (RAM). Electronic memory can be volatile or non-volatile. Non-volatile memory retains its stored data when power is off, while volatile memory loses its data storage contents when power is off. Magnetic tunnel junctions (MTJs) can be used in hard disk drives and / or RAM, and are therefore promising candidates for next-generation memory solutions. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, a memory device is provided, comprising: a source region and a drain region located above a substrate; a channel region located between the source region and the drain region; a gate dielectric layer located above the channel region; a magnetic tunnel junction (MTJ) stack located above the gate dielectric layer, the MTJ stack including a first ferromagnetic layer, a second ferromagnetic layer having switchable magnetization, and a tunnel barrier layer located between the first ferromagnetic layer and the second ferromagnetic layer; and a metal gate located above the MTJ stack.

[0004] According to another aspect of the present invention, a memory device is provided, comprising: a magnetic tunnel junction (MTJ) structure located above a semiconductor channel region; a source region and a drain region located on opposite sides of the MTJ structure; and a gate located above the MTJ structure, wherein the capacitance of the MTJ structure has a binary value that can be switched by a voltage applied to the gate, and the drain current of the drain region depends on the capacitance of the MTJ structure.

[0005] According to another aspect of the present invention, a method for forming a memory device is provided, comprising: forming a semiconductor channel over a substrate; forming source / drain regions on opposite sides of the semiconductor channel; forming a gate dielectric layer on the semiconductor channel; forming a magnetic tunnel junction (MTJ) stack over the gate dielectric layer, the MTJ stack including a first ferromagnetic layer over the gate dielectric layer, a tunnel barrier layer over the first ferromagnetic layer, and a second ferromagnetic layer over the tunnel barrier layer; and forming a metal gate over the MTJ stack. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a cross-sectional view of an example IC structure including a MeFET-based memory device according to some embodiments of this disclosure.

[0008] Figure 2A This is a cross-sectional view illustrating a film stack of an MTJ stack in a MeFET-based memory device according to some embodiments of the present disclosure.

[0009] Figure 2B This is a cross-sectional view of a film stack showing the SAF layer in an MTJ stack according to some embodiments of the present disclosure.

[0010] Figure 3 This is a cross-sectional view of an example IC structure including a MeFET-based memory device according to some embodiments of this disclosure.

[0011] Figure 4A and Figure 4B The current-voltage characteristics of a MeFET-based memory device according to some embodiments of the present disclosure are shown.

[0012] Figure 5 This is a graph showing example simulation results of read operations of various MeFET-based memory devices in the saturation and subthreshold regions according to some embodiments of this disclosure.

[0013] Figure 6 Example overlapping layouts of various levels of an IC structure having multiple MeFET-based memory devices according to some embodiments of the present disclosure are shown.

[0014] Figure 7 and Figure 8 Some embodiments according to this disclosure are shown. Figure 6 Write and read operations on the circuit diagram of the IC structure.

[0015] Figure 9 Example overlapping layouts of various levels of an IC structure having multiple MeFET-based memory devices according to some embodiments of the present disclosure are shown.

[0016] Figure 10 and Figure 11 Some embodiments according to this disclosure are shown. Figure 9 Write and read operations on the circuit diagram of the IC structure.

[0017] Figures 12-18 This is a cross-sectional view of an intermediate stage in the fabrication of an IC structure having a MeFET memory device according to some embodiments of the present disclosure.

[0018] Figures 19-21This is a cross-sectional view of an intermediate stage in the fabrication of an IC structure having a MeFET memory device according to some embodiments of the present disclosure.

[0019] Figures 22A-25C These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure with a MeFET memory device using a gate-first process flow according to some embodiments of this disclosure.

[0020] Figures 26A-29C These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure with a MeFET memory device using a post-gate process flow according to some embodiments of this disclosure.

[0021] Figures 30A-35C These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure for a MeFET memory device in the form of a gate-all-around (GAA) device, according to some embodiments of this disclosure. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0024] Magnetoresistive random access memory (MRAM) cells typically comprise vertically arranged magnetic tunnel junction (MTJ) cells within an integrated back-end process (BEOL) between conductive electrodes. An MTJ cell includes a first ferromagnetic layer and a second ferromagnetic layer separated by a tunnel barrier layer. One of the ferromagnetic layers (often called the "reference layer" or "pinned layer") has a fixed magnetization direction (also known as magnetization orientation), while the other ferromagnetic layer (often called the "free layer") has a variable or switchable magnetization direction. For an MTJ cell with positive tunnel magnetoresistance (TMR), if the magnetization directions of the reference layer and the free layer are parallel, electrons are more likely to tunnel through the tunnel barrier layer, resulting in a low-resistance state for the MTJ cell. Conversely, if the magnetization directions of the reference layer and the free layer are antiparallel, electrons are less likely to tunnel through the tunnel barrier layer, resulting in a high-resistance state for the MTJ cell. Therefore, MTJ cells can typically switch between two resistance states using TMR, i.e., a first state with low resistance (R0). P (The magnetization directions of the reference layer and the free layer are parallel) and a second state with high resistance (R AP (The magnetization directions of the reference layer and the free layer are antiparallel). Due to their binary characteristics, MTJ cells can be used to store digital data, where the low-resistance state R... P Corresponding to the first data state (e.g., logic "0"), and the high resistance state R AP This corresponds to the second data state (e.g., logic "1").

[0025] In a spin-torque (“STT”) MRAM (“STT-MRAM”) cell, a write current is applied across the entire MTJ, i.e., the reference layer, tunnel barrier layer, and free layer. The MTJ sets the magnetization direction of the free layer via the spin-torque effect. Therefore, STT-MRAM cells typically suffer from tunnel barrier reliability degradation because both write and read currents pass through the thin tunnel barrier layer. In a spin-orbit torque (“SOT”) MRAM (“SOT-MRAM”) cell, the MTJ structure sits on a heavy metal layer with large spin-orbit interactions. Spin torque is caused by an in-plane current injected through the heavy metal layer under spin-orbit coupling effects, which generally include one or more of the Rashba effect or the spin Hall effect (“SHE effect”). The write current does not pass through the vertical MTJ. Instead, the write current passes through the heavy metal layer in a planar direction. The magnetization direction in the free layer is set by the SOT effect. More specifically, when current is injected in-plane within the heavy metal layer, spin-orbit coupling results in orthogonal spin currents, which generate spin torque and induce magnetization reversal in the free layer. SOT-MRAM cells typically require large write currents to induce magnetization reversal in the free layer, which in turn increases the size and power consumption of the MRAM cell.

[0026] In some embodiments, this disclosure provides a magnetoelectric field-effect transistor (MeFET) having an MTJ within the gate structure of a MeFET. The magnetization state of the MTJ can be switched between an antiparallel state (AP state) and a parallel state (P state) using voltage-controlled magnetic anisotropy (VCMA). Due to the tunnel magnetocapacitance (TMC) effect of the MTJ, the capacitance of the MTJ in the AP state is lower than that in the P state, therefore the MTJ can switch between two capacitance states, i.e., a first state with low capacitance (C). MTJ,AP (The magnetization directions of the reference layer and the free layer are antiparallel) and a second state with high capacitance (C MTJ,P (The magnetization directions of the reference layer and the free layer are parallel). The difference in MTJ capacitance leads to a difference in gate capacitance between the AP and P states, which in turn leads to a difference in the threshold voltage of the MeFET between the AP and P states, and consequently, a difference in the saturation current and / or subthreshold current of the MeFET between the AP and P states. Due to the binary nature of MTJ capacitance, MeFETs can be used as memory devices for storing digital data, especially in low MTJ capacitance states C. MTJ,AP Corresponding to the first data state (e.g., logic "0"), the high MTJ capacitor state C MTJ,P This corresponds to the second data state (e.g., logic "1"). MeFET-based memory devices can be operated using VCMA or a magnetic field without allowing current to pass through the tunnel barrier layer in the MTJ, thus MeFET-based memory devices offer improved tunnel barrier reliability and reduced power consumption compared to the MRAM devices discussed above.

[0027] Figure 1 This is a cross-sectional view of an example integrated circuit (IC) structure, including a substrate 100 in which one or more MeFET-based memory devices 10 are formed. According to some embodiments of this disclosure, portions of a multi-level interconnect structure (e.g., metal vias V0 and metal lines M1) are formed on the substrate. Typically, Figure 1 A MeFET-based memory device 10 in the form of a fin field-effect transistor (FinFET) is shown, comprising a semiconductor fin 102 extending from a substrate 100, an MTJ-containing gate structure (or MTJ-containing gate stack) 104 extending through the semiconductor fin 102, and source and drain regions 106 on opposite sides of the MTJ-containing gate structure 104. In some embodiments, the MeFET-based memory device may be in the form of a gate-all-around (GAA) FET, a planar FET, a complementary FET (CFET), etc.

[0028] Figure 1The substrate 100 shown may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate. Substrate 100 may include: semiconductor materials, such as elemental semiconductors including Si and Ge; compound or alloy semiconductors, including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; and combinations thereof. Substrate 200 may be doped or substantially undoped. In a specific example, substrate 200 is a bulk silicon substrate, which may be a wafer.

[0029] Figure 1 The MeFET-based memory device 10 shown is a three-dimensional MOSFET structure formed in a fin-like strip called a fin protrusion 102. Figure 1 The cross-section shown is along the longitudinal axis of the semiconductor fin 102 in a direction parallel to the source and drain regions 106 (collectively referred to as source / drain regions or S / D regions 106). The fin 102 can be formed by patterning the substrate using photolithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed over the substrate and patterned using suitable photolithography and etching processes to form a mandrel. Spacers are formed alongside the mandrel using a self-aligned process. The sacrificial layer is then removed using a suitable selective etching process. Each remaining spacer can then be used as a hard mask to pattern the corresponding fin 102 by etching trenches in the substrate 100 using, for example, reactive ion etching (RIE). Figure 1 A single fin 102 is shown, although the substrate 100 may include any number of fins.

[0030] The MTJ-containing gate structure 104 may have a longitudinal axis perpendicular to the longitudinal axis of the semiconductor fin 102. Therefore, the MTJ-containing gate structure 104 surrounds the semiconductor fin 102 on three sides. The MTJ-containing gate structure 104 includes a gate dielectric layer 108, a hard magnetic layer 110 on the gate dielectric layer 108, a tunnel barrier layer 112 on the hard magnetic layer 110, a soft magnetic layer 114 on the tunnel barrier layer 112, and a metal gate 118 above the soft magnetic layer 114. The hard magnetic layer 110, the tunnel barrier layer 112, and the soft magnetic layer 114 together serve as an MTJ stack 116. Each of the soft magnetic layer 114 and the hard magnetic layer 110 is capable of maintaining a magnetization direction. The magnetization direction of the soft layer 114 can be switched or changed by VCMA or by exposure to a magnetic field generated within the memory device 10 during operation. However, the magnetization direction of the hard magnetic layer 110 cannot be switched or changed after fabrication. Therefore, the hard magnetic layer 110 includes a ferromagnetic reference layer or pinning layer, while the soft magnetic layer 114 includes a ferromagnetic free layer. In some embodiments, the tunnel barrier layer 112 has a greater thickness than the hard magnetic layer 110 and / or the soft magnetic layer 114. For example, the thickness of the tunnel barrier layer 112 is in the range of about 0.5 nm to about 50 nm, and the thickness of the soft magnetic layer 114 is in the range of about 0.5 nm to about 10 nm, and the thickness of the hard magnetic layer 110 is in the range of about 0.5 nm to about 30 nm. In some embodiments, the total thickness of the MTJ stack 116 is in the range of about 22 nm to about 36 nm.

[0031] Figure 2A This is a cross-sectional view illustrating a film stack 116 of an MTJ stack according to some embodiments of the present disclosure. The MTJ stack 116 includes a bottom electrode 211 located above a gate dielectric layer 108. In some embodiments, the bottom electrode 211 includes Ta, TaN, TiN, W, Ru, etc., and / or alloys thereof. The thickness of the bottom electrode 211 is in the range of about 1 nm to about 50 nm. In some embodiments, the bottom electrode 211 is a dummy electrode because it is not electrically coupled to the upper metal gate 118 and the lower fin 102. The MTJ stack 116 also includes a seed layer 212 above the bottom electrode 211. The seed layer 212 includes Pt, Ta, Ru, etc., and / or alloys thereof, and has a thickness in the range of about 1 nm to about 50 nm.

[0032] The MTJ stack 116 also includes a pinning layer 213 formed above the seed layer 212. In some embodiments, the pinning layer 213 is a synthetic antiferromagnetic (SAF) layer. The SAF layer 213 can be used to fix the magnetization direction of the reference layer 215 in a fixed direction. Fixing the magnetization direction of the reference layer 215 allows the MTJ stack 116 to switch between a low-capacitance state and a high-capacitance state by changing the magnetization direction of the free layer 216 relative to the reference layer 215.

[0033] In some embodiments, SAF layer 213 may include multiple layers of different materials. For example, SAF layer 213 may include a stack of one or more ferromagnetic layers and one or more non-magnetic layers. For example, as Figure 2B As shown, SAF layer 213 may include two ferromagnetic layers 218 and 220, with a nonmagnetic spacer layer 219 sandwiched between the ferromagnetic layers 218 and 220, or SAF layer 213 may be alternating nonmagnetic and ferromagnetic layers. In some embodiments, ferromagnetic layers 218 and 220 may be formed of materials such as Co, Pt, Fe, Ni, CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, or combinations thereof. For example, ferromagnetic layers 218 and 220 are both multilayer structures made of (Co / Pt)n, (Co / Ni)n, etc., where n is the number of layers (e.g., n ranges from about 1 to 20), and the total thickness of the multilayer structure is in the range of about 0.1 nm to about 100 nm. In some embodiments, nonmagnetic spacer layer 219 may be formed of materials such as Ru, Ir, W, Ta, Mg, etc., or combinations thereof, and includes a thickness in the range of about 0.1 nm to about 5 nm. In some embodiments, a thicker SAF layer 213 may have stronger antiferromagnetic properties or be more robust against external magnetic fields or thermal fluctuations.

[0034] The MTJ stack 116 also includes a metal spacer layer 214 formed over the pinning layer 213. In some embodiments, the metal spacer layer 214 may be formed of a material such as Ta, W, Mo, or combinations thereof, and includes a thickness ranging from about 0.1 nm to about 5 nm. The MTJ stack 116 includes a reference layer 215 formed over the metal spacer layer 214. The reference layer 215 may be a ferromagnetic layer formed of a ferromagnetic material, such as one or more layers of Fe, Co, CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, or combinations thereof. The thickness of the reference layer 215 ranges from about 0.1 nm to about 10 nm. The ferromagnetic reference layer 215 has a “fixed” magnetization direction because the magnetization direction of the reference layer 215 is pinned by the pinning layer 213.

[0035] The MTJ stack 116 includes a tunnel barrier layer 112 formed above the reference layer 215. The thickness of the tunnel barrier layer 112 is sufficient to prevent quantum mechanical tunneling of current between the ferromagnetic reference layer 215 and the ferromagnetic free layer 216. As a result, the MTJ stack 116 can operate using VCMA without current flowing through the MTJ stack (i.e., tunneling through the tunnel barrier layer 112). Specifically, when a VCMA voltage source is coupled to the free layer 216, the VCMA voltage source essentially applies a VCMA voltage to the tunnel barrier layer 112. In some embodiments, the VCMA voltage is large enough to overcome / eliminate the energy barrier accumulated by the tunnel barrier layer 112, which prevents switching between the AP and P states of the MTJ stack 116. Meanwhile, the VCMA voltage is not as large as in STT-MRAM and / or SOT-MRAM configurations to break down the dielectric barrier of the tunnel barrier layer 112. Therefore, in some embodiments, the tunnel barrier layer 112 has a greater thickness than the STT-MRAM device and / or the SOT-MRAM device, which relies on a thin tunnel barrier to allow quantum mechanical tunneling of current through it. Specifically, the tunnel barrier in the STT-MRAM device and / or the SOT-MRAM device may have a smaller thickness than the free layer and the reference layer. Conversely, in some embodiments of this disclosure, the tunnel barrier layer 112 may have a greater thickness than the free layer 216 and / or the reference layer 215 to suppress current tunneling through the tunnel barrier layer 112. In some embodiments, the tunnel barrier layer 112 may therefore be the thickest layer among all layers in the MTJ stack 116. Due to the thick tunnel barrier layer 112, VCMA can be used to write to the MTJ stack 116 without current tunneling through the tunnel barrier layer 112. In embodiments, the thickness of the tunnel barrier layer 112 is in the range of about 0.5 nm to about 50 nm. In some embodiments, the tunnel barrier layer 112 may include a crystalline barrier, such as magnesium oxide (MgO) or spinel (MgAl2O4, also known as MAO); or an amorphous barrier layer, such as aluminum oxide (AlO2). x ) or titanium dioxide (TiO) x In some embodiments where the tunnel barrier layer 112 is monocrystalline MgO, the relative permittivity (i.e., dielectric constant) of the MgO layer is typically about 9.9. If the MgO layer is very thin (e.g., about 3 nm), it will exhibit polycrystalline properties and have a relative permittivity of about 80.

[0036] The MTJ stack 116 includes a free layer 216 having a magnetization intensity that can be freely switched by either VCMA or a magnetic field without current tunneling through the tunnel barrier layer 112. Therefore, the free layer 216 can change its magnetization direction between two magnetization states, resulting in two different MTJ capacitances corresponding to binary data states. For example, utilizing the VCMA effect, an electric field is used to switch the MTJ states. This occurs due to the accumulation of electron charge induced by the electric field, which alters the occupancy of atomic orbitals at the free layer interface. This interaction with the spin orbitals leads to a change in magnetic anisotropy. More specifically, the two stable magnetization states of the free layer 216 are separated by an energy barrier (E0). b The layers are spaced apart. When a negative VCMA voltage is applied to the free layer 216 of the MTJ stack 116, the magnitude of the voltage is equal to or greater than the critical voltage (V). c ), critical voltage (V c The minimum voltage required to eliminate the energy barrier of the MTJ is VCMA. Without the energy barrier, the magnetization (M) of the free layer 216 enters a precession process, oscillating between two stable states (i.e., the P state and the AP state). Removing the VCMA voltage ends the precession. By using a controlled timing of the VCMA voltage removal, where the removal voltage corresponds to the magnetization position at the end of the precession process, the magnetization of the free layer 216 will deterministically stabilize at either the AP or P state. Specifically, after removing the VCMA voltage to end the precession, the magnetization of the free layer 216 will stabilize in the vertical direction adjacent to the precession end position. As a result, the magnetization state of the MTJ stack 116 can be switched or controlled by the duration of the VCMA voltage pulse.

[0037] In some embodiments, the free layer 216 may be a ferromagnetic layer formed, for example, of a ferromagnetic material such as iron, nickel, cobalt, and alloys thereof. For example, in some embodiments, the free layer 216 may include cobalt, iron, and boron, such as a CoFeB ferromagnetic free layer. In some embodiments, the free layer 216 is a multilayer structure of a stack comprising a CoFeB layer, a metal spacer layer, and another CoFeB layer. In some embodiments, the orientation of the easy magnetization axis of the reference layer 215 and the free layer 216 is in-plane (i.e., parallel to the top and bottom surfaces of the stack). In some other embodiments, the orientation of the easy magnetization axis of the reference layer 214 and the free layer 216 is perpendicular (i.e., perpendicular to the top and bottom surfaces of the stack). The MTJ stack 116 also includes a capping layer 217 formed over the free layer 216. In some embodiments, the capping layer 217 comprises Ta, Ru, MgO, or combinations thereof. In some embodiments, the geometry of the MTJ stack 116 includes rectangles, squares, etc., and the geometry of the MTJ stack 116 may have rounded corners. In some embodiments, the MTJ stack 116 has a junction size ranging from about 1 nm to about 1 μm. In some embodiments, each layer of the MTJ stack 116 may be formed by PVD, ALD, CVD and / or other suitable deposition techniques.

[0038] In some embodiments, Figure 1The gate dielectric layer 108 shown is used to electrically isolate the MTJ stack 116 from the semiconductor fin 102, such that the MTJ stack 116 can be controlled by a VCMA voltage applied by the metal gate 118. The gate dielectric layer 108 includes an interface layer and a high-k dielectric layer above the interface layer. As used and described herein, a high-k dielectric includes a dielectric material having a high dielectric constant, for example, greater than that of thermally heated silicon oxide (~3.9). The interface layer of the gate dielectric layer 108 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 108 may include hafnium oxide (HfO2). Optionally, the gate dielectric layer 108 may include other high-k dielectric materials, such as hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (La2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0039] In some embodiments, Figure 1 The metal gate 118 shown is a transistor gate terminal and can be used as a VCMA voltage source to apply a VCMA voltage to the MTJ stack 116, particularly to the soft magnetic layer 114 in contact with the metal gate 118. In some other embodiments, a hard magnetic layer 110 is disposed above the tunnel barrier layer 112 and a soft magnetic layer 114 is disposed below the tunnel barrier layer 112. In this case, the metal gate 118 contacts the hard magnetic layer 110 to apply a VCMA voltage to the MTJ stack 116. When the gate voltage is large enough to eliminate the energy barrier of the MTJ stack 116, the magnetization state of the MTJ stack 116 can switch from the P state to the AP state (also known as a P-to-AP switch) or from the AP state to the P state (also known as an AP-to-P switch), which in turn enables write operations of the memory device 10. In some embodiments, the free layer 216 of the soft magnetic layer 114 may be more stable in the AP state than in the P state, resulting in an energy barrier asymmetry between the AP and P states. In this case, the P-to-AP switch can be triggered by a lower gate voltage than the AP-to-P switch.

[0040] In some embodiments, the metal gate 118 includes one or more n-type work function metal (N-metal) layers and / or one or more p-type work function metal (P-metal) layers. The n-type work function metal may, exemplarily, include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC), tungsten carbide (WC)), aluminum compounds, and / or other suitable materials. The p-type work function metal may, exemplarily, include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. The metal gate 118 may also include fill metal to fill the remaining recess defined by the U-shaped MTJ stack 116. The filler metal may include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0041] In such Figure 1 In some embodiments shown, each of the gate dielectric layer 108, hard magnetic layer 110, tunnel barrier layer 112, and soft magnetic layer 114 has a U-shaped cross-section. This is because the MTJ-containing gate stack 104 is formed using a post-gate process flow, which will be described in more detail below. In some other embodiments where the MTJ-containing gate stack 104 is formed using a pre-gate process flow, each of the gate dielectric layer 108, hard magnetic layer 110, tunnel barrier layer 112, and soft magnetic layer 114 has a linear cross-section, such as... Figure 3 As shown.

[0042] Figure 1The source / drain region 106 and gate spacer 120 shown are formed, for example, in self-alignment with the MTJ-containing gate structure 104. The gate spacer 120 may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof. The gate spacer 120 is used to laterally space the MTJ-containing gate structure 104 from the source / drain region 106. The source / drain region 106 is a semiconductor region in direct contact with the semiconductor fin 102. In some embodiments, the source / drain region 106 may include an epitaxial growth region. For example, after forming the gate spacer 120, a raised source / drain epitaxial structure 106 can be formed by first etching the fin 102 to form a recess, and then filling the recess with a crystalline semiconductor material through a selective epitaxial growth (SEG) process, which may extend beyond the original surface of the fin 102, to form a source / drain region 106 self-aligned with the spacer 120, such as... Figure 1 As shown. Crystalline semiconductor materials can be elements (e.g., Si or Ge, etc.) or alloys (e.g., Si). 1-x C x or Si 1-x Ge x (etc.). SEG processes can utilize any suitable epitaxial growth method, such as vapor phase / solid phase / liquid phase epitaxy (VPE, SPE, LPE) or metal-organic CVD (MOCVD) or molecular beam epitaxy (MBE), etc. Appropriate doses (e.g., from about 10) can be applied in situ during SEG or via an ion implantation process performed after SEG, or by a combination thereof. 17 cm -2 Up to 10 22 cm -2 The dopant is introduced into the source / drain region 106. In some embodiments, the geometry of the source / drain region 106 may be rhomboid, circular, polygonal, etc., and the source / drain region 106 may have rounded corners.

[0043] Semiconductor fin 102 serves as a transistor channel region extending between source / drain regions 106. The source-drain current depends on the transistor's threshold voltage, which in turn depends on the gate capacitance of the gate structure 104. Furthermore, the gate capacitance depends on the MTJ capacitance, which has binary values ​​corresponding to the AP and P states, respectively. As a result, for the same given gate voltage, the source-drain current obtained when the MTJ stack 116 is in the AP state can differ from the source-drain current obtained when the MTJ stack 116 is in the P state. Such a difference in source-drain current can be used to identify the magnetization state of the MTJ stack 116, thereby allowing the data state of the MeFET-based memory device 10 to be read out using the source-drain current.

[0044] Specifically, the total gate capacitance C of the gate structure 104 total Including the series-connected gate dielectric capacitance C ox and MTJ capacitor C MTJ Therefore, their relationship can be expressed as: 1 / C total =1 / C ox +1 / C MTJ Therefore, MTJ capacitor C MTJ With gate capacitance C total They are positively correlated. Furthermore, the threshold voltage (V) of the transistor... t ) and gate capacitance C total The source-drain currents (e.g., drain saturation current I) are negatively correlated. dsat The MTJ capacitance is negatively correlated with the transistor's threshold voltage. Therefore, the lower the MTJ capacitance, the smaller the source-drain current generated; the higher the MTJ capacitance, the larger the source-drain current generated. Since the MTJ capacitance in the AP state is typically lower than that in the P state, the MeFET-based memory device 10 may have a smaller source-drain current corresponding to the first data state (e.g., logic "0") and a larger source-drain current corresponding to the second data state (e.g., logic "1") during a read operation.

[0045] Figure 4A and Figure 4B MeFET-based memory devices are shown (e.g., such as...). Figure 1 or Figure 3 The current-voltage characteristics of the memory device 10 shown are as follows: Figure 4A It focuses on the current-voltage characteristics in the saturation region, and Figure 4B The focus is on the current-voltage characteristics in the subthreshold region. Figure 4A and Figure 4B In the middle, the logarithmic drain current (LogI) d The gate-source voltage (V) is displayed on the vertical axis. GS (This is displayed on the horizontal axis.) Figure 4A As shown, when a MeFET-based memory device operates in the saturation region with a given gate-source voltage V1, there is a distinguishable drain saturation current ratio or difference between the P-state and AP-state. Figure 4B As shown, when a MeFET-based memory device operates in the subthreshold region with a given gate-source voltage V2 less than V1, a distinguishable subthreshold drain current ratio or difference exists between the P-state and AP-state. Therefore, read operations of the MeFET-based memory device can be performed in the saturation region and / or the subthreshold region. Furthermore, a comparison... Figure 4B and Figure 4AThe subthreshold drain current ratio between the P state and the AP state may be greater than the drain saturation current ratio between the P state and the AP state. Therefore, according to some embodiments of the read operation of the MeFET-based memory device of this disclosure, the read window performed in the subthreshold region may have a larger read window than the read window performed in the saturation region.

[0046] Figure 5 This is a graph illustrating example simulation results of read operations in the saturation and subthreshold regions of various MeFET-based memory devices according to some embodiments of this disclosure. Figure 5 In the diagram, column 1 shows the magnetization state of the MTJ in the MeFET-based memory device, column 2 shows the MTJ capacitance of the MeFET-based memory device, column 3 shows the total gate capacitance of the MeFET-based memory device, and column 4 shows the AP state threshold voltage (V). TH,AP ) and P-state threshold voltage (V TH,P ), column 5 shows the drain saturation current (I) in P state. dsat,P ) and AP state drain saturation current (I dsat,AP The ratio of the P-state subthreshold drain current (Ip) is shown in column 6. sub,P ) and AP state subthreshold drain current (I sub,AP The ratio of ).

[0047] Line 1 includes simulation results for a first MeFET-based memory device having a tunnel barrier (e.g., MgO) thickness in the range of 5 nm to about 7 nm (e.g., about 6 nm), and a thickness in the range of about 116 fF / µm. 2 Up to approximately 118 fF / um 2 Within the range (e.g., approximately 117.5 fF / um) 2 AP state MTJ capacitor C MTJ,AP The tunnel magnetic capacitance (TMC) ranges from approximately 90% to approximately 100% (e.g., approximately 100%), with a value ranging from approximately 38 fF / µm. 2 Up to approximately 39 fF / um 2 Within the range (e.g., 38.4 fF / um) 2 The gate dielectric capacitance C ox And the equivalent oxide thickness (EOT) in the range of approximately 0.85 nm to approximately 0.95 nm (e.g., approximately 0.9 nm). The TMC percentage can be expressed as: TMC = (C MTJ,P -C MTJ,AP ) / C MTJ,AP ×100%.

[0048] Line 2 includes simulation results for the second MeFET-based memory device. The second MeFET-based memory device has similar conditions to the first MeFET-based memory device discussed previously with respect to line 1, except that the second MeFET-based memory device has a smaller EOT in the range of about 0.37 nm to about 0.41 nm (e.g., about 0.39 nm), and therefore has a value in the range of about 88 fF / µm. 2 Up to approximately 89 fF / um 2 Within the range (e.g., 88.5fF / um) 2 The larger gate dielectric capacitance C) ox Comparing the simulation results in rows 2 and 1, it can be observed that the reduction in gate dielectric thickness leads to a slight increase in the ratio of P-state drain saturation current to AP-state drain saturation current (e.g., the ratio increases from approximately 1.41 to approximately 1.58), and almost no increase in the ratio of P-state subthreshold drain current to AP-state subthreshold drain current (e.g., the ratio remains at approximately 3.3). The simulation results suggest that a reduction in gate dielectric thickness may result in a slight improvement in the read window during read operations performed in the saturation region, and may result in no improvement or negligible improvement in the read window during read operations performed in the subthreshold region.

[0049] Line 3 includes simulation results for a third MeFET-based memory device. This third MeFET-based memory device has similar conditions to the second MeFET-based memory device discussed previously in line 2, except that it has a larger tunnel barrier thickness in the range of approximately 17 nm to approximately 19 nm (e.g., approximately 18 nm), and therefore a smaller MTJ capacitance. For example, the third MeFET-based memory device has a capacitance ranging from approximately 38 fF / µm. 2 Up to approximately 40 fF / um 2 Within the range (e.g., approximately 39.17 fF / um) 2 AP state MTJ capacitor C MTJ,AP Comparing the simulation results in rows 3 and 2, it can be observed that increasing the tunnel barrier thickness leads to a significant increase in the ratio of P-state drain saturation current to AP-state drain saturation current (e.g., from approximately 1.58 to approximately 2.75), and also a significant increase in the ratio of P-state subthreshold drain current to AP-state subthreshold drain current (e.g., from approximately 3.3 to approximately 36). The simulation results suggest that increasing the tunnel barrier thickness may lead to a significant improvement in the read window during read operations performed in the saturation or subthreshold regions.

[0050] Line 4 includes simulation results for the fourth MeFET-based memory device. The fourth MeFET-based memory device has similar conditions to the third MeFET-based memory device discussed earlier in line 3, except that the fourth MeFET-based memory device has a larger TMC percentage in the range of approximately 180% to approximately 200% (e.g., approximately 200%), meaning that the fourth MeFET-based memory device may have a higher MTJ capacitance C in the P-state. MTJ,P and AP state MTJ capacitor C MTJ,AP There is a greater difference between them, and / or a smaller AP state MTJ capacitance C MTJ,AP The TMC percentage depends on the material of the MTJ stack and can therefore be controlled by selecting an appropriate material for the MTJ stack. Comparing the simulation results in rows 4 and 3, it can be observed that increasing the TMC percentage leads to a significant increase in the ratio of P-state drain saturation current to AP-state drain saturation current (e.g., from approximately 2.75 to approximately 3.93), and also a significant increase in the ratio of P-state subthreshold drain current to AP-state subthreshold drain current (e.g., from approximately 36 to approximately 118). Simulation results indicate that increasing the TMC percentage may result in a significant improvement in the read window during read operations performed in the saturation or subthreshold regions.

[0051] based on Figure 5 The simulation results shown, especially rows 2 and 3, indicate that the MTJ capacitance C in the AP state is affected. MTJ,AP and P-state MTJ capacitor C MTJ,P One or two of them are smaller than the gate dielectric capacitance C. OX This leads to a significant improvement in the ratio of P-state drain saturation current to AP-state drain saturation current, and the ratio of P-state subthreshold drain current to AP-state subthreshold drain current. This is likely because a smaller MTJ capacitance can dominate the total gate capacitance more significantly than a larger MTJ capacitance. Furthermore, increasing the tunnel barrier thickness can reduce the MTJ capacitance. Therefore, in some embodiments, the tunnel barrier layer can be the thickest layer among all layers in the gate structure.

[0052] Return to reference Figure 1The source / drain region 106 of the MeFET-based memory device 10 can be electrically connected to conductive components of the first interconnect layer MLI1 using conductive connectors (e.g., source / drain contacts 122). In some embodiments, the source / drain contacts 122 comprise a suitable metal, such as W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, etc. Depending on the back-end process (BEOL) scheme employed in the integrated circuit design, multiple interconnect layers are formed above the source / drain contacts 122 and the MTJ gate structure 104. Each interconnect layer includes a conductive via extending in the vertical direction and a conductor extending in the lateral direction. Typically, the conductive via conducts current vertically and is used to electrically connect two conductive components located in vertically adjacent layers, while the conductor conducts current laterally and is used to distribute electrical signals and power within a layer.

[0053] exist Figure 1 The diagram shows the bottommost of a plurality of interconnect layers. The bottommost interconnect layer ML1 includes a plurality of conductive vias V0 extending vertically over the MTJ gate structure 104 and source / drain contacts 122, and a plurality of conductors M1 extending laterally over the plurality of conductive vias V0. The conductive vias V0 include a gate via 124 formed over the MTJ gate structure 104, and a source / drain via 126 formed over the source / drain contacts 122. The gate via 124 electrically connects the metal gate 118 of the MTJ gate structure 104 to word lines of the plurality of conductors M1, thereby applying word line voltages to the metal gate 118 for writing and / or reading the MeFET-based memory device 10. In some embodiments, the gate via 124 is positioned over the metal gate 118, so that the MTJ stack 116 and the gate dielectric layer 108 are spaced apart from the gate via 124. Source / drain vias 126 electrically connect source / drain contacts 122 to the bit lines and source lines of a plurality of conductors M1, respectively, for performing write and / or read operations on the MeFET-based memory device 10. In some embodiments, the word lines, bit lines, and source lines are located at the upper interconnect level above the bottom interconnect level ML1.

[0054] Figure 6 Example overlapping layouts of various levels of an IC structure having multiple MeFET-based memory devices 10 according to some embodiments of the present disclosure are shown. Figure 6A 2×2 array (i.e., two columns × two rows) of MeFET-based memory devices 10 is shown for illustrative purposes only and is not intended to limit the scope of this disclosure. MeFET-based memory devices 10 in the same row may share the same active region (e.g., semiconductor fins 102 or semiconductor nanosheets or nanowires, which will be discussed in detail below). MeFET-based memory devices 10 in the same column may share the same MTJ-containing gate structure 104. In the top view, the semiconductor fins 102 extend along a first direction (i.e., the X direction), and the MTJ-containing gate structure 104 and source / drain contacts 122 extend along a second direction (i.e., the Y direction) different from the first direction. In some embodiments, the first direction is perpendicular to the second direction. Word lines WL extend along the Y direction directly above the MTJ-containing gate structure 104, so that the word lines WL and the MTJ-containing gate structure 104 extend along the same direction and together resemble an overlapping rectangular pattern with parallel longitudinal axes in the top view. In some embodiments, the width of the MTJ-containing gate structure 104 in the X direction is smaller than the width of the word lines WL in the X direction. Therefore, as Figure 6 As shown, the MTJ gate structure 104 can extend laterally across the opposite longitudinal side of the word line WL. In some embodiments, the conductor M1 overlapping with the corresponding source / drain via 126 can be a bit line and a source line, or the conductor M1 can be electrically coupled to a bit line and a source line of an upper interconnect layer. The conductor M1 overlapping with the source / drain via 126 has a different top-view profile than the word line WL. For example, from a top view, the word line WL resembles a rectangular pattern extending in the Y direction, while the conductor M1 overlapping with the source / drain via 126 resembles a square pattern. The conductor M1 overlapping with the source / drain via 126 therefore has a Y-direction dimension smaller than the length of the word line WL measured in the Y direction.

[0055] Figure 7 and Figure 8 Some embodiments according to this disclosure are shown. Figure 6 The write and read operations of the IC structure circuit diagram. Figure 7 and Figure 8 In the IC structure, there are multiple word lines (e.g., WL_1, WL_2, ..., and WL_N), each word line is electrically coupled to the gate structure of the MeFET-based memory device 10 in the same column, multiple source lines (e.g., SL_1, SL_2, ..., and SL_M) are electrically coupled to the source regions of the MeFET-based memory device 10 in the same row, and multiple bit lines (e.g., BL_1, BL_2, ..., and BL_M) are electrically coupled to the drain regions of the MeFET-based memory device 10 in the same row.

[0056] exist Figure 7In the write operation of the MeFET-based memory device 10 coupled to the word line WL_N, source line SL_1, and bit line BL_1, a negative voltage (e.g., -V) will be applied. DD The negative voltage applied to the word line WL_N, source line SL_1, and bit line BL_1 is grounded. The negative voltage applied to the free layer FL in the corresponding gate structure 104 can eliminate the energy barrier of the MTJ stack in the gate structure 104 through VCMA, thereby switching the magnetization direction of the free layer of the MTJ stack in the gate structure 104 (in...). Figure 7 (referred to as FL in Chinese). Figure 7 In the illustrated embodiment, the free layer FL is electrically coupled to the word line WL_N, and the reference layer (denoted as PL) is electrically isolated from the word line WL_N. However, in some other embodiments, the word line WL_N may be electrically coupled to the reference layer PL and isolated from the free layer FL. In this case, the reference layer PL is formed on top of the free layer FL and is positively voltaged (e.g., +V). DD A write operation is triggered by applying a value to the word line WL_N.

[0057] exist Figure 8 In a read operation of a MeFET-based memory device 10 connected to word line WL_N, source line SL_1, and bit line BL_1, the word line voltage VWL (e.g., +V) is... DD The voltage V is applied to word line WL_N and read. read A bit line BL_1 is applied, and the source line SL_1 is grounded. A voltage V is applied to the gate structure 104. DD This allows the MeFET-based memory device 10 to operate in the saturation region, thereby generating a drain saturation current I for reading the data state of the MeFET-based memory device 10. dsat Optionally, the word line voltage V is lower than the threshold voltage of the MeFET-based memory device 10. WL The voltage V is applied to word line WL_N and read. read The word line voltage V is applied to bit line BL_1, and the source line SL_1 is grounded. This is lower than the threshold voltage of the MeFET-based memory device 10. WL This allows the MeFET-based memory device 10 to operate in the subthreshold region, thereby generating a subthreshold drain current (I0). sub () for reading MeFET-based memory device 10.

[0058] Figure 9 Example overlapping layouts of various levels of an IC structure having multiple MeFET-based memory devices 10 according to some embodiments of the present disclosure are shown. The IC structure has... Figure 6The IC structure shown includes similar components and arrangements, but in addition to the IC structure, it also includes write word lines (WWLs) disposed above but electrically isolated from the MTJ-containing gate structure 104. In such embodiments, the magnetization direction of the free layer in the MTJ stack of each gate structure 104 is switched by using a magnetic field generated by a current flowing in the corresponding write word line (WWL). The write word line (WWL) can therefore be referred to as a magnetic field induction structure, and may have a top-view dimension (e.g., length, width, or diameter) ranging from about 0.1 nm to about 1 μm. In some embodiments, the write word line (WWL) extends directly above the corresponding MTJ-containing gate structure 104 along the Y direction, so that the write word line (WWL) and the corresponding MTJ-containing gate structure 104 extend in the same direction and together resemble an overlapping rectangular pattern having parallel longitudinal axes in top view. In some embodiments, the width of the MTJ-containing gate structure 104 in the X direction is smaller than the width of the write word line (WWL) in the X direction. Therefore, as Figure 9 As shown, the MTJ gate structure 104 can extend laterally across the opposite longitudinal side of the write word line WWL.

[0059] In addition, Figure 9 In this configuration, a gate via 124 electrically connects each gate structure 104 to a read word line RWL. The read word line RWL is used to apply voltage to the corresponding gate structure 104 during a read operation, but not during a write operation. The read word line RWL partially overlaps with a region of the gate structure 104 and has a smaller top-view area than the write word line WWL. For example, from a top view, the write word line WWL resembles a rectangular pattern extending along the Y direction, while the read word line RWL resembles a square pattern spaced Y-direction distance from the rectangular pattern of the write word line. From a top view, the gate via 124 is located within and spaced apart from the write word line WWL to electrically couple the gate structure 104 to the read word line RWL instead of the write word line WWL.

[0060] Figure 10 and Figure 11 Some embodiments according to this disclosure are shown. Figure 9 The circuit diagram of the IC structure includes write and read operations. This circuit diagram has... Figures 7-8 The circuit diagram shown uses similar components and configurations, except that the IC structure has a write word line WWL for writing to the MeFET-based memory device 10 in the same column and a read word line RWL for reading from the MeFET-based memory device 10 in that column. Figure 10 In the write operation of the MeFET-based memory device 10 connected to the read word line RWL, source line SL_1, and bit line BL_1, a write word line voltage (e.g., +V) is applied. DD or -V DDThe write word line WWL and source line SL_1 are connected to ground, while the bit line BL_1 and read word line RWL are connected to ground. The write word line voltage generates a current in the write word line WWL, producing a sufficiently large magnetic field to switch the magnetization direction of the free layer FL of the corresponding MTJ stack in the gate structure 104.

[0061] exist Figure 11 In the read operation of a MeFET-based memory device 10 connected to the read word line RWL, source line SL_1, and bit line BL_1, the read word line voltage V... RWL (For example, +V) DD The read voltage V is applied to the read word line RWL. read Apply ground to bit line BL_1, source line SL_1, and write word line WWL. Apply V to gate structure 104. DD This allows the MeFET-based memory device 10 to operate in the saturation region, thereby generating a drain saturation current I for reading the data state of the MeFET-based memory device 10. dsat Optionally, the read word line voltage V is lower than the threshold voltage of the MeFET-based memory device 10. RWL The read voltage V is applied to the read word line RWL. read The bit line BL_1 is applied, and the source line SL_1 is grounded. Read the word line voltage V. RWL A voltage below the threshold voltage of the MeFET-based memory device 10 allows the MeFET-based memory device 10 to operate in the subthreshold region, thereby generating a subthreshold drain current (I0) for reading the data state. sub ).

[0062] Figures 12-18 This is a cross-sectional view of an intermediate stage in the fabrication of an IC structure having a MeFET memory device according to some embodiments of the present disclosure. The fabrication process steps can be used to manufacture, for example... Figure 1 The IC structure shown is understandable. Figures 12-18 Additional operations are provided before, during, and after the process shown. In other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0063] Figure 12 An initial structure including substrate 100 is shown. Substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a fully depleted semiconductor-on-insulator (FD-SOI) substrate, etc., and may be doped (e.g., with p-type or n-type dopants) or undoped. Further details regarding substrate 100 are provided above regarding... Figure 1 The discussion has been conducted, so for the sake of brevity, it will not be repeated. Figure 12Fins 102 formed in substrate 100 are also shown. In some embodiments, fins 102 can be formed in substrate 100 by etching trenches in substrate 100. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0064] The fin can be patterned using any suitable method. For example, the fin 102 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning combines photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fin can then be patterned using the remaining spacers. In some embodiments, a mask (or other layer) may be retained on the fin 102.

[0065] Once the fins 102 are formed, an insulating material 103 is formed over the substrate 100 and between adjacent fins 102. The insulating material 103 can be an oxide, such as silicon oxide, nitrides, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 103 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material 103 is formed such that excess insulating material 103 covers the fins 102. Although the insulating material 103 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a pad (not shown) may first be formed along the surfaces of the substrate 100 and the fins 102. Subsequently, a filler material such as those described above may be formed over the pad.

[0066] Once the insulating material 103 is deposited on top of the fin 102, a removal process is applied to the insulating material 103 to remove excess insulating material 103 from the fin 102. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., can be used. The planarization process exposes the fin 102 such that the top surface of the fin 102 and the insulating material 103 are flush after the planarization process is completed.

[0067] exist Figure 13In this process, the insulating material 103 is recessed to form shallow trench isolation (STI) regions 105. The recessed insulating material 103 causes the upper portion of the fin 102 to protrude between adjacent STI regions 105. Furthermore, the surface of the top STI region 105 can have a flat surface, a convex surface, a concave surface (such as a pit), or a combination thereof. The top surface of the STI region 105 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 105 can be recessed using acceptable etching processes, such as etching processes selectively targeting the material of the insulating material 103 (e.g., etching the material of the insulating material 103 at a faster rate than the material of the fin 102). For example, it can be removed using an oxide, for example, dilute hydrofluoric acid (dHF).

[0068] about Figures 12-13 The described process is merely one example of how fin 102 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed on the top surface of substrate 100, and trenches can be etched through the dielectric layer to expose the underlying substrate 100. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes from the dielectric layer to form a fin. Furthermore, in some embodiments, heteroethelic structures can be used for fin 102. For example, Figures 12-13 The fin 102 shown can be recessed, and a material different from the fin 102 can be epitaxially grown on the recessed fin 102. In such an embodiment, the fin 102 includes a recessed material and an epitaxial growth material disposed on the recessed material. In a further embodiment, a dielectric layer can be formed over the top surface of the substrate 100, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from the substrate 100, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 102. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be in-situ doped during the growth process, which avoids prior and subsequent implantation, although in-situ and implantation doping can be used together.

[0069] exist Figure 14In this process, a dummy gate dielectric layer 107 is formed above the fin 102, and a dummy gate structure 109 is formed above the dummy gate dielectric layer 107. The formation of the dummy gate dielectric layer 107 and the dummy gate structure 109 includes, for example, depositing a dielectric material layer on the fin 102 and a dummy gate material layer on the dielectric material layer using a suitable deposition technique, then patterning the dummy gate material layer into the dummy gate structure 109, and patterning the dielectric material layer into the dummy gate dielectric layer 107 using a suitable photolithography and etching technique. The resulting dummy gate structure 109 has a longitudinal axis perpendicular to the longitudinal axis of the fin 102. In some embodiments, the dummy gate dielectric layer 107 may be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. The dummy gate structure 109 may be a conductive or non-conductive material and may be selected from amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals.

[0070] After forming the dummy gate structure 109, gate spacers 120 are formed on the sidewalls of the dummy gate structure 109. In some embodiments of the spacer formation step, a spacer material layer is deposited on the substrate 100. The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer is conformally disposed on the top and sidewalls of the dummy gate structure 109. The spacer material layer may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon carbide, SiOCN film, and / or combinations thereof. The spacer material layer can be formed by depositing the dielectric material on the dummy gate structure 109 using processes such as CVD, subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. An anisotropic etching process is then performed on the deposited spacer material layer to expose portions of the fin 102 not covered by the dummy gate structure 109 (e.g., in the source / drain portions of the fin 102). The portion of the spacer material layer directly above the dummy gate structure 109 can be completely removed by this anisotropic etching process. The portion of the spacer material layer on the sidewall of the dummy gate structure 109 can be retained to form a gate sidewall spacer, which, for simplicity, is represented as gate spacer 120.

[0071] exist Figure 15In this process, after the gate spacer 120 is formed, an epitaxial source / drain region 106 is formed on the fin 102 and on the opposite side of the dummy gate structure 109. For example, the exposed portion of the semiconductor fin 102 extending laterally beyond the gate spacer 120 (e.g., in the source and drain portions of the fin 102) is etched using an anisotropic etching process, for example, using the dummy gate structure 109 and the gate spacer 120 as an etching mask, to obtain a recess into the semiconductor fin 102. In some embodiments, anisotropic etching can be performed by dry chemical etching with a plasma source and a reactive gas. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactive gas can be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, etc.), a chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen (O2), etc., or combinations thereof. Then, the epitaxial source / drain region 106 is epitaxially grown in the recess of the fin 102. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the composition of the semiconductor material of the fin 102. In some embodiments, epitaxial material may be deposited by a selective epitaxial growth (SEG) process to fill the recess of the fin 102 and extend beyond the original surface of the semiconductor fin 102 to form a raised epitaxial structure 106, the top surface of which is higher than the top surface of the semiconductor fin 102.

[0072] In some embodiments where the MeFET is an n-type transistor, the epitaxial source / drain region 106 may include any acceptable material suitable for an n-type FET. For example, if the fin 102 is silicon, the epitaxial source / drain region 106 may include a material for applying tensile strain to the fin 102, such as silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. In some embodiments where the MeFET is a p-type transistor, the epitaxial source / drain region 106 may include any acceptable material suitable for a p-type FET. For example, if the fin 102 is silicon, the epitaxial source / drain region 106 may include a material for applying compressive strain to the fin 102, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 106 may have a surface protruding from a corresponding upper surface of the upper channel layer and may have a facet. In some embodiments, the epitaxial source / drain region 106 includes Si, Ge, Sn, Si 1-x Ge x Si 1-x-y Ge x Sn y wait.

[0073] The epitaxial source / drain region 106 can be formed by implanting dopants, followed by an annealing process. The source / drain region can have, for example, a size of about 1 × 10⁻⁶. 17 atoms / cm 3 1×10 22 atoms / cm 3 The impurity concentration varies. Dopants include, for example, boron or gallium for p-type MeFETs, and phosphorus or arsenic for n-type MeFETs. In some embodiments, the epitaxial source / drain region 106 may be doped in situ during growth.

[0074] exist Figure 16 In this configuration, a first ILD layer 111 is formed above the substrate 100. The first ILD layer 111 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. A planarization process (such as CMP) can then be performed to make the top surface of the first ILD layer 111 flush with the top surface of the dummy gate structure 109 (e.g., ...). Figure 15 (As shown).

[0075] Next, the dummy gate structure 109 and the dummy gate dielectric layer 107 are removed, thereby forming a gate trench GT1 between the gate spacers 120. Then, an MTJ-containing gate structure 104 is formed in the gate trench GT1 to complete the gate process flow. Specifically, a gate dielectric layer 108, a hard magnetic layer 110, a tunnel barrier layer 112, a soft magnetic layer 114, and a metal gate 118 are deposited sequentially to overfill the gate trench GT1, and then a CMP process is performed to remove the excess portions of these layers outside the gate trench GT1. In this way, the MTJ-containing gate structure 104 is formed in the gate trench GT1 and has a top surface that is substantially coplanar with the top surface of the first ILD layer 111. (Previously regarding...) Figure 1 The materials and other details regarding the MTJ gate structure 104 have been discussed, and therefore will not be repeated for the sake of brevity. The MTJ gate structure 104, the bottom channel region in the semiconductor fin 102, and the source / drain regions 106 located on the opposite side of the MTJ gate structure 104 together serve as a MeFET-based memory device. The MeFET-based memory device can be fabricated simultaneously with the front-end process (FEOL) process for forming other transistors (e.g., logic transistors), rather than in the BEOL process for forming a multi-level interconnect structure.

[0076] exist Figure 17In this configuration, source / drain contacts 122 are formed in the first ILD layer 111 and above the epitaxial source / drain region 106. The formation of the source / drain contacts 122 includes (by way of example and not limitation) performing one or more etching processes to form contact openings extending through the first ILD layer 111 to expose the source / drain region 106, depositing one or more metallic materials (e.g., titanium nitride, tungsten, cobalt, copper, etc., or combinations thereof) using a suitable deposition technique (e.g., CVD, PVD, ALD, etc., or combinations thereof) to overfill the contact openings, and then performing a CMP process to remove excess metallic material outside the contact openings. Thus, the CMP process can planarize the top surface of the source / drain contacts 122 together with the top surface of the MTJ gate structure 104.

[0077] exist Figure 18 In this process, after the source / drain contacts 122 are formed in the first ILD layer 111, a first interconnect layer ML1 is formed over the first ILD layer 111, the source / drain contacts 122, and the MTJ-containing gate structure 104. In some embodiments, a second ILD layer 113 is deposited over the first ILD layer 111 using a suitable deposition technique. The candidate material for the second interlayer dielectric layer 113 is similar to that of the first interlayer dielectric layer 111, and therefore will not be described again. A plurality of conductive vias V0 are formed in the second ILD layer 113 by etching via openings, depositing one or more metallic materials (e.g., titanium nitride, tungsten, cobalt, copper, ruthenium, etc., or combinations thereof in the via openings), and performing a CMP process to remove excess material outside the via openings. The conductive vias V0 include gate vias 124 and source / drain vias 126. Then, a third ILD layer 115 is formed over the second ILD layer 113 and the conductive vias V0 using a suitable deposition technique. The candidate material for the third interlayer dielectric layer 115 is similar to that of the first interlayer dielectric layer 111, and therefore will not be described again. Multiple conductors M1 are then formed in the trench by etching trenches in the third ILD layer 115, depositing one or more metallic materials (e.g., titanium nitride, tungsten, cobalt, copper, ruthenium, etc., or combinations thereof), and performing a CMP process to remove excess material outside the trench. Regarding... Figure 18 The description is merely one example of how interconnect layer ML1 can be formed. It will be understood that interconnect layer ML1 and the subsequent upper interconnect layer (not shown) formed above interconnect layer ML1 can be formed using any other suitable method, such as dual damascene process.

[0078] Figures 19-21 This is a cross-sectional view of an intermediate stage in the fabrication of an IC structure having a MeFET memory device according to some embodiments of the present disclosure. The fabrication process steps can be used to manufacture, for example... Figure 3 The IC structure shown is illustrated. It should be understood that it can be... Figures 19-21Additional operations are provided before, during, and after the process shown. For additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0079] exist Figure 19 In the process of completing the formation of semiconductor fin 102 and STI region 105 (such as... Figure 13 Following the steps shown, a gate-first approach is used, so the gate structure will remain in the final MeFET-based memory device and will not be replaced by another gate structure in subsequent processing. Specifically, the material containing the MTJ gate structure 104 is sequentially deposited on the substrate 100, followed by an etching process to pattern these materials into the gate dielectric layer 108, hard magnetic layer 110, tunnel barrier layer 112, soft magnetic layer 114, and metal gate 118 positioned on the semiconductor fin 102. Thus, each of the gate dielectric layer 108, hard magnetic layer 110, tunnel barrier layer 112, and soft magnetic layer 114 has a linear cross-section. Then, gate spacers 120 are formed on the sidewalls of the MTJ gate structure 104 by depositing one or more spacer materials on the MTJ gate structure 104, followed by etching the spacer materials using an anisotropic etching process as previously discussed. Figure 14 The subject of discussion.

[0080] exist Figure 20 In the middle, the epitaxial source / drain region 106 is formed on the fin 102 and on the opposite side of the MTJ gate structure 104. Details regarding the formation of the source / drain region 106 are referred to above. Figure 15 It has been described, and therefore will not be repeated for the sake of brevity.

[0081] exist Figure 21 In this process, a first ILD layer 111 is formed above the source / drain region 106, and source / drain contacts 122 are formed in the first ILD layer 111 and above the corresponding source / drain regions 106. Then, a first interconnect layer MLI1 is formed above the first ILD layer 111. Details regarding the formation of the first ILD layer 111, the source / drain contacts 122, and the first interconnect layer MLI1 are described above. Figure 17 and Figure 18 The description has already been provided, so it will not be repeated for the sake of brevity.

[0082] Figures 22A-25C These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure with a MeFET memory device using a gate-first process flow according to some embodiments of this disclosure. It will be understood that... Figures 22A-25C Additional operations are provided before, during, and after the process shown. In other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes can be interchanged. Figures 22A-25C In the middle, the "A" diagram (for example, Figure 22A Each of the above diagrams shows a top view of the IC structure, and the "B" diagram (e.g., Figure 22B Each shows a cross-sectional view and a “C” diagram obtained from a plane containing line A-A’. Figure 22C Each of these shows a cross-sectional view obtained from the plane containing the B-B' line.

[0083] exist Figures 22A-22C In this process, a semiconductor fin 302 is formed on a base region 303 of a semiconductor substrate 300. In some embodiments, the semiconductor fin 302 and the base region 303 can be formed, for example, by performing multiple patterning steps on the semiconductor substrate 300. By way of example and not limitation, a first patterned mask having an H-shaped top view profile is formed over the substrate 300, and then a first etching step is performed on the substrate 300 using the first patterned mask as an etching mask to form the base region 303 having an H-shaped top view profile. Then, a second patterned mask having a striped top view profile is formed in the central region of the base region 303, and then a second etching step is performed on the base region 303 using the second patterned mask as an etching mask to form the semiconductor fin 302 having a striped top view profile. Subsequently, an STI region 305 is formed over the substrate 300. In some embodiments, the formation of the STI region 305 includes, for example, depositing one or more dielectric materials over a substrate 300, performing a CMP process on the deposited dielectric material until the semiconductor fin 302 is exposed, and then etching back the dielectric material until the pedestal region 303 is exposed.

[0084] exist Figures 23A-23C In this configuration, an MTJ gate structure 304 is formed over a portion of the base region 303 and spans the semiconductor fin 302. This gate structure will remain in the final MeFET-based memory device and will not be replaced by another gate structure in subsequent processes. Specifically, the material containing the MTJ gate structure 304 is sequentially deposited on the substrate 100, followed by an etching process to pattern these materials into a gate dielectric layer 308, a hard magnetic layer 310, a tunnel barrier layer 312, a soft magnetic layer 314, and a metal gate 318. The hard magnetic layer 310, the tunnel barrier layer 312, and the soft magnetic layer 314 collectively serve as the MTJ stack. The materials of the gate dielectric layer 308, the hard magnetic layer 310, the tunnel barrier layer 312, and the soft magnetic layer 314 are similar to those of the gate dielectric layer 108, the hard magnetic layer 110, the tunnel barrier layer 112, the soft magnetic layer 114, and the metal gate 118, and therefore will not be described again for simplicity. Figure 23A In the top view, the dashed lines show the semiconductor fin 302 covered by the MTJ gate structure 304.

[0085] exist Figures 24A-24CIn this configuration, a gate spacer 320 is formed on the sidewall of the MTJ-containing gate structure 104. The formation of the gate spacer 320 includes, for example, depositing one or more spacer materials on the MTJ-containing gate structure 304, followed by using methods as previously described... Figure 14 The anisotropic etching process discussed etches the spacer material. In some embodiments, such as... Figure 24A As shown in the top view, four gate spacers 320 are formed on the four sides of the MTJ gate structure 304. These gate spacers 320 are connected to form a rectangular or square annular spacer surrounding the MTJ gate structure 304.

[0086] exist Figures 25A-25C In this process, a crystalline semiconductor material is deposited on the exposed surface of a semiconductor substrate 300 using, for example, selective epitaxial growth (SEG), while an epitaxial source / drain region 306 is formed on the exposed surface of the base region 303 of the semiconductor substrate 300. Details regarding the formation of the source / drain region 306 are consistent with previous descriptions. Figure 15 The details of the described source / drain region 106 are similar, and therefore will not be repeated for the sake of brevity. In some embodiments, the thickness of the epitaxial source / drain region 306 ranges from about 1 nm to about 100 nm. Subsequently, a BEOL process is performed to achieve the desired effect. Figures 25A-25C An interconnection structure is formed above the structure shown (e.g., as shown in the image). Figure 21 (The metal through-hole and metal wire shown).

[0087] Figures 26A-29C These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure with a MeFET memory device using a post-gate process flow according to some embodiments of this disclosure. It will be understood that... Figures 26A-29C Additional operations are provided before, during, and after the process shown. In other embodiments of the method, some of the operations described below can be replaced or eliminated. The order of operations / processes can be interchanged. Figures 26A-29C In the middle, the "A" diagram (for example, Figure 26A Each of the above diagrams shows a top view of the IC structure, and the "B" diagram (e.g., Figure 26B Each of the above shows a cross-sectional view obtained from a plane containing line A-A', and the "C" diagram (e.g., Figure 26C Each of these shows a cross-sectional view obtained from the plane containing the B-B' line.

[0088] exist Figures 26A-26C In the process of forming semiconductor fins 302, base region 303 and STI region 305 (e.g. Figures 22A-22CFollowing the steps shown, a dummy gate dielectric layer 307 is formed on the semiconductor fin 302, and then a dummy gate structure 309 is formed over the dummy gate dielectric layer 307. Example materials and processes used to form the dummy gate dielectric layer 307 and the dummy gate structure 309 are similar to those previously described. Figure 14 The materials and example processes of the pseudo-gate dielectric layer 107 and pseudo-gate structure 109 discussed will not be repeated for the sake of brevity.

[0089] Subsequently, gate spacers 320 are formed on the sidewalls of the dummy gate structure 309. In some embodiments, such as Figure 26A As shown in the top view, four gate spacers 320 are formed on the four sides of the dummy gate structure 309. These gate spacers 320 are connected to form a rectangular or square annular spacer surrounding the dummy gate structure 309. Then, for example, by selectively depositing a crystalline semiconductor material on the exposed surface of the pedestal region 303 using selective epitaxial growth (SEG), an epitaxial source / drain region 306 is formed on the exposed surface of the pedestal region 303 of the semiconductor substrate 300. Then, by depositing one or more dielectric materials over the epitaxial source / drain region 306 and the dummy gate structure 309 and performing a CMP process until the dummy gate structure 309 is exposed, an ILD layer (e.g., SiO2, low-k dielectric, etc.) 311 is formed over the epitaxial source / drain region 306.

[0090] Reference in the figure Figures 27A-27C The dummy gate structure 309 and the dummy gate dielectric layer 307 are removed, thereby forming a gate trench GT2 between the gate spacers 320. For example... Figures 28A-28C As shown, a gate dielectric layer 308, a hard magnetic layer 310, a tunnel barrier layer 312, a soft magnetic layer 314, and a metal gate 318 are deposited sequentially until the overfill gate trench GT2 is reached. Figures 29A-29C In the process, a CMP process is performed to remove excess material from the gate dielectric layer 308, hard magnetic layer 310, tunnel barrier layer 312, soft magnetic layer 314, and metal gate 318 outside the gate trench GT2. Thus, the remaining gate dielectric layer 308, hard magnetic layer 310, tunnel barrier layer 312, soft magnetic layer 314, and metal gate 318 in the gate trench GT2 can be collectively referred to as the MTJ-containing gate structure 304. Subsequently, a BEOL process is performed to... Figures 29A-29C An interconnection structure is formed above the structure shown (e.g., as shown in the image). Figure 21 (The metal through-hole and metal wire shown).

[0091] Figures 30A-35C These are top and cross-sectional views of an intermediate stage in the fabrication of an IC structure for a MeFET memory device in the form of a gate-all-around (GAA) device, according to some embodiments of this disclosure. It will be understood that... Figures 30A-35CAdditional operations are provided before, during, and after the process shown. For additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes can be interchanged. Figures 30A-35C In the middle, the "A" diagram (for example, Figure 30A Each of the above diagrams shows a top view of the IC structure, and the "B" diagram (e.g., Figure 30B Each of the above shows a cross-sectional view obtained from a plane containing line A-A', and the "C" diagram (e.g., Figure 30C Each of these shows a cross-sectional view obtained from the plane containing the B-B' line.

[0092] exist Figures 30A-30C In this embodiment, an epitaxial stack 402 is formed over a base region 303 of a substrate 300. The epitaxial stack 402 includes an epitaxial layer 404 of a first component into which an epitaxial layer 406 of a second component is inserted. The first and second components may be different. In some embodiments, the epitaxial layer 404 is SiGe and the epitaxial layer 406 is silicon (Si). However, other embodiments are also possible, including embodiments providing a first and second component with different oxidation rates and / or etch selectivity. In some embodiments, the epitaxial layer 404 comprises SiGe, and in the case where the epitaxial layer 406 comprises Si, the Si oxidation rate of the epitaxial layer 406 is less than the SiGe oxidation rate of the epitaxial layer 404.

[0093] It is worth noting that the three epitaxial layers 404 and the three epitaxial layers 406 are arranged alternately, such as... Figures 30B-30C The illustration is for illustrative purposes only and is not intended to limit the scope beyond what is specifically described in this disclosure. It will be understood that any number of epitaxial layers can be formed in the epitaxial stack 402; the number of layers depends on the number of channel regions required for the transistor. In some embodiments, the number of epitaxial layers 406 is between 2 and 10.

[0094] As described in more detail below, epitaxial layer 406 will serve as the transistor channel region for the subsequently formed GAA device, and its thickness is selected based on device performance considerations. Epitaxial layer 404 can eventually be removed and used to define the vertical distance between adjacent channel regions for the subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Therefore, epitaxial layer 404 can also be referred to as a sacrificial layer, and epitaxial layer 406 can also be referred to as a channel layer.

[0095] For example, the epitaxial growth of the layers of stack 402 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer, such as epitaxial layer 406, comprises the same material as the substrate 300. In some embodiments, epitaxial growth layers 404 and 406 comprise materials different from the substrate 300. As described above, in at least some examples, epitaxial layer 404 comprises an epitaxially grown silicon-germanium (SiGe) layer and epitaxial layer 406 comprises an epitaxially grown silicon (Si) layer. Optionally, in some embodiments, either of epitaxial layers 404 and 406 may comprise other materials: such as germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. As discussed, the materials for epitaxial layers 404 and 406 can be selected based on providing different oxidation properties and / or etch selectivity properties. In some embodiments, where, for example, no intentional doping is performed during the epitaxial growth process, epitaxial layers 404 and 406 are substantially dopant-free (i.e., having a dopant content from about 0 cm⁻¹). -3 Up to approximately 1×10 18 cm -3 (external dopant concentration).

[0096] A dummy gate dielectric layer 307 is formed on the epitaxial stack 402, and a dummy gate structure 309 is formed on the dummy gate dielectric layer 307. A gate spacer 320 is formed on the sidewall of the dummy gate structure 309, and then the gate spacer 320 is exposed. The lateral extensions of the epitaxial stack 402 beyond the dummy gate structure 309 and the gate spacer 320 are etched until the base region 303 is exposed. The example materials and processes used to form the dummy gate dielectric layer 307, the dummy gate structure 309, and the gate spacer 320 are similar to those previously described. Figure 14 The materials and example processes for the dummy gate dielectric layer 107, dummy gate structure 109, and gate spacer 120 discussed will not be repeated for the sake of brevity.

[0097] exist Figures 31A-31CIn this process, sacrificial layer 404 is recessed laterally or horizontally using a suitable etching technique, thereby creating respective vertical lateral recesses between corresponding channel layers 406. This step can be performed using a selective etching process. By way of example and not limitation, sacrificial layer 404 is SiGe and channel layer 406 is silicon that allows selective etching of sacrificial layer 404. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture) of SiGe at an etch rate faster than that of Si. In some embodiments, selective etching includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, followed by removal of SiGeO by an etchant (such as NH4OH). x The etchant selectively etches SiGeOx at a faster etch rate than it etches Si. Furthermore, because the oxidation rate of Si is slower than that of SiGe, the channel layer 406 is not significantly etched by the process of laterally recessing the sacrificial layer 404. As a result, the channel layer 406 extends laterally across the opposite end faces of the sacrificial layer 404.

[0098] After the lateral recessed sacrificial layer 404 is recessed, an internal spacer 408 is formed to fill the recess left by the lateral etching of the sacrificial layer 404. The internal spacer 408 can be formed, for example, by depositing one or more dielectric materials into the recess left by the lateral etching that removes the sacrificial layer 404, followed by an anisotropic etching process to trim the deposited one or more dielectric materials. The remaining portion of the deposited one or more dielectric materials after the trimming process is represented as the internal spacer 408. The internal spacer 408 serves to isolate the MTJ-containing gate from the source / drain epitaxial structure formed in subsequent processes. Figure 31B In the example shown, the outermost wall of the inner spacer 408 is substantially aligned with the sidewall of the channel layer 406.

[0099] exist Figures 32A-32C In this process, an epitaxial source / drain region 306 is formed on the exposed surface of the base region 303 of the semiconductor substrate 300 by selectively depositing crystalline semiconductor material on the exposed surface of the base region 303 using, for example, selective epitaxial growth (SEG). Details regarding the formation of the source / drain region 306 are consistent with previous descriptions. Figure 15 The details of the source / drain region 106 are similar, so they will not be repeated for the sake of brevity. Then, an ILD layer 311 is formed over the epitaxial source / drain region 306 by depositing one or more dielectric materials over the epitaxial source / drain region 306 and the dummy gate structure 309 and performing a CMP process until the dummy gate structure 309 is formed.

[0100] like Figures 33A-33CAs shown, the dummy gate structure 309 and the dummy gate dielectric layer 307 are removed, followed by the removal of the sacrificial layer 404. In some embodiments, the dummy gate structure 309 and the dummy gate dielectric layer 307 are removed by using one or more selective etching processes (e.g., selective dry etching, selective wet etching, or combinations thereof) to etch the materials in the dummy gate structure 309 and the dummy gate dielectric layer 307 at a faster etching rate than etching other materials (e.g., gate spacers 320, internal spacers 408, and / or ILD layer 311), thus creating a gate trench GT3 between the corresponding gate spacers 320, in which the sacrificial layer 404 is exposed. Subsequently, the sacrificial layer 404 in the gate trench GT3 is removed by using another selective etching process to etch the sacrificial layer 404 at a faster etching rate than etching the channel layer 406, thereby forming an opening 410 between adjacent channel layers 406. In this way, the channel layer 406 becomes a nanosheet suspended above the substrate 300 and between the source / drain epitaxial structures 306. This step is also known as the channel release process. In this intermediate processing step, the openings 410 between the nanosheets 406 can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the nanosheets 406 can be interchangeably referred to as nanowires, nanoplates, and nanorings, depending on their geometry. For example, in some other embodiments, the channel layer 406 can be trimmed into a substantially circular shape (i.e., cylindrical) due to a selective etching process used to completely remove the sacrificial layer 404. In this case, the resulting channel layer 406 can be referred to as a nanowire. In some embodiments, the geometry of the channel layer 406 can be circular, rhomboid, etc., and the channel layer 406 can have rounded corners. In some embodiments, the thickness of each channel layer 406 is in the range of about 1 nm to about 100 nm, the width is in the range of about 1 nm to about 100 nm, and the number of channel layers 406 can be one or more. In some embodiments, the vertical pitch of the channel layers 406 can be in the range of about 2 nm to about 500 nm.

[0101] In some embodiments, the sacrificial layer 404 is removed using a selective wet etching process. In some embodiments, the sacrificial layer 404 is SiGe and the channel layer 406 is silicon that allows for the selective removal of the sacrificial layer 404. In some embodiments, the selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, selective removal includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, followed by removal of SiGeO by an etchant (such as NH4OH). x This etchant selectively etches SiGeO at a faster etch rate than it etches Si. xFurthermore, since the oxidation rate of Si is much slower than that of SiGe (sometimes 30 times slower), the channel layer 406 may not be significantly etched by the channel release process.

[0102] Next, in Figures 34A-34C In the process, a gate dielectric layer 308, a hard magnetic layer 310, a tunnel barrier layer 312, a soft magnetic layer 314, and a metal gate 318 are deposited sequentially until the gate trench GT3 is filled. Figures 35A-35C In the process, a CMP process is performed to remove excess material from the gate dielectric layer 308, hard magnetic layer 310, tunnel barrier layer 312, soft magnetic layer 314, and metal gate 318 outside the gate trench GT3. Thus, the remaining gate dielectric layer 308, hard magnetic layer 310, tunnel barrier layer 312, soft magnetic layer 314, and metal gate 318 in the gate trench GT3 can be collectively referred to as the MTJ-containing gate structure 304. Subsequently, a BEOL process is performed to... Figures 35A-35C An interconnection structure is formed above the structure shown (e.g., as shown in the image). Figure 21 (The metal through-hole and metal wire shown).

[0103] Based on the above discussion, it can be seen that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and no particular advantage is required for all embodiments. One advantage is that MeFET-based memory devices can be operated using VCMA or magnetic fields without current tunneling through the tunnel barrier layer in the MTJ, thus MeFET-based memory devices have improved tunnel barrier reliability and reduced power consumption. Another advantage is that the MTJ is integrated into transistors fabricated in the FEOL process, thus allowing more available wiring space to be used to perform the BEOL process for interconnects and vias.

[0104] In some embodiments, the memory device includes a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source and drain regions are above a substrate. The channel region is located between the source and drain regions. The gate dielectric layer is located above the channel region. The MTJ stack is located above the gate dielectric layer. The MTJ stack includes a first ferromagnetic layer, a second ferromagnetic layer having switchable magnetization, and a tunnel barrier layer located between the first and second ferromagnetic layers. The metal gate is located above the MTJ stack. In some embodiments, the thickness of the tunnel barrier layer is greater than the thickness of the second ferromagnetic layer. In some embodiments, the second ferromagnetic layer is in contact with the metal gate. In some embodiments, the first ferromagnetic layer is in contact with the gate dielectric layer. In some embodiments, the first ferromagnetic layer has a U-shaped cross-section, the tunnel barrier layer has a U-shaped cross-section, and the second ferromagnetic layer has a U-shaped cross-section. In some embodiments, the capacitance of the MTJ stack is less than the capacitance of the gate dielectric layer.

[0105] In some embodiments, the memory device includes an MTJ structure, a source region, a drain region, and a gate. The MTJ structure is located above a semiconductor channel region. The source and drain regions are located on opposite sides of the MTJ structure. The gate is located above the MTJ structure. The capacitance of the MTJ structure has a binary value that can be switched by a voltage applied to the gate, and the drain current of the drain region depends on the capacitance of the MTJ structure. In some embodiments, the memory device further includes a gate dielectric layer that separates the MTJ structure from the semiconductor channel region. In some embodiments, one or both of the binary values ​​of the capacitance of the MTJ structure are less than the capacitance of the gate dielectric layer. In some embodiments, the memory device further includes a metal line extending laterally above the gate, and the capacitance of the MTJ structure is also switchable by a magnetic field generated from the metal line. In some embodiments, the drain current that depends on the capacitance of the MTJ structure is a drain saturation current or a subthreshold drain current.

[0106] In some embodiments, a method includes forming a semiconductor channel over a substrate, forming source / drain regions on opposite sides of the semiconductor channel, forming a gate dielectric layer on the semiconductor channel, forming an MTJ stack over the gate dielectric layer, and forming a metal gate on the MTJ stack. The MTJ stack includes a first ferromagnetic layer over the gate dielectric layer, a tunnel barrier layer over the first ferromagnetic layer, and a second ferromagnetic layer over the tunnel barrier layer. In some embodiments, the method further includes forming a dummy gate structure over the semiconductor channel, forming gate spacers on the sidewalls of the dummy gate structure, removing the dummy gate structure to form a gate trench between the gate spacers, wherein after removing the dummy gate structure, the gate dielectric layer, the MTJ stack, and the metal gate are formed in the gate trench. In some embodiments, the gate dielectric layer, the MTJ stack, and the metal gate are formed before forming the source / drain regions. In some embodiments, forming the semiconductor channel includes forming fins extending from the substrate. In some embodiments, forming the semiconductor channel includes forming nanosheets extending between the source / drain regions and suspended over the substrate. In some embodiments, the tunnel barrier layer is thicker than the second ferromagnetic layer. In some embodiments, the method further includes forming a gate via located on the metal gate and spaced apart from the MTJ stack.

[0107] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory device, comprising: The source and drain regions are located above the substrate; The channel region is located between the source region and the drain region; A gate dielectric layer is located above the channel region; A magnetic tunnel junction stack is located above the gate dielectric layer. The magnetic tunnel junction stack includes a first ferromagnetic layer, a second ferromagnetic layer having switchable magnetization, and a tunnel barrier layer located between the first ferromagnetic layer and the second ferromagnetic layer. as well as A metal gate is located above the magnetic tunnel junction stack. The capacitance of the magnetic tunnel junction stack is smaller than the capacitance of the gate dielectric layer.

2. The memory device according to claim 1, wherein, The thickness of the tunnel barrier layer is greater than the thickness of the second ferromagnetic layer.

3. The memory device according to claim 1, wherein, The second ferromagnetic layer is in contact with the metal gate.

4. The memory device according to claim 1, wherein, The first ferromagnetic layer is in contact with the gate dielectric layer.

5. The memory device according to claim 1, wherein, The first ferromagnetic layer has a U-shaped cross-section.

6. The memory device according to claim 1, wherein, The tunnel barrier layer has a U-shaped cross-section.

7. The memory device according to claim 1, wherein, The second ferromagnetic layer has a U-shaped cross-section.

8. The memory device according to claim 1, wherein, The channel region includes a nanosheet extending between the source region and the drain region and suspended above the substrate.

9. A memory device, comprising: A magnetic tunnel junction structure is located above the semiconductor channel region; A gate dielectric layer separates the magnetic tunnel junction structure from the semiconductor channel region; The source and drain regions are located on opposite sides of the magnetic tunnel junction structure, respectively. as well as A gate is located above the magnetic tunnel junction structure, wherein the capacitance of the magnetic tunnel junction structure has a switchable binary value by applying a voltage to the gate, one or both of the binary values ​​of the capacitance of the magnetic tunnel junction structure are less than the capacitance of the gate dielectric layer, and the drain current of the drain region depends on the capacitance of the magnetic tunnel junction structure.

10. The memory device according to claim 9, wherein, The magnetic tunnel structure includes a first ferromagnetic layer, a second ferromagnetic layer with switchable magnetization, and a tunnel barrier layer located between the first ferromagnetic layer and the second ferromagnetic layer.

11. The memory device according to claim 10, wherein, The thickness of the tunnel barrier layer is greater than the thickness of the second ferromagnetic layer.

12. The memory device according to claim 9, further comprising: A metal line extends laterally above the gate, wherein the capacitance of the magnetic tunnel junction structure is also switchable by a magnetic field generated from the metal line.

13. The memory device according to claim 9, wherein, The drain current, depending on the capacitance of the magnetic tunnel junction structure, is either a drain saturation current or a subthreshold drain current.

14. A method of forming a memory device, comprising: A semiconductor channel is formed above the substrate; Source / drain regions are formed on opposite sides of the semiconductor channel, respectively; A gate dielectric layer is formed on the semiconductor channel; A magnetic tunnel junction stack is formed above the gate dielectric layer. The magnetic tunnel junction stack includes a first ferromagnetic layer above the gate dielectric layer, a tunnel barrier layer above the first ferromagnetic layer, and a second ferromagnetic layer above the tunnel barrier layer. The capacitance of the magnetic tunnel junction stack is smaller than the capacitance of the gate dielectric layer. as well as A metal gate is formed above the magnetic tunnel junction stack.

15. The method of claim 14, further comprising: A dummy gate structure is formed above the semiconductor channel; A gate spacer is formed on the sidewall of the dummy gate structure; and Remove the dummy gate structure to form a gate trench between the gate spacers. After removing the dummy gate structure, the gate dielectric layer, the magnetic tunnel junction stack, and the metal gate are formed in the gate trench.

16. The method of claim 14, wherein, The gate dielectric layer, the magnetic tunnel junction stack, and the metal gate are formed prior to the formation of the source / drain regions.

17. The method according to claim 14, wherein, Forming the semiconductor channel includes forming fins extending from the substrate.

18. The method according to claim 14, wherein, Forming the semiconductor channel includes forming a nanosheet that extends between the source / drain regions and is suspended above the substrate.

19. The method of claim 14, wherein, The tunnel barrier layer is thicker than the second ferromagnetic layer.

20. The method of claim 14, further comprising: A gate via is formed on the metal gate and spaced apart from the magnetic tunnel junction stack.

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