IBC / HBC batteries based on high hole mobility materials and their preparation methods

Abstract

This invention discloses an IBC / HBC battery based on a high hole mobility material and its fabrication method. The IBC / HBC battery includes: a crystalline silicon substrate having a front and a back side; a first passivation layer on the front side of the crystalline silicon substrate; an antireflection layer on the surface of the first passivation layer away from the crystalline silicon substrate; a second passivation layer on the back side of the crystalline silicon substrate; a hole transport layer including multiple sub-hole transport layers; and an electron transport layer including multiple sub-electron transport layers, the sub-hole transport layers being spaced apart on the surface of the second passivation layer away from the crystalline silicon substrate. The hole transport layer is made of a polymer material. This invention improves the crystallinity of each sub-hole transport layer, thereby significantly improving the carrier mobility and conductivity of each sub-hole transport layer.

Description

Technical Field

[0001] This invention belongs to the field of solar photovoltaic technology, specifically relating to an IBC / HBC battery based on a high hole mobility material and its preparation method. Background Technology

[0002] P-type polymers (PTAA, PEDOT:PSS, etc.) are widely used in photovoltaic cells as hole transport layers due to their tunable bandgap, simple preparation process, and good device compatibility. However, their low conductivity (typically 1-500 S / cm) limits further improvements in cell efficiency.

[0003] According to the Drude model of conductivity, the main ways to improve conductivity include increasing carrier concentration (n) and increasing carrier mobility (μ). However, for organic polymers, it is difficult to improve both simultaneously because the doping ions introduced to increase carrier concentration greatly increase ionized impurity scattering, resulting in a significant decrease in carrier mobility and thus conductivity. Of the two methods mentioned above, this invention chooses to increase carrier mobility to improve the conductivity of the polymer.

[0004] To further illustrate how to improve carrier mobility, we introduce the Drude model here:

[0005]

[0006] Where q, n, m, and τ represent the carrier charge constant, carrier density, carrier mass, and mean free time between carrier collisions, respectively.

[0007] The mean free time τ can be expressed as:

[0008]

[0009] Where L,V R denoted as mean free path and velocity of charge carriers, respectively; μ is the carrier mobility; e is the charge constant; and m is the charge mass.

[0010] As can be seen from formula (3.2), increasing L (mean free path of carrier movement) can effectively improve carrier mobility. L is only related to crystal structure. L in crystal is 2-3 orders of magnitude higher than that in amorphous or semi-crystalline states. Therefore, preparing amorphous or semi-crystalline polymer materials into highly crystalline or even single crystals will significantly improve the carrier mobility of polymers, thereby improving their electrical conductivity. Summary of the Invention

[0011] This invention aims to at least partially address one of the technical problems in related technologies. Therefore, the objective of this invention is to propose an IBC / HBC battery based on a high hole mobility material and its preparation method. This invention improves the crystallinity of each sub-hole transport layer, thereby significantly increasing the carrier mobility and conductivity of each sub-hole transport layer.

[0012] In one aspect of the present invention, an IBC / HBC battery based on a high hole mobility material is proposed. According to an embodiment of the present invention, the IBC / HBC battery based on the high hole mobility material comprises:

[0013] A crystalline silicon substrate having opposing front and back sides;

[0014] A first passivation layer is provided on the front side of the crystalline silicon substrate.

[0015] An anti-reflection layer, the anti-reflection layer being located on the surface of the first passivation layer away from the crystalline silicon substrate layer;

[0016] A second passivation layer is provided on the back side of the crystalline silicon substrate.

[0017] A hole transport layer, wherein the hole transport layer includes multiple sub-hole transport layers;

[0018] An electron transport layer, the electron transport layer comprising a plurality of sub-electron transport layers, the sub-hole transport layers and the sub-electron transport layers being spaced apart on the surface of the second passivation layer away from the crystalline silicon substrate layer;

[0019] The hole transport layer is made of polymer material.

[0020] According to embodiments of the present invention, the IBC / HBC battery based on high hole mobility materials, by alternating between sub-hole transport layers and sub-electron transport layers, kinetically restricts the gradual polymerization reaction of polymer materials in each sub-hole transport layer, allowing them to be arranged regularly within the template (i.e., between adjacent sub-electron transport layers), thereby obtaining highly ordered polymer chains, i.e., highly crystalline polymer materials. This improves the crystallinity of each sub-hole transport layer, thereby significantly increasing the carrier mobility and conductivity of each sub-hole transport layer.

[0021] In addition, the IBC / HBC battery based on a high hole mobility material according to the above embodiments of the present invention may also have the following additional technical features:

[0022] In some embodiments of the present invention, the width of a single sub-hole transport layer is not greater than 90 μm; preferably, the width of a single sub-hole transport layer is not greater than 50 μm, more preferably 100–200 nm.

[0023] In some embodiments of the present invention, the thickness of a single sub-hole transport layer is no greater than 50 nm; preferably, the thickness of a single sub-hole transport layer is no greater than 20 nm.

[0024] In some embodiments of the present invention, the hole transport layer is made of a P-type polymer, which is selected from at least one of PTAA, PEDOT and P3HT.

[0025] In some embodiments of the present invention, the crystallinity of the hole transport layer is 50-100%, preferably 80-100%.

[0026] In some embodiments of the present invention, the hole mobility of the hole transport layer formed from the PEDOT material is 5 to 30 cm⁻¹. 2 / Vs, conductivity 1000~9000S / cm.

[0027] In some embodiments of the present invention, the hole mobility of the hole transport layer formed from the P3HT material is 20–100 cm⁻¹. 2 / Vs, with an electrical conductivity of 1000–4000 S / cm.

[0028] In another aspect of the invention, a method for preparing the IBC / HBC battery based on a high hole mobility material as described in the above embodiments is provided. According to an embodiment of the invention, the method includes:

[0029] (1) A crystalline silicon substrate layer is provided, the crystalline silicon substrate layer having opposing front and back sides;

[0030] (2) A first passivation layer and an anti-reflection layer are sequentially formed on the front side of the crystalline silicon substrate;

[0031] (3) A second passivation layer is formed on the back side of the crystalline silicon substrate;

[0032] (4) An isolation layer is formed on the surface of the second passivation layer away from the crystalline silicon substrate, and the isolation layer corresponding to the multiple sub-electron transport layers is removed to prepare multiple sub-electron transport layers.

[0033] (5) Remove the isolation layer corresponding to the region of the multiple sub-hole transport layers to prepare multiple sub-hole transport layers, and set the sub-hole transport layers and the sub-electron transport layers at intervals.

[0034] According to the method of this invention, by alternating between the sub-hole transport layer and the sub-electron transport layer, the gradual polymerization reaction of the polymer material in each sub-hole transport layer is kinetically restricted, and the polymer materials can only be arranged regularly in the template (i.e., between adjacent sub-electron transport layers). This results in highly ordered polymer chains, i.e., highly crystalline polymer materials, which improves the crystallinity of each sub-hole transport layer, thereby significantly increasing the carrier mobility and conductivity of each sub-hole transport layer. Furthermore, this method is simple and easy to implement.

[0035] In addition, the method according to the above embodiments of the present invention may also have the following technical solutions:

[0036] In some embodiments of the present invention, the method further includes: texturing the crystalline silicon substrate before forming the first passivation layer on the front side of the crystalline silicon substrate, thereby forming pyramid-like structures on the front and back sides respectively.

[0037] In some embodiments of the present invention, the method for preparing the sub-hole transport layer includes: under the action of an oxidant, using a gas-phase synthesis method to gradually polymerize the monomers of the polymer material to synthesize a plurality of the sub-hole transport layers.

[0038] In some embodiments of the present invention, the oxidant is a salt oxidant with an oxidation potential of 0.6-0.9V.

[0039] In some embodiments of the present invention, the salt oxidant is selected from Fe. 3+ Salts and Ag + At least one of the salts.

[0040] In some embodiments of the present invention, the Fe 3+ The salts are selected from at least one of FeCl3, FeBr3, FeI3, FeTos, Fe2(SO4)3, Fe2(NO3)3, Fe2O3 and FeOOH.

[0041] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0043] Figure 1 This is a schematic diagram of the structure of an IBC / HBC battery based on a high hole mobility material according to an embodiment of the present invention.

[0044] Attached image captions:

[0045] 1-Antireflection layer, 2-First passivation layer, 3-Crystal silicon substrate layer, 3-1-Front side, 3-2-Back side, 4-Second passivation layer, 5-Sub-electron transport layer, 6-Sub-hole transport layer, 7-Sub-gate line, 8-Main gate line. Detailed Implementation

[0046] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0047] In one aspect of the invention, an IBC / HBC battery based on a high hole mobility material is proposed. According to an embodiment of the invention, refer to the appendix... Figure 1 An IBC / HBC battery based on a high hole mobility material includes: a crystalline silicon substrate 3 having a front side 3-1 and a back side 3-2; a first passivation layer 2 on the front side 3-1 of the crystalline silicon substrate 3; an antireflection layer 1 on the surface of the first passivation layer 2 away from the crystalline silicon substrate 3; a second passivation layer 4 on the back side 3-2 of the crystalline silicon substrate 3; a hole transport layer including a plurality of sub-hole transport layers 6; and an electron transport layer including a plurality of sub-electron transport layers 5, the sub-hole transport layers 6 and the sub-electron transport layers 5 being spaced apart on the surface of the second passivation layer 4 away from the crystalline silicon substrate 3; the hole transport layer is made of a polymer material. Therefore, by setting the sub-hole transport layer 6 and the sub-electron transport layer 5 alternately, the polymer material of each sub-hole transport layer 6 is kinetically restricted and can only be arranged regularly in the template (i.e., between adjacent sub-electron transport layers 5), thereby obtaining highly ordered polymer chains, i.e., highly crystalline polymer materials, which improves the crystallinity of each sub-hole transport layer 6, thereby significantly improving the carrier mobility and conductivity of each sub-hole transport layer 6.

[0048] According to a specific embodiment of the present invention, the width of a single sub-hole transport layer 6 is no greater than 90 μm, preferably no greater than 50 μm, and more preferably 100–200 nm. Limiting the width of a single sub-hole transport layer 6 to the above range further facilitates the orderly arrangement of the sub-hole transport layers 6 between adjacent sub-electron transport layers 5, thereby obtaining highly ordered polymer chains and further improving the crystallinity of each sub-hole transport layer 6.

[0049] According to another specific embodiment of the present invention, the thickness of a single sub-hole transport layer 6 is no greater than 50 nm; preferably, the thickness of a single sub-hole transport layer 6 is no greater than 20 nm. Thus, limiting the thickness of a single sub-hole transport layer 6 to the above range further facilitates the orderly arrangement of the sub-hole transport layers 6 in a limited space, thereby obtaining highly ordered polymer chains and further improving the crystallinity of each sub-hole transport layer 6.

[0050] In embodiments of the present invention, the filling space of the polymer is controlled by limiting the width and thickness between templates (i.e., the width and thickness of a single sub-hole transport layer 6), so that the polymer material of each sub-hole transport layer 6 is kinetically restricted and can only be arranged regularly in the template (i.e., between adjacent sub-electron transport layers 5), thereby obtaining highly ordered polymer chains, i.e., highly crystalline polymer materials, which improves the crystallinity of each sub-hole transport layer, thereby significantly improving the carrier mobility and conductivity of each sub-hole transport layer.

[0051] According to another specific embodiment of the present invention, the hole transport layer is made of a P-type polymer, which is selected from at least one of PTAA, PEDOT, and P3HT. It should be noted that the crystallinity of hole transport layers varies depending on the material, as shown in Table 1.

[0052] Table 1

[0053]

[0054] The structural formula of PEDOT is as follows: When the width of a single subhole transport layer is less than or equal to 200 nm and the thickness is less than or equal to 12 nm, it reaches the single crystal state, and its crystallinity reaches 100%.

[0055] The structural formula of P3HT is as follows: When the width of a single subhole transport layer is less than or equal to 150 nm and the thickness is less than or equal to 20 nm, it reaches the single crystal state, and its crystallinity reaches 100%.

[0056] Compared to hole transport layers prepared by conventional methods, the hole transport layer prepared by the template method in this invention (which defines the width and thickness of the sub-hole transport layers) exhibits significantly improved hole mobility and conductivity. Specifically, the hole mobility of the PEDOT hole transport layer prepared by conventional methods is 0.01-1 cm⁻¹. 2 / Vs, conductivity 100-500S / cm; the hole mobility of the PEDOT hole transport layer prepared by the template method in this invention is 5-30cm. 2 / Vs, with an electrical conductivity of 1000–9000 S / cm. The hole mobility of the hole transport layer of P3HT material prepared using conventional methods is 0.01 cm. 2 / Vs, conductivity 10S / cm; the hole mobility of the P3HT hole transport layer prepared by the template method in this invention is 20-100cm. 2 / Vs, with a conductivity of 1000–4000 S / cm. In contrast, the hole mobility of the hole transport layer made of pa-Si(H) material using conventional methods is 10. -4 ~10 -3 cm 2 / Vs, conductivity 10 -3 ~10 -2 S / cm.

[0057] In embodiments of the present invention, the material of the first passivation layer is not particularly limited, and may include, but is not limited to, a-Si, polycrystalline silicon, microcrystalline silicon, silicon oxide, etc. Similarly, the material of the second passivation layer is not particularly limited, and may include, but is not limited to, a-Si, polycrystalline silicon, microcrystalline silicon, silicon oxide, etc.

[0058] In another aspect, the present invention provides a method for preparing the IBC / HBC battery based on a high hole mobility material as described in the above embodiments. According to an embodiment of the present invention, the method includes:

[0059] S100: Provides a crystalline silicon substrate layer

[0060] In this step, a crystalline silicon substrate 3 is provided, which has a front side 3-1 and a back side 3-2. The front side 3-1 refers to the light-facing surface, and the back side 3-2 refers to the light-repelling surface. (Refer to the attached diagram.) Figure 1 .

[0061] According to a specific embodiment of the present invention, before forming the first passivation layer on the front side of the crystalline silicon substrate, the crystalline silicon substrate is texturized to form a pyramid-like structure on both the front and back sides. The purpose of texturizing the front side is to reduce the reflection of incident light, increase the short-circuit current of the battery, and thus improve the photoelectric conversion efficiency of the battery.

[0062] S200: A first passivation layer and an anti-reflection layer are sequentially formed on the front side of the aforementioned crystalline silicon substrate.

[0063] In this step, a first passivation layer and an antireflection layer are sequentially formed on the front side of the aforementioned crystalline silicon substrate. The specific process is conventional technology in this field and will not be described in detail here. The first passivation layer passesivates the silicon-oxygen dangling bonds on the front side of the crystalline silicon substrate through chemical bonding. The antireflection layer blocks light reflected from the upper surface of the crystalline silicon by controlling its material and thickness. The material of the first passivation layer is not particularly limited, and may include, but is not limited to, a-Si, polycrystalline silicon, microcrystalline silicon, and silicon oxide. The material of the antireflection layer includes, but is not limited to, silicon nitride.

[0064] S300: A second passivation layer is formed on the back side of the aforementioned crystalline silicon substrate.

[0065] In this step, a second passivation layer is formed on the back side of the aforementioned crystalline silicon substrate. The specific process is conventional in the art and will not be described in detail here. The function of the second passivation layer is to passivate the silicon-oxygen dangling bonds on the back side of the crystalline silicon substrate through chemical bonding. The material of the second passivation layer is not particularly limited, and may include, but is not limited to, a-Si, polycrystalline silicon, microcrystalline silicon, and silicon oxide.

[0066] S400: An isolation layer is formed on the surface of the second passivation layer away from the aforementioned crystalline silicon substrate. The isolation layer corresponding to the regions of the multiple sub-electron transport layers is removed to prepare multiple sub-electron transport layers.

[0067] In this step, an isolation layer (e.g., a mask layer) is formed on the surface of the second passivation layer away from the aforementioned crystalline silicon substrate. The mask layer corresponding to multiple sub-electron transport layers is removed by exposure, exposing a portion of the second passivation layer. Multiple sub-electron transport layers are then fabricated on the exposed surface of the second passivation layer. For example, phosphorus diffusion (forming an electron transport layer) can be performed in the phosphorus diffusion region where the mask layer has been removed. Because other regions are protected by the mask layer, several independent N-type doped regions are formed in the phosphorus diffusion region. Then, a mask layer of a certain thickness is grown on the surface of the electron transport layer to prevent it from being affected when a hole transport layer is subsequently formed.

[0068] S500: Remove the isolation layer in the corresponding regions of multiple sub-hole transport layers to prepare multiple sub-hole transport layers.

[0069] In this step, the isolation layer (e.g., a mask layer) corresponding to the regions of the multiple sub-hole transport layers is removed to expose the remaining second passivation layer. Multiple sub-hole transport layers are then prepared on the exposed surface of the second passivation layer, with the sub-hole transport layers and the sub-electron transport layers spaced apart.

[0070] The above-mentioned sub-hole transport layer is prepared by: under the action of a salt oxidant with an oxidation potential of 0.6-0.9V, the monomers of the polymer material are gradually polymerized by gas phase synthesis. The polymer monomers are oxidized into free radicals and are arranged and filled in the spacer region in one step through the gradual polymerization reaction, thereby synthesizing multiple sub-hole transport layers.

[0071] According to another specific embodiment of the present invention, the above-mentioned salt oxidant is selected from Fe 3+ Salts and Ag + At least one type of salt, thus, the above-mentioned salt oxidants are highly efficient at initiating monomer polymerization reactions. Specifically, the specific types of the above-mentioned salt oxidants are not particularly limited; as some specific examples, the above-mentioned Fe... 3+ The salts are selected from at least one of FeCl3, FeBr3, FeI3, FeTos, Fe2(SO4)3, Fe2(NO3)3, Fe2O3 and FeOOH.

[0072] After forming multiple sub-hole transport layers, the above method further includes: removing the mask layer from the entire silicon wafer surface, and then using metallization paste to form main gate lines 8 and sub-gate lines 7 on the main gate region and sub-gate region of the P-type doped region (hole transport layer) and N-type doped region (electron transport layer), respectively. After sintering, a single IBC / HBC cell is formed. (Refer to Appendix) Figure 1 .

[0073] According to the method of this invention, by alternating between the sub-hole transport layer and the sub-electron transport layer, the gradual polymerization reaction of the polymer material in each sub-hole transport layer is kinetically restricted, and the polymer materials can only be arranged regularly in the template (i.e., between adjacent sub-electron transport layers). This results in highly ordered polymer chains, i.e., highly crystalline polymer materials, which improves the crystallinity of each sub-hole transport layer, thereby significantly increasing the carrier mobility and conductivity of each sub-hole transport layer. Furthermore, this method is simple and easy to implement.

[0074] The embodiments of the present invention are described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, unless otherwise specified, all reagents used in the following embodiments are commercially available or can be synthesized according to the methods described herein or known to others. For reaction conditions not listed, they are also readily available to those skilled in the art.

[0075] Example 1

[0076] This embodiment provides an IBC solar cell, the preparation method of which is as follows:

[0077] 1) A 160μm thick crystalline silicon substrate is provided. The crystalline silicon substrate is texturized, and a first passivation layer with a thickness of 10nm (made of SiO2) and an antireflection layer with a thickness of 200nm (made of SiN) are sequentially formed on the front side of the texturized crystalline silicon substrate. x ).

[0078] 2): A second passivation layer with a thickness of 10 nm (made of SiO2) is sequentially formed on the back side of the texturized crystalline silicon substrate, and a mask layer with a thickness of 30 nm (made of PCB photoresist) is formed on the surface of the second passivation layer.

[0079] 3): The mask layer corresponding to multiple sub-electron transport layers is removed by exposure, exposing part of the second passivation layer. Phosphorus diffusion is then performed on the exposed surface of the second passivation layer to form multiple sub-electron transport layers (made of a-Si(P+)). Each sub-electron transport layer has a width of 1 μm and a thickness of 100 nm. Because other regions are protected by the mask layer, several independent N-type doped regions are formed in the phosphorus diffusion region. Then, another mask layer is grown.

[0080] 4) Remove the mask layer corresponding to the regions of multiple sub-hole transport layers to expose the remaining second passivation layer. Load P-type doped material PEDOT onto the surface of the exposed second passivation layer to form multiple sub-hole transport layers, with the sub-hole transport layers and sub-electron transport layers spaced apart. The width d of a single sub-hole transport layer is 100 nm, and the thickness h is 20 nm.

[0081] 5): Remove the mask layer from the entire silicon wafer.

[0082] 6): Metallization paste is used to form main grid lines and sub-grid lines on the main grid region and sub-grid region of P-type doped region and N-type doped region, and after sintering, a single IBC cell is formed.

[0083] The hole mobility of the PEDOT transport layer prepared in this embodiment was found to be 8 cm⁻¹. 2 / Vs, conductivity 3000S / cm.

[0084] Example 2

[0085] This embodiment provides an IBC solar cell. The only difference between this embodiment and Embodiment 1 is that:

[0086] 4) The width of a single subhole transport layer is d = 200 nm and the thickness is h = 12 nm.

[0087] All other steps are the same as in Example 1.

[0088] The hole mobility of the PEDOT transport layer prepared in this embodiment was found to be 30 cm⁻¹.2 / Vs, with an electrical conductivity of 9000 S / cm.

[0089] Example 3

[0090] This embodiment provides an IBC solar cell. The only difference between this embodiment and Embodiment 1 is that:

[0091] 4) The width of a single subhole transport layer is d = 500 nm and the thickness is h = 15 nm.

[0092] All other steps are the same as in Example 1.

[0093] The hole mobility of the PEDOT transport layer prepared in this embodiment was found to be 10 cm⁻¹. 2 / Vs, conductivity 7500 S / cm.

[0094] Example 4

[0095] This embodiment provides an IBC solar cell. The only difference between this embodiment and Embodiment 1 is that:

[0096] 4) The hole transport layer is made of P3HT, and the width of a single sub-hole transport layer is d = 150 nm and the thickness is h = 10 nm.

[0097] All other steps are the same as in Example 1.

[0098] The hole mobility of the P3HT transport layer prepared in this embodiment was found to be 90 cm⁻¹. 2 / Vs, conductivity 3500 S / cm.

[0099] Example 5

[0100] This embodiment provides an IBC solar cell. The only difference between this embodiment and Embodiment 4 is that:

[0101] 4) The width of a single subhole transport layer is d = 500 nm and the thickness is h = 20 nm.

[0102] All other steps are the same as in Example 4.

[0103] The hole mobility of the P3HT transport layer prepared in this embodiment was found to be 30 cm⁻¹. 2 / Vs, with an electrical conductivity of 1000 S / cm.

[0104] Example 6

[0105] This embodiment provides an IBC solar cell. The only difference between this embodiment and Embodiment 4 is that:

[0106] 4) The width of a single subhole transport layer is d = 300 nm and the thickness is h = 20 nm.

[0107] All other steps are the same as in Example 4.

[0108] The hole mobility of the P3HT transport layer prepared in this embodiment was tested to be 70 cm⁻¹. 2 / Vs, conductivity 2000 S / cm.

[0109] Comparative Example 1

[0110] The only difference between this comparative example and Example 1 is that:

[0111] 4) The width of a single subhole transport layer is d = 200 μm and the thickness is h = 85 nm.

[0112] All other steps are the same as in Example 1.

[0113] The hole mobility of the PEDOT transport layer prepared in this comparative example was found to be 5 cm. 2 / Vs, conductivity 1500S / cm.

[0114] Comparative Example 2

[0115] The only difference between this comparative example and Example 4 is that:

[0116] 4) The width of a single subhole transport layer is d = 200 μm and the thickness is h = 85 nm.

[0117] All other steps are the same as in Example 1.

[0118] The hole mobility of the P3HT transport layer prepared in this comparative example was found to be 20 cm⁻¹. 2 / Vs, conductivity 1000S / cm.

[0119] Comparative Example 3

[0120] This comparative example uses conventional methods to prepare electron transport layers and hole transport layers, including:

[0121] 1) A 160μm thick crystalline silicon substrate is provided. The crystalline silicon substrate is texturized, and a first passivation layer with a thickness of 10nm (made of SiO2) and an antireflection layer with a thickness of 200nm (made of SiN) are sequentially formed on the front side of the texturized crystalline silicon substrate. x ).

[0122] 2): A second passivation layer with a thickness of 10 nm (the material is SiO2) is formed on the back side of the texturized crystalline silicon substrate.

[0123] 3): BBr3 tubular diffusion is performed on the exposed surface of the second passivation layer to form the overall hole transport layer.

[0124] 4) A 30nm thick mask layer (made of PCB photoresist) is formed on the surface of the total hole transport layer. The mask layer and hole transport layer corresponding to the multiple sub-electron transport layers are removed to expose the second passivation layer. POCl3 is then diffused in a tubular manner on the exposed second passivation layer surface to form multiple sub-electron transport layers, with the sub-hole transport layers spaced apart. The width d of a single sub-hole transport layer is 200μm, and the thickness h is 200nm.

[0125] All other contents are the same as in Example 1.

[0126] The hole mobility of the P3HT transport layer prepared in this comparative example was measured to be 0.01 cm⁻¹. 2 / Vs, conductivity 10S / cm.

[0127] It can be seen that the hole mobility and conductivity of the hole transport layers prepared in Examples 1-6 of this invention are relatively high. Comparing Example 1 and Comparative Example 1, it can be seen that when the width and thickness of a single sub-PEDOT hole transport layer are too large, its hole mobility and conductivity decrease significantly. Comparing Example 4 and Comparative Example 2, it can be seen that when the width and thickness of a single sub-P3HT hole transport layer are too large, its hole mobility and conductivity decrease significantly. Comparing Example 1 and Comparative Example 3, it can be seen that the hole mobility and conductivity of the hole transport layer prepared using the conventional method are significantly reduced.

[0128] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0129] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An IBC / HBC battery based on a high hole mobility material, characterized in that, include: A crystalline silicon substrate having opposing front and back sides; A first passivation layer is provided on the front side of the crystalline silicon substrate. An anti-reflection layer, the anti-reflection layer being located on the surface of the first passivation layer away from the crystalline silicon substrate layer; A second passivation layer is provided on the back side of the crystalline silicon substrate. A hole transport layer, comprising multiple sub-hole transport layers; wherein, the hole transport layer is used to synthesize polymer materials by stepwise polymerization of monomers in a gas-phase synthesis method under the action of an oxidant; An electron transport layer, comprising a plurality of sub-electron transport layers, wherein the sub-hole transport layers are spaced apart on the surface of the second passivation layer away from the crystalline silicon substrate; the hole transport layer is made of a polymer material, and the space between adjacent sub-electron transport layers serves as a template, such that the polymer material of the sub-hole transport layers is regularly arranged in the template.

2. The IBC / HBC battery based on a high hole mobility material according to claim 1, characterized in that, The width of a single subhole transport layer is no greater than 90µm.

3. The IBC / HBC battery based on a high hole mobility material according to claim 2, characterized in that, The width of a single subhole transport layer is no greater than 50µm.

4. The IBC / HBC battery based on a high hole mobility material according to claim 3, characterized in that, The width of a single sub-hole transport layer is 100~200nm.

5. The IBC / HBC battery based on a high hole mobility material according to any one of claims 2-4, characterized in that, The thickness of a single sub-hole transport layer is no greater than 50 nm.

6. The IBC / HBC battery based on a high hole mobility material according to claim 5, characterized in that, The thickness of a single subhole transport layer is no greater than 20 nm.

7. The IBC / HBC battery based on a high hole mobility material according to claim 1, characterized in that, The hole transport layer is made of a P-type polymer, which is selected from at least one of PTAA, PEDOT, and P3HT.

8. The IBC / HBC battery based on a high hole mobility material according to claim 7, characterized in that, The crystallinity of the hole transport layer is 50-100%.

9. The IBC / HBC battery based on a high hole mobility material according to claim 8, characterized in that, The crystallinity of the hole transport layer is 80-100%.

10. The IBC / HBC battery based on a high hole mobility material according to claim 7, characterized in that, The hole mobility of the hole transport layer formed from the PEDOT material is 5~30 cm. 2 / Vs, conductivity 1000~9000 S / cm.

11. The IBC / HBC battery based on a high hole mobility material according to claim 7, characterized in that, The hole mobility of the hole transport layer formed from the P3HT material is 20~100 cm. 2 / Vs, with an electrical conductivity of 1000~4000 S / cm.

12. A method for preparing an IBC / HBC battery based on a high hole mobility material as described in any one of claims 1 to 11, characterized in that, include: (1) A crystalline silicon substrate layer is provided, the crystalline silicon substrate layer having opposing front and back sides; (2) A first passivation layer and an anti-reflection layer are sequentially formed on the front side of the crystalline silicon substrate; (3) A second passivation layer is formed on the back side of the crystalline silicon substrate; (4) An isolation layer is formed on the surface of the second passivation layer away from the crystalline silicon substrate layer, and the isolation layer corresponding to the multiple sub-electron transport layers is removed to prepare multiple sub-electron transport layers; (5) Remove the isolation layer in the corresponding region of multiple sub-hole transport layers to prepare multiple sub-hole transport layers, such that the sub-hole transport layers and the sub-electron transport layers are spaced apart; The method for preparing the sub-hole transport layer is as follows: Under the action of an oxidant, the monomers of the polymer material are gradually polymerized using a gas-phase synthesis method to synthesize multiple sub-hole transport layers.

13. The method according to claim 12, characterized in that, Also includes: Before forming the first passivation layer on the front side of the crystalline silicon substrate, the crystalline silicon substrate is texturized to form pyramid-like structures on the front and back sides, respectively.

14. The method according to claim 12, characterized in that, The oxidant is a salt oxidant with an oxidation potential of 0.6-0.9 V.

15. The method according to claim 14, characterized in that, The salt oxidant is selected from Fe 3+ Salts and Ag + At least one of the salts.

16. The method according to claim 15, characterized in that, The Fe 3+ The salts are selected from at least one of FeCl3, FeBr3, FeI3, FeTos, Fe2(SO4)3, Fe2(NO3)3, Fe2O3 and FeOOH.

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